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7
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <asm/titan_dep.h>
13
14extern struct pci_ops titan_pci_ops;
15
16static struct resource py_mem_resource = {
17 .start = 0xe0000000UL,
18 .end = 0xe3ffffffUL,
19 .name = "Titan PCI MEM",
20 .flags = IORESOURCE_MEM
21};
22
23
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26
27
28#define TITAN_IO_SIZE 0x0000ffffUL
29#define TITAN_IO_BASE 0xe8000000UL
30
31static struct resource py_io_resource = {
32 .start = 0x00001000UL,
33 .end = TITAN_IO_SIZE - 1,
34 .name = "Titan IO MEM",
35 .flags = IORESOURCE_IO,
36};
37
38static struct pci_controller py_controller = {
39 .pci_ops = &titan_pci_ops,
40 .mem_resource = &py_mem_resource,
41 .mem_offset = 0x00000000UL,
42 .io_resource = &py_io_resource,
43 .io_offset = 0x00000000UL
44};
45
46static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
47
48static int __init pmc_yosemite_setup(void)
49{
50 unsigned long io_v_base;
51
52 io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
53 if (!io_v_base)
54 panic(ioremap_failed);
55
56 set_io_port_base(io_v_base);
57 TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
58
59 ioport_resource.end = TITAN_IO_SIZE - 1;
60
61 register_pci_controller(&py_controller);
62
63 return 0;
64}
65
66arch_initcall(pmc_yosemite_setup);
67