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19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/smp.h>
22#include <linux/kernel_stat.h>
23
24#include <asm/mmu_context.h>
25#include <asm/io.h>
26#include <asm/fw/cfe/cfe_api.h>
27#include <asm/sibyte/sb1250.h>
28#include <asm/sibyte/bcm1480_regs.h>
29#include <asm/sibyte/bcm1480_int.h>
30
31extern void smp_call_function_interrupt(void);
32
33
34
35
36
37
38static void *mailbox_0_set_regs[] = {
39 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
40 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
41 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
42 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
43};
44
45static void *mailbox_0_clear_regs[] = {
46 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
47 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
48 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
49 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
50};
51
52static void *mailbox_0_regs[] = {
53 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
54 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
55 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
56 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
57};
58
59
60
61
62void __cpuinit bcm1480_smp_init(void)
63{
64 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
65 STATUSF_IP1 | STATUSF_IP0;
66
67
68 change_c0_status(ST0_IM, imask);
69}
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79
80static void bcm1480_send_ipi_single(int cpu, unsigned int action)
81{
82 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
83}
84
85static void bcm1480_send_ipi_mask(const struct cpumask *mask,
86 unsigned int action)
87{
88 unsigned int i;
89
90 for_each_cpu(i, mask)
91 bcm1480_send_ipi_single(i, action);
92}
93
94
95
96
97static void __cpuinit bcm1480_init_secondary(void)
98{
99 extern void bcm1480_smp_init(void);
100
101 bcm1480_smp_init();
102}
103
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107
108static void __cpuinit bcm1480_smp_finish(void)
109{
110 extern void sb1480_clockevent_init(void);
111
112 sb1480_clockevent_init();
113 local_irq_enable();
114}
115
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118
119static void bcm1480_cpus_done(void)
120{
121}
122
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126
127static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle)
128{
129 int retval;
130
131 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
132 __KSTK_TOS(idle),
133 (unsigned long)task_thread_info(idle), 0);
134 if (retval != 0)
135 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
136}
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143
144
145static void __init bcm1480_smp_setup(void)
146{
147 int i, num;
148
149 cpus_clear(cpu_possible_map);
150 cpu_set(0, cpu_possible_map);
151 __cpu_number_map[0] = 0;
152 __cpu_logical_map[0] = 0;
153
154 for (i = 1, num = 0; i < NR_CPUS; i++) {
155 if (cfe_cpu_stop(i) == 0) {
156 cpu_set(i, cpu_possible_map);
157 __cpu_number_map[i] = ++num;
158 __cpu_logical_map[num] = i;
159 }
160 }
161 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
162}
163
164static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
165{
166}
167
168struct plat_smp_ops bcm1480_smp_ops = {
169 .send_ipi_single = bcm1480_send_ipi_single,
170 .send_ipi_mask = bcm1480_send_ipi_mask,
171 .init_secondary = bcm1480_init_secondary,
172 .smp_finish = bcm1480_smp_finish,
173 .cpus_done = bcm1480_cpus_done,
174 .boot_secondary = bcm1480_boot_secondary,
175 .smp_setup = bcm1480_smp_setup,
176 .prepare_cpus = bcm1480_prepare_cpus,
177};
178
179void bcm1480_mailbox_interrupt(void)
180{
181 int cpu = smp_processor_id();
182 int irq = K_BCM1480_INT_MBOX_0_0;
183 unsigned int action;
184
185 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
186
187 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
188
189
190 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
191
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196
197 if (action & SMP_CALL_FUNCTION)
198 smp_call_function_interrupt();
199}
200