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18#ifndef __ASM_POWERPC_IMMAP_86XX_H__
19#define __ASM_POWERPC_IMMAP_86XX_H__
20#ifdef __KERNEL__
21
22
23struct ccsr_guts {
24 __be32 porpllsr;
25 __be32 porbmsr;
26 __be32 porimpscr;
27 __be32 pordevsr;
28 __be32 pordbgmsr;
29 u8 res1[0x20 - 0x14];
30 __be32 porcir;
31 u8 res2[0x30 - 0x24];
32 __be32 gpiocr;
33 u8 res3[0x40 - 0x34];
34 __be32 gpoutdr;
35 u8 res4[0x50 - 0x44];
36 __be32 gpindr;
37 u8 res5[0x60 - 0x54];
38 __be32 pmuxcr;
39 u8 res6[0x70 - 0x64];
40 __be32 devdisr;
41 __be32 devdisr2;
42 u8 res7[0x80 - 0x78];
43 __be32 powmgtcsr;
44 u8 res8[0x90 - 0x84];
45 __be32 mcpsumr;
46 __be32 rstrscr;
47 u8 res9[0xA0 - 0x98];
48 __be32 pvr;
49 __be32 svr;
50 u8 res10[0xB0 - 0xA8];
51 __be32 rstcr;
52 u8 res11[0xC0 - 0xB4];
53 __be32 elbcvselcr;
54 u8 res12[0x800 - 0xC4];
55 __be32 clkdvdr;
56 u8 res13[0x900 - 0x804];
57 __be32 ircr;
58 u8 res14[0x908 - 0x904];
59 __be32 dmacr;
60 u8 res15[0x914 - 0x90C];
61 __be32 elbccr;
62 u8 res16[0xB20 - 0x918];
63 __be32 ddr1clkdr;
64 __be32 ddr2clkdr;
65 __be32 ddrclkdr;
66 u8 res17[0xE00 - 0xB2C];
67 __be32 clkocr;
68 u8 res18[0xE10 - 0xE04];
69 __be32 ddrdllcr;
70 u8 res19[0xE20 - 0xE14];
71 __be32 lbcdllcr;
72 u8 res20[0xF04 - 0xE24];
73 __be32 srds1cr0;
74 __be32 srds1cr1;
75 u8 res21[0xF40 - 0xF0C];
76 __be32 srds2cr0;
77 __be32 srds2cr1;
78} __attribute__ ((packed));
79
80#define CCSR_GUTS_DMACR_DEV_SSI 0
81#define CCSR_GUTS_DMACR_DEV_IR 1
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96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device)
98{
99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102}
103
104#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
105#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000
106#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000
107#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000
108#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000
109#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000
110#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000
111#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000
112#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000
113#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000
114#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400
115#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200
116#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
117#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
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132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
133 unsigned int co, unsigned int ch, unsigned int value)
134{
135 if ((ch == 0) || (ch == 3)) {
136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
137
138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
139 }
140}
141
142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
145#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
146#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
147#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
148 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
149#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
150#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
151#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
152#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
153#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
154
155#endif
156#endif
157