1#ifndef _ASM_POWERPC_PTRACE_H 2#define _ASM_POWERPC_PTRACE_H 3 4/* 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This struct defines the way the registers are stored on the 8 * kernel stack during a system call or other kernel entry. 9 * 10 * this should only contain volatile regs 11 * since we can keep non-volatile in the thread_struct 12 * should set this up when only volatiles are saved 13 * by intr code. 14 * 15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 16 * that the overall structure is a multiple of 16 bytes in length. 17 * 18 * Note that the offsets of the fields in this struct correspond with 19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License 23 * as published by the Free Software Foundation; either version 24 * 2 of the License, or (at your option) any later version. 25 */ 26 27#ifndef __ASSEMBLY__ 28 29struct pt_regs { 30 unsigned long gpr[32]; 31 unsigned long nip; 32 unsigned long msr; 33 unsigned long orig_gpr3; /* Used for restarting system calls */ 34 unsigned long ctr; 35 unsigned long link; 36 unsigned long xer; 37 unsigned long ccr; 38#ifdef __powerpc64__ 39 unsigned long softe; /* Soft enabled/disabled */ 40#else 41 unsigned long mq; /* 601 only (not used at present) */ 42 /* Used on APUS to hold IPL value. */ 43#endif 44 unsigned long trap; /* Reason for being here */ 45 /* N.B. for critical exceptions on 4xx, the dar and dsisr 46 fields are overloaded to hold srr0 and srr1. */ 47 unsigned long dar; /* Fault registers */ 48 unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 49 unsigned long result; /* Result of a system call */ 50}; 51 52#endif /* __ASSEMBLY__ */ 53 54#ifdef __KERNEL__ 55 56#ifdef __powerpc64__ 57 58#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 59#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ 60#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) 61#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ 62 STACK_FRAME_OVERHEAD + 288) 63#define STACK_FRAME_MARKER 12 64 65/* Size of dummy stack frame allocated when calling signal handler. */ 66#define __SIGNAL_FRAMESIZE 128 67#define __SIGNAL_FRAMESIZE32 64 68 69#else /* __powerpc64__ */ 70 71#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 72#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ 73#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) 74#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD) 75#define STACK_FRAME_MARKER 2 76 77/* Size of stack frame allocated when calling signal handler. */ 78#define __SIGNAL_FRAMESIZE 64 79 80#endif /* __powerpc64__ */ 81 82#ifndef __ASSEMBLY__ 83 84#define instruction_pointer(regs) ((regs)->nip) 85#define user_stack_pointer(regs) ((regs)->gpr[1]) 86#define regs_return_value(regs) ((regs)->gpr[3]) 87 88#ifdef CONFIG_SMP 89extern unsigned long profile_pc(struct pt_regs *regs); 90#else 91#define profile_pc(regs) instruction_pointer(regs) 92#endif 93 94#ifdef __powerpc64__ 95#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) 96#else 97#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) 98#endif 99 100#define force_successful_syscall_return() \ 101 do { \ 102 set_thread_flag(TIF_NOERROR); \ 103 } while(0) 104 105struct task_struct; 106extern unsigned long ptrace_get_reg(struct task_struct *task, int regno); 107extern int ptrace_put_reg(struct task_struct *task, int regno, 108 unsigned long data); 109 110/* 111 * We use the least-significant bit of the trap field to indicate 112 * whether we have saved the full set of registers, or only a 113 * partial set. A 1 there means the partial set. 114 * On 4xx we use the next bit to indicate whether the exception 115 * is a critical exception (1 means it is). 116 */ 117#define FULL_REGS(regs) (((regs)->trap & 1) == 0) 118#ifndef __powerpc64__ 119#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) 120#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) 121#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) 122#endif /* ! __powerpc64__ */ 123#define TRAP(regs) ((regs)->trap & ~0xF) 124#ifdef __powerpc64__ 125#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) 126#else 127#define CHECK_FULL_REGS(regs) \ 128do { \ 129 if ((regs)->trap & 1) \ 130 printk(KERN_CRIT "%s: partial register set\n", __func__); \ 131} while (0) 132#endif /* __powerpc64__ */ 133 134/* 135 * These are defined as per linux/ptrace.h, which see. 136 */ 137#define arch_has_single_step() (1) 138#define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601)) 139extern void user_enable_single_step(struct task_struct *); 140extern void user_enable_block_step(struct task_struct *); 141extern void user_disable_single_step(struct task_struct *); 142 143#endif /* __ASSEMBLY__ */ 144 145#endif /* __KERNEL__ */ 146 147/* 148 * Offsets used by 'ptrace' system call interface. 149 * These can't be changed without breaking binary compatibility 150 * with MkLinux, etc. 151 */ 152#define PT_R0 0 153#define PT_R1 1 154#define PT_R2 2 155#define PT_R3 3 156#define PT_R4 4 157#define PT_R5 5 158#define PT_R6 6 159#define PT_R7 7 160#define PT_R8 8 161#define PT_R9 9 162#define PT_R10 10 163#define PT_R11 11 164#define PT_R12 12 165#define PT_R13 13 166#define PT_R14 14 167#define PT_R15 15 168#define PT_R16 16 169#define PT_R17 17 170#define PT_R18 18 171#define PT_R19 19 172#define PT_R20 20 173#define PT_R21 21 174#define PT_R22 22 175#define PT_R23 23 176#define PT_R24 24 177#define PT_R25 25 178#define PT_R26 26 179#define PT_R27 27 180#define PT_R28 28 181#define PT_R29 29 182#define PT_R30 30 183#define PT_R31 31 184 185#define PT_NIP 32 186#define PT_MSR 33 187#define PT_ORIG_R3 34 188#define PT_CTR 35 189#define PT_LNK 36 190#define PT_XER 37 191#define PT_CCR 38 192#ifndef __powerpc64__ 193#define PT_MQ 39 194#else 195#define PT_SOFTE 39 196#endif 197#define PT_TRAP 40 198#define PT_DAR 41 199#define PT_DSISR 42 200#define PT_RESULT 43 201#define PT_REGS_COUNT 44 202 203#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 204 205#ifndef __powerpc64__ 206 207#define PT_FPR31 (PT_FPR0 + 2*31) 208#define PT_FPSCR (PT_FPR0 + 2*32 + 1) 209 210#else /* __powerpc64__ */ 211 212#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 213 214#ifdef __KERNEL__ 215#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */ 216#endif 217 218#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ 219#define PT_VSCR (PT_VR0 + 32*2 + 1) 220#define PT_VRSAVE (PT_VR0 + 33*2) 221 222#ifdef __KERNEL__ 223#define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */ 224#define PT_VSCR_32 (PT_VR0 + 32*4 + 3) 225#define PT_VRSAVE_32 (PT_VR0 + 33*4) 226#endif 227 228/* 229 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 230 */ 231#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ 232#define PT_VSR31 (PT_VSR0 + 2*31) 233#ifdef __KERNEL__ 234#define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */ 235#endif 236#endif /* __powerpc64__ */ 237 238/* 239 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 240 * The transfer totals 34 quadword. Quadwords 0-31 contain the 241 * corresponding vector registers. Quadword 32 contains the vscr as the 242 * last word (offset 12) within that quadword. Quadword 33 contains the 243 * vrsave as the first word (offset 0) within the quadword. 244 * 245 * This definition of the VMX state is compatible with the current PPC32 246 * ptrace interface. This allows signal handling and ptrace to use the same 247 * structures. This also simplifies the implementation of a bi-arch 248 * (combined (32- and 64-bit) gdb. 249 */ 250#define PTRACE_GETVRREGS 18 251#define PTRACE_SETVRREGS 19 252 253/* Get/set all the upper 32-bits of the SPE registers, accumulator, and 254 * spefscr, in one go */ 255#define PTRACE_GETEVRREGS 20 256#define PTRACE_SETEVRREGS 21 257 258/* Get the first 32 128bit VSX registers */ 259#define PTRACE_GETVSRREGS 27 260#define PTRACE_SETVSRREGS 28 261 262/* 263 * Get or set a debug register. The first 16 are DABR registers and the 264 * second 16 are IABR registers. 265 */ 266#define PTRACE_GET_DEBUGREG 25 267#define PTRACE_SET_DEBUGREG 26 268 269/* (new) PTRACE requests using the same numbers as x86 and the same 270 * argument ordering. Additionally, they support more registers too 271 */ 272#define PTRACE_GETREGS 12 273#define PTRACE_SETREGS 13 274#define PTRACE_GETFPREGS 14 275#define PTRACE_SETFPREGS 15 276#define PTRACE_GETREGS64 22 277#define PTRACE_SETREGS64 23 278 279/* (old) PTRACE requests with inverted arguments */ 280#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */ 281#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */ 282#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */ 283#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */ 284 285/* Calls to trace a 64bit program from a 32bit program */ 286#define PPC_PTRACE_PEEKTEXT_3264 0x95 287#define PPC_PTRACE_PEEKDATA_3264 0x94 288#define PPC_PTRACE_POKETEXT_3264 0x93 289#define PPC_PTRACE_POKEDATA_3264 0x92 290#define PPC_PTRACE_PEEKUSR_3264 0x91 291#define PPC_PTRACE_POKEUSR_3264 0x90 292 293#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 294 295#endif /* _ASM_POWERPC_PTRACE_H */ 296