LXR linux/arch/powerpc/kernel/mpc7450-pmu.c

   1/*
   2 * Performance counter support for MPC7450-family processors.
   3 *
   4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version
   9 * 2 of the License, or (at your option) any later version.
  10 */
  11#include <linux/string.h>
  12#include <linux/perf_event.h>
  13#include <asm/reg.h>
  14#include <asm/cputable.h>
  15
  16#define N_COUNTER       6       /* Number of hardware counters */
  17#define MAX_ALT         3       /* Maximum number of event alternative codes */
  18
  19/*
  20 * Bits in event code for MPC7450 family
  21 */
  22#define PM_THRMULT_MSKS 0x40000
  23#define PM_THRESH_SH    12
  24#define PM_THRESH_MSK   0x3f
  25#define PM_PMC_SH       8
  26#define PM_PMC_MSK      7
  27#define PM_PMCSEL_MSK   0x7f
  28
  29/*
  30 * Classify events according to how specific their PMC requirements are.
  31 * Result is:
  32 *      0: can go on any PMC
  33 *      1: can go on PMCs 1-4
  34 *      2: can go on PMCs 1,2,4
  35 *      3: can go on PMCs 1 or 2
  36 *      4: can only go on one PMC
  37 *      -1: event code is invalid
  38 */
  39#define N_CLASSES       5
  40
  41static int mpc7450_classify_event(u32 event)
  42{
  43        int pmc;
  44
  45        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
  46        if (pmc) {
  47                if (pmc > N_COUNTER)
  48                        return -1;
  49                return 4;
  50        }
  51        event &= PM_PMCSEL_MSK;
  52        if (event <= 1)
  53                return 0;
  54        if (event <= 7)
  55                return 1;
  56        if (event <= 13)
  57                return 2;
  58        if (event <= 22)
  59                return 3;
  60        return -1;
  61}
  62
  63/*
  64 * Events using threshold and possible threshold scale:
  65 *      code    scale?  name
  66 *      11e     N       PM_INSTQ_EXCEED_CYC
  67 *      11f     N       PM_ALTV_IQ_EXCEED_CYC
  68 *      128     Y       PM_DTLB_SEARCH_EXCEED_CYC
  69 *      12b     Y       PM_LD_MISS_EXCEED_L1_CYC
  70 *      220     N       PM_CQ_EXCEED_CYC
  71 *      30c     N       PM_GPR_RB_EXCEED_CYC
  72 *      30d     ?       PM_FPR_IQ_EXCEED_CYC ?
  73 *      311     Y       PM_ITLB_SEARCH_EXCEED
  74 *      410     N       PM_GPR_IQ_EXCEED_CYC
  75 */
  76
  77/*
  78 * Return use of threshold and threshold scale bits:
  79 * 0 = uses neither, 1 = uses threshold, 2 = uses both
  80 */
  81static int mpc7450_threshold_use(u32 event)
  82{
  83        int pmc, sel;
  84
  85        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
  86        sel = event & PM_PMCSEL_MSK;
  87        switch (pmc) {
  88        case 1:
  89                if (sel == 0x1e || sel == 0x1f)
  90                        return 1;
  91                if (sel == 0x28 || sel == 0x2b)
  92                        return 2;
  93                break;
  94        case 2:
  95                if (sel == 0x20)
  96                        return 1;
  97                break;
  98        case 3:
  99                if (sel == 0xc || sel == 0xd)
 100                        return 1;
 101                if (sel == 0x11)
 102                        return 2;
 103                break;
 104        case 4:
 105                if (sel == 0x10)
 106                        return 1;
 107                break;
 108        }
 109        return 0;
 110}
 111
 112/*
 113 * Layout of constraint bits:
 114 * 33222222222211111111110000000000
 115 * 10987654321098765432109876543210
 116 *  |<    ><  > < > < ><><><><><><>
 117 *  TS TV   G4   G3  G2P6P5P4P3P2P1
 118 *
 119 * P1 - P6
 120 *      0 - 11: Count of events needing PMC1 .. PMC6
 121 *
 122 * G2
 123 *      12 - 14: Count of events needing PMC1 or PMC2
 124 *
 125 * G3
 126 *      16 - 18: Count of events needing PMC1, PMC2 or PMC4
 127 *
 128 * G4
 129 *      20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4
 130 *
 131 * TV
 132 *      24 - 29: Threshold value requested
 133 *
 134 * TS
 135 *      30: Threshold scale value requested
 136 */
 137
 138static u32 pmcbits[N_COUNTER][2] = {
 139        { 0x00844002, 0x00111001 },     /* PMC1 mask, value: P1,G2,G3,G4 */
 140        { 0x00844008, 0x00111004 },     /* PMC2: P2,G2,G3,G4 */
 141        { 0x00800020, 0x00100010 },     /* PMC3: P3,G4 */
 142        { 0x00840080, 0x00110040 },     /* PMC4: P4,G3,G4 */
 143        { 0x00000200, 0x00000100 },     /* PMC5: P5 */
 144        { 0x00000800, 0x00000400 }      /* PMC6: P6 */
 145};
 146
 147static u32 classbits[N_CLASSES - 1][2] = {
 148        { 0x00000000, 0x00000000 },     /* class 0: no constraint */
 149        { 0x00800000, 0x00100000 },     /* class 1: G4 */
 150        { 0x00040000, 0x00010000 },     /* class 2: G3 */
 151        { 0x00004000, 0x00001000 },     /* class 3: G2 */
 152};
 153
 154static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
 155                                  unsigned long *valp)
 156{
 157        int pmc, class;
 158        u32 mask, value;
 159        int thresh, tuse;
 160
 161        class = mpc7450_classify_event(event);
 162        if (class < 0)
 163                return -1;
 164        if (class == 4) {
 165                pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK;
 166                mask  = pmcbits[pmc - 1][0];
 167                value = pmcbits[pmc - 1][1];
 168        } else {
 169                mask  = classbits[class][0];
 170                value = classbits[class][1];
 171        }
 172
 173        tuse = mpc7450_threshold_use(event);
 174        if (tuse) {
 175                thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK;
 176                mask  |= 0x3f << 24;
 177                value |= thresh << 24;
 178                if (tuse == 2) {
 179                        mask |= 0x40000000;
 180                        if ((unsigned int)event & PM_THRMULT_MSKS)
 181                                value |= 0x40000000;
 182                }
 183        }
 184
 185        *maskp = mask;
 186        *valp = value;
 187        return 0;
 188}
 189
 190static const unsigned int event_alternatives[][MAX_ALT] = {
 191        { 0x217, 0x317 },               /* PM_L1_DCACHE_MISS */
 192        { 0x418, 0x50f, 0x60f },        /* PM_SNOOP_RETRY */
 193        { 0x502, 0x602 },               /* PM_L2_HIT */
 194        { 0x503, 0x603 },               /* PM_L3_HIT */
 195        { 0x504, 0x604 },               /* PM_L2_ICACHE_MISS */
 196        { 0x505, 0x605 },               /* PM_L3_ICACHE_MISS */
 197        { 0x506, 0x606 },               /* PM_L2_DCACHE_MISS */
 198        { 0x507, 0x607 },               /* PM_L3_DCACHE_MISS */
 199        { 0x50a, 0x623 },               /* PM_LD_HIT_L3 */
 200        { 0x50b, 0x624 },               /* PM_ST_HIT_L3 */
 201        { 0x50d, 0x60d },               /* PM_L2_TOUCH_HIT */
 202        { 0x50e, 0x60e },               /* PM_L3_TOUCH_HIT */
 203        { 0x512, 0x612 },               /* PM_INT_LOCAL */
 204        { 0x513, 0x61d },               /* PM_L2_MISS */
 205        { 0x514, 0x61e },               /* PM_L3_MISS */
 206};
 207
 208/*
 209 * Scan the alternatives table for a match and return the
 210 * index into the alternatives table if found, else -1.
 211 */
 212static int find_alternative(u32 event)
 213{
 214        int i, j;
 215
 216        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 217                if (event < event_alternatives[i][0])
 218                        break;
 219                for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
 220                        if (event == event_alternatives[i][j])
 221                                return i;
 222        }
 223        return -1;
 224}
 225
 226static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 227{
 228        int i, j, nalt = 1;
 229        u32 ae;
 230
 231        alt[0] = event;
 232        nalt = 1;
 233        i = find_alternative((u32)event);
 234        if (i >= 0) {
 235                for (j = 0; j < MAX_ALT; ++j) {
 236                        ae = event_alternatives[i][j];
 237                        if (ae && ae != (u32)event)
 238                                alt[nalt++] = ae;
 239                }
 240        }
 241        return nalt;
 242}
 243
 244/*
 245 * Bitmaps of which PMCs each class can use for classes 0 - 3.
 246 * Bit i is set if PMC i+1 is usable.
 247 */
 248static const u8 classmap[N_CLASSES] = {
 249        0x3f, 0x0f, 0x0b, 0x03, 0
 250};
 251
 252/* Bit position and width of each PMCSEL field */
 253static const int pmcsel_shift[N_COUNTER] = {
 254        6,      0,      27,     22,     17,     11
 255};
 256static const u32 pmcsel_mask[N_COUNTER] = {
 257        0x7f,   0x3f,   0x1f,   0x1f,   0x1f,   0x3f
 258};
 259
 260/*
 261 * Compute MMCR0/1/2 values for a set of events.
 262 */
 263static int mpc7450_compute_mmcr(u64 event[], int n_ev,
 264                                unsigned int hwc[], unsigned long mmcr[])
 265{
 266        u8 event_index[N_CLASSES][N_COUNTER];
 267        int n_classevent[N_CLASSES];
 268        int i, j, class, tuse;
 269        u32 pmc_inuse = 0, pmc_avail;
 270        u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0;
 271        u32 ev, pmc, thresh;
 272
 273        if (n_ev > N_COUNTER)
 274                return -1;
 275
 276        /* First pass: count usage in each class */
 277        for (i = 0; i < N_CLASSES; ++i)
 278                n_classevent[i] = 0;
 279        for (i = 0; i < n_ev; ++i) {
 280                class = mpc7450_classify_event(event[i]);
 281                if (class < 0)
 282                        return -1;
 283                j = n_classevent[class]++;
 284                event_index[class][j] = i;
 285        }
 286
 287        /* Second pass: allocate PMCs from most specific event to least */
 288        for (class = N_CLASSES - 1; class >= 0; --class) {
 289                for (i = 0; i < n_classevent[class]; ++i) {
 290                        ev = event[event_index[class][i]];
 291                        if (class == 4) {
 292                                pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
 293                                if (pmc_inuse & (1 << (pmc - 1)))
 294                                        return -1;
 295                        } else {
 296                                /* Find a suitable PMC */
 297                                pmc_avail = classmap[class] & ~pmc_inuse;
 298                                if (!pmc_avail)
 299                                        return -1;
 300                                pmc = ffs(pmc_avail);
 301                        }
 302                        pmc_inuse |= 1 << (pmc - 1);
 303
 304                        tuse = mpc7450_threshold_use(ev);
 305                        if (tuse) {
 306                                thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK;
 307                                mmcr0 |= thresh << 16;
 308                                if (tuse == 2 && (ev & PM_THRMULT_MSKS))
 309                                        mmcr2 = 0x80000000;
 310                        }
 311                        ev &= pmcsel_mask[pmc - 1];
 312                        ev <<= pmcsel_shift[pmc - 1];
 313                        if (pmc <= 2)
 314                                mmcr0 |= ev;
 315                        else
 316                                mmcr1 |= ev;
 317                        hwc[event_index[class][i]] = pmc - 1;
 318                }
 319        }
 320
 321        if (pmc_inuse & 1)
 322                mmcr0 |= MMCR0_PMC1CE;
 323        if (pmc_inuse & 0x3e)
 324                mmcr0 |= MMCR0_PMCnCE;
 325
 326        /* Return MMCRx values */
 327        mmcr[0] = mmcr0;
 328        mmcr[1] = mmcr1;
 329        mmcr[2] = mmcr2;
 330        return 0;
 331}
 332
 333/*
 334 * Disable counting by a PMC.
 335 * Note that the pmc argument is 0-based here, not 1-based.
 336 */
 337static void mpc7450_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 338{
 339        if (pmc <= 1)
 340                mmcr[0] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
 341        else
 342                mmcr[1] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
 343}
 344
 345static int mpc7450_generic_events[] = {
 346        [PERF_COUNT_HW_CPU_CYCLES]              = 1,
 347        [PERF_COUNT_HW_INSTRUCTIONS]            = 2,
 348        [PERF_COUNT_HW_CACHE_MISSES]            = 0x217, /* PM_L1_DCACHE_MISS */
 349        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x122, /* PM_BR_CMPL */
 350        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x41c, /* PM_BR_MPRED */
 351};
 352
 353#define C(x)    PERF_COUNT_HW_CACHE_##x
 354
 355/*
 356 * Table of generalized cache-related events.
 357 * 0 means not supported, -1 means nonsensical, other values
 358 * are event codes.
 359 */
 360static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 361        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 362                [C(OP_READ)] = {        0,              0x225   },
 363                [C(OP_WRITE)] = {       0,              0x227   },
 364                [C(OP_PREFETCH)] = {    0,              0       },
 365        },
 366        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 367                [C(OP_READ)] = {        0x129,          0x115   },
 368                [C(OP_WRITE)] = {       -1,             -1      },
 369                [C(OP_PREFETCH)] = {    0x634,          0       },
 370        },
 371        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 372                [C(OP_READ)] = {        0,              0       },
 373                [C(OP_WRITE)] = {       0,              0       },
 374                [C(OP_PREFETCH)] = {    0,              0       },
 375        },
 376        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 377                [C(OP_READ)] = {        0,              0x312   },
 378                [C(OP_WRITE)] = {       -1,             -1      },
 379                [C(OP_PREFETCH)] = {    -1,             -1      },
 380        },
 381        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 382                [C(OP_READ)] = {        0,              0x223   },
 383                [C(OP_WRITE)] = {       -1,             -1      },
 384                [C(OP_PREFETCH)] = {    -1,             -1      },
 385        },
 386        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 387                [C(OP_READ)] = {        0x122,          0x41c   },
 388                [C(OP_WRITE)] = {       -1,             -1      },
 389                [C(OP_PREFETCH)] = {    -1,             -1      },
 390        },
 391};
 392
 393struct power_pmu mpc7450_pmu = {
 394        .name                   = "MPC7450 family",
 395        .n_counter              = N_COUNTER,
 396        .max_alternatives       = MAX_ALT,
 397        .add_fields             = 0x00111555ul,
 398        .test_adder             = 0x00301000ul,
 399        .compute_mmcr           = mpc7450_compute_mmcr,
 400        .get_constraint         = mpc7450_get_constraint,
 401        .get_alternatives       = mpc7450_get_alternatives,
 402        .disable_pmc            = mpc7450_disable_pmc,
 403        .n_generic              = ARRAY_SIZE(mpc7450_generic_events),
 404        .generic_events         = mpc7450_generic_events,
 405        .cache_events           = &mpc7450_cache_events,
 406};
 407
 408static int init_mpc7450_pmu(void)
 409{
 410        if (!cur_cpu_spec->oprofile_cpu_type ||
 411            strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
 412                return -ENODEV;
 413
 414        return register_power_pmu(&mpc7450_pmu);
 415}
 416
 417arch_initcall(init_mpc7450_pmu);
 418