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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29
30#include <asm/processor.h>
31#include <asm/io.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/byteorder.h>
35#include <asm/machdep.h>
36#include <asm/ppc-pci.h>
37#include <asm/firmware.h>
38#include <asm/eeh.h>
39
40static DEFINE_SPINLOCK(hose_spinlock);
41LIST_HEAD(hose_list);
42
43
44static int global_phb_number;
45
46
47resource_size_t isa_mem_base;
48
49
50unsigned int ppc_pci_flags = 0;
51
52
53static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
54
55void set_pci_dma_ops(struct dma_map_ops *dma_ops)
56{
57 pci_dma_ops = dma_ops;
58}
59
60struct dma_map_ops *get_pci_dma_ops(void)
61{
62 return pci_dma_ops;
63}
64EXPORT_SYMBOL(get_pci_dma_ops);
65
66int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
67{
68 return dma_set_mask(&dev->dev, mask);
69}
70
71int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
72{
73 int rc;
74
75 rc = dma_set_mask(&dev->dev, mask);
76 dev->dev.coherent_dma_mask = dev->dma_mask;
77
78 return rc;
79}
80
81struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
82{
83 struct pci_controller *phb;
84
85 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
86 if (phb == NULL)
87 return NULL;
88 spin_lock(&hose_spinlock);
89 phb->global_number = global_phb_number++;
90 list_add_tail(&phb->list_node, &hose_list);
91 spin_unlock(&hose_spinlock);
92 phb->dn = dev;
93 phb->is_dynamic = mem_init_done;
94#ifdef CONFIG_PPC64
95 if (dev) {
96 int nid = of_node_to_nid(dev);
97
98 if (nid < 0 || !node_online(nid))
99 nid = -1;
100
101 PHB_SET_NODE(phb, nid);
102 }
103#endif
104 return phb;
105}
106
107void pcibios_free_controller(struct pci_controller *phb)
108{
109 spin_lock(&hose_spinlock);
110 list_del(&phb->list_node);
111 spin_unlock(&hose_spinlock);
112
113 if (phb->is_dynamic)
114 kfree(phb);
115}
116
117static resource_size_t pcibios_io_size(const struct pci_controller *hose)
118{
119#ifdef CONFIG_PPC64
120 return hose->pci_io_size;
121#else
122 return hose->io_resource.end - hose->io_resource.start + 1;
123#endif
124}
125
126int pcibios_vaddr_is_ioport(void __iomem *address)
127{
128 int ret = 0;
129 struct pci_controller *hose;
130 resource_size_t size;
131
132 spin_lock(&hose_spinlock);
133 list_for_each_entry(hose, &hose_list, list_node) {
134 size = pcibios_io_size(hose);
135 if (address >= hose->io_base_virt &&
136 address < (hose->io_base_virt + size)) {
137 ret = 1;
138 break;
139 }
140 }
141 spin_unlock(&hose_spinlock);
142 return ret;
143}
144
145unsigned long pci_address_to_pio(phys_addr_t address)
146{
147 struct pci_controller *hose;
148 resource_size_t size;
149 unsigned long ret = ~0;
150
151 spin_lock(&hose_spinlock);
152 list_for_each_entry(hose, &hose_list, list_node) {
153 size = pcibios_io_size(hose);
154 if (address >= hose->io_base_phys &&
155 address < (hose->io_base_phys + size)) {
156 unsigned long base =
157 (unsigned long)hose->io_base_virt - _IO_BASE;
158 ret = base + (address - hose->io_base_phys);
159 break;
160 }
161 }
162 spin_unlock(&hose_spinlock);
163
164 return ret;
165}
166EXPORT_SYMBOL_GPL(pci_address_to_pio);
167
168
169
170
171int pci_domain_nr(struct pci_bus *bus)
172{
173 struct pci_controller *hose = pci_bus_to_host(bus);
174
175 return hose->global_number;
176}
177EXPORT_SYMBOL(pci_domain_nr);
178
179
180
181
182
183
184
185
186struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
187{
188 while(node) {
189 struct pci_controller *hose, *tmp;
190 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
191 if (hose->dn == node)
192 return hose;
193 node = node->parent;
194 }
195 return NULL;
196}
197
198static ssize_t pci_show_devspec(struct device *dev,
199 struct device_attribute *attr, char *buf)
200{
201 struct pci_dev *pdev;
202 struct device_node *np;
203
204 pdev = to_pci_dev (dev);
205 np = pci_device_to_OF_node(pdev);
206 if (np == NULL || np->full_name == NULL)
207 return 0;
208 return sprintf(buf, "%s", np->full_name);
209}
210static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
211
212
213int pcibios_add_platform_entries(struct pci_dev *pdev)
214{
215 return device_create_file(&pdev->dev, &dev_attr_devspec);
216}
217
218char __devinit *pcibios_setup(char *str)
219{
220 return str;
221}
222
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226
227
228int pci_read_irq_line(struct pci_dev *pci_dev)
229{
230 struct of_irq oirq;
231 unsigned int virq;
232
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241
242#ifdef CONFIG_PPC_ISERIES
243 if (firmware_has_feature(FW_FEATURE_ISERIES))
244 return -1;
245#endif
246
247 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
248
249#ifdef DEBUG
250 memset(&oirq, 0xff, sizeof(oirq));
251#endif
252
253 if (of_irq_map_pci(pci_dev, &oirq)) {
254 u8 line, pin;
255
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262
263 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
264 return -1;
265 if (pin == 0)
266 return -1;
267 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
268 line == 0xff || line == 0) {
269 return -1;
270 }
271 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
272 line, pin);
273
274 virq = irq_create_mapping(NULL, line);
275 if (virq != NO_IRQ)
276 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
277 } else {
278 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
279 oirq.size, oirq.specifier[0], oirq.specifier[1],
280 oirq.controller ? oirq.controller->full_name :
281 "<default>");
282
283 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
284 oirq.size);
285 }
286 if(virq == NO_IRQ) {
287 pr_debug(" Failed to map !\n");
288 return -1;
289 }
290
291 pr_debug(" Mapped to linux irq %d\n", virq);
292
293 pci_dev->irq = virq;
294
295 return 0;
296}
297EXPORT_SYMBOL(pci_read_irq_line);
298
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315
316static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
317 resource_size_t *offset,
318 enum pci_mmap_state mmap_state)
319{
320 struct pci_controller *hose = pci_bus_to_host(dev->bus);
321 unsigned long io_offset = 0;
322 int i, res_bit;
323
324 if (hose == 0)
325 return NULL;
326
327
328 if (mmap_state == pci_mmap_mem) {
329#if 0
330 *offset += hose->pci_mem_offset;
331#endif
332 res_bit = IORESOURCE_MEM;
333 } else {
334 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
335 *offset += io_offset;
336 res_bit = IORESOURCE_IO;
337 }
338
339
340
341
342
343 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
344 struct resource *rp = &dev->resource[i];
345 int flags = rp->flags;
346
347
348 if (i == PCI_ROM_RESOURCE)
349 flags |= IORESOURCE_MEM;
350
351
352 if ((flags & res_bit) == 0)
353 continue;
354
355
356 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
357 continue;
358
359
360 if (mmap_state == pci_mmap_io)
361 *offset += hose->io_base_phys - io_offset;
362 return rp;
363 }
364
365 return NULL;
366}
367
368
369
370
371
372static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
373 pgprot_t protection,
374 enum pci_mmap_state mmap_state,
375 int write_combine)
376{
377 unsigned long prot = pgprot_val(protection);
378
379
380
381
382
383
384
385 if (mmap_state != pci_mmap_mem)
386 write_combine = 0;
387 else if (write_combine == 0) {
388 if (rp->flags & IORESOURCE_PREFETCH)
389 write_combine = 1;
390 }
391
392
393 if (write_combine)
394 return pgprot_noncached_wc(prot);
395 else
396 return pgprot_noncached(prot);
397}
398
399
400
401
402
403
404pgprot_t pci_phys_mem_access_prot(struct file *file,
405 unsigned long pfn,
406 unsigned long size,
407 pgprot_t prot)
408{
409 struct pci_dev *pdev = NULL;
410 struct resource *found = NULL;
411 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
412 int i;
413
414 if (page_is_ram(pfn))
415 return prot;
416
417 prot = pgprot_noncached(prot);
418 for_each_pci_dev(pdev) {
419 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
420 struct resource *rp = &pdev->resource[i];
421 int flags = rp->flags;
422
423
424 if ((flags & IORESOURCE_MEM) == 0)
425 continue;
426
427 if (offset < (rp->start & PAGE_MASK) ||
428 offset > rp->end)
429 continue;
430 found = rp;
431 break;
432 }
433 if (found)
434 break;
435 }
436 if (found) {
437 if (found->flags & IORESOURCE_PREFETCH)
438 prot = pgprot_noncached_wc(prot);
439 pci_dev_put(pdev);
440 }
441
442 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
443 (unsigned long long)offset, pgprot_val(prot));
444
445 return prot;
446}
447
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458
459int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
460 enum pci_mmap_state mmap_state, int write_combine)
461{
462 resource_size_t offset =
463 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
464 struct resource *rp;
465 int ret;
466
467 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
468 if (rp == NULL)
469 return -EINVAL;
470
471 vma->vm_pgoff = offset >> PAGE_SHIFT;
472 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
473 vma->vm_page_prot,
474 mmap_state, write_combine);
475
476 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
477 vma->vm_end - vma->vm_start, vma->vm_page_prot);
478
479 return ret;
480}
481
482
483int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
484{
485 unsigned long offset;
486 struct pci_controller *hose = pci_bus_to_host(bus);
487 struct resource *rp = &hose->io_resource;
488 void __iomem *addr;
489
490
491
492
493
494
495 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
496 offset += port;
497
498 if (!(rp->flags & IORESOURCE_IO))
499 return -ENXIO;
500 if (offset < rp->start || (offset + size) > rp->end)
501 return -ENXIO;
502 addr = hose->io_base_virt + port;
503
504 switch(size) {
505 case 1:
506 *((u8 *)val) = in_8(addr);
507 return 1;
508 case 2:
509 if (port & 1)
510 return -EINVAL;
511 *((u16 *)val) = in_le16(addr);
512 return 2;
513 case 4:
514 if (port & 3)
515 return -EINVAL;
516 *((u32 *)val) = in_le32(addr);
517 return 4;
518 }
519 return -EINVAL;
520}
521
522
523int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
524{
525 unsigned long offset;
526 struct pci_controller *hose = pci_bus_to_host(bus);
527 struct resource *rp = &hose->io_resource;
528 void __iomem *addr;
529
530
531
532
533
534
535 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
536 offset += port;
537
538 if (!(rp->flags & IORESOURCE_IO))
539 return -ENXIO;
540 if (offset < rp->start || (offset + size) > rp->end)
541 return -ENXIO;
542 addr = hose->io_base_virt + port;
543
544
545
546
547
548
549 switch(size) {
550 case 1:
551 out_8(addr, val >> 24);
552 return 1;
553 case 2:
554 if (port & 1)
555 return -EINVAL;
556 out_le16(addr, val >> 16);
557 return 2;
558 case 4:
559 if (port & 3)
560 return -EINVAL;
561 out_le32(addr, val);
562 return 4;
563 }
564 return -EINVAL;
565}
566
567
568int pci_mmap_legacy_page_range(struct pci_bus *bus,
569 struct vm_area_struct *vma,
570 enum pci_mmap_state mmap_state)
571{
572 struct pci_controller *hose = pci_bus_to_host(bus);
573 resource_size_t offset =
574 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
575 resource_size_t size = vma->vm_end - vma->vm_start;
576 struct resource *rp;
577
578 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
579 pci_domain_nr(bus), bus->number,
580 mmap_state == pci_mmap_mem ? "MEM" : "IO",
581 (unsigned long long)offset,
582 (unsigned long long)(offset + size - 1));
583
584 if (mmap_state == pci_mmap_mem) {
585
586
587
588
589
590
591
592 if ((offset + size) > hose->isa_mem_size) {
593 printk(KERN_DEBUG
594 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
595 current->comm, current->pid, pci_domain_nr(bus), bus->number);
596 if (vma->vm_flags & VM_SHARED)
597 return shmem_zero_setup(vma);
598 return 0;
599 }
600 offset += hose->isa_mem_phys;
601 } else {
602 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
603 unsigned long roffset = offset + io_offset;
604 rp = &hose->io_resource;
605 if (!(rp->flags & IORESOURCE_IO))
606 return -ENXIO;
607 if (roffset < rp->start || (roffset + size) > rp->end)
608 return -ENXIO;
609 offset += hose->io_base_phys;
610 }
611 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
612
613 vma->vm_pgoff = offset >> PAGE_SHIFT;
614 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
615 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
616 vma->vm_end - vma->vm_start,
617 vma->vm_page_prot);
618}
619
620void pci_resource_to_user(const struct pci_dev *dev, int bar,
621 const struct resource *rsrc,
622 resource_size_t *start, resource_size_t *end)
623{
624 struct pci_controller *hose = pci_bus_to_host(dev->bus);
625 resource_size_t offset = 0;
626
627 if (hose == NULL)
628 return;
629
630 if (rsrc->flags & IORESOURCE_IO)
631 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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649
650#if 0
651 else if (rsrc->flags & IORESOURCE_MEM)
652 offset = hose->pci_mem_offset;
653#endif
654
655 *start = rsrc->start - offset;
656 *end = rsrc->end - offset;
657}
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692void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
693 struct device_node *dev,
694 int primary)
695{
696 const u32 *ranges;
697 int rlen;
698 int pna = of_n_addr_cells(dev);
699 int np = pna + 5;
700 int memno = 0, isa_hole = -1;
701 u32 pci_space;
702 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
703 unsigned long long isa_mb = 0;
704 struct resource *res;
705
706 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
707 dev->full_name, primary ? "(primary)" : "");
708
709
710 ranges = of_get_property(dev, "ranges", &rlen);
711 if (ranges == NULL)
712 return;
713
714
715 while ((rlen -= np * 4) >= 0) {
716
717 pci_space = ranges[0];
718 pci_addr = of_read_number(ranges + 1, 2);
719 cpu_addr = of_translate_address(dev, ranges + 3);
720 size = of_read_number(ranges + pna + 3, 2);
721 ranges += np;
722
723
724
725
726
727
728 if (cpu_addr == OF_BAD_ADDR || size == 0)
729 continue;
730
731
732 for (; rlen >= np * sizeof(u32);
733 ranges += np, rlen -= np * 4) {
734 if (ranges[0] != pci_space)
735 break;
736 pci_next = of_read_number(ranges + 1, 2);
737 cpu_next = of_translate_address(dev, ranges + 3);
738 if (pci_next != pci_addr + size ||
739 cpu_next != cpu_addr + size)
740 break;
741 size += of_read_number(ranges + pna + 3, 2);
742 }
743
744
745 res = NULL;
746 switch ((pci_space >> 24) & 0x3) {
747 case 1:
748 printk(KERN_INFO
749 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
750 cpu_addr, cpu_addr + size - 1, pci_addr);
751
752
753 if (hose->pci_io_size) {
754 printk(KERN_INFO
755 " \\--> Skipped (too many) !\n");
756 continue;
757 }
758#ifdef CONFIG_PPC32
759
760 if (size > 0x01000000)
761 size = 0x01000000;
762
763
764 hose->io_base_virt = ioremap(cpu_addr, size);
765
766
767 if (primary)
768 isa_io_base =
769 (unsigned long)hose->io_base_virt;
770#endif
771
772
773
774 hose->pci_io_size = pci_addr + size;
775 hose->io_base_phys = cpu_addr - pci_addr;
776
777
778 res = &hose->io_resource;
779 res->flags = IORESOURCE_IO;
780 res->start = pci_addr;
781 break;
782 case 2:
783 case 3:
784 printk(KERN_INFO
785 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
786 cpu_addr, cpu_addr + size - 1, pci_addr,
787 (pci_space & 0x40000000) ? "Prefetch" : "");
788
789
790 if (memno >= 3) {
791 printk(KERN_INFO
792 " \\--> Skipped (too many) !\n");
793 continue;
794 }
795
796 if (pci_addr == 0) {
797 isa_mb = cpu_addr;
798 isa_hole = memno;
799 if (primary || isa_mem_base == 0)
800 isa_mem_base = cpu_addr;
801 hose->isa_mem_phys = cpu_addr;
802 hose->isa_mem_size = size;
803 }
804
805
806
807
808
809 if (memno == 0 ||
810 (isa_hole >= 0 && pci_addr != 0 &&
811 hose->pci_mem_offset == isa_mb))
812 hose->pci_mem_offset = cpu_addr - pci_addr;
813 else if (pci_addr != 0 &&
814 hose->pci_mem_offset != cpu_addr - pci_addr) {
815 printk(KERN_INFO
816 " \\--> Skipped (offset mismatch) !\n");
817 continue;
818 }
819
820
821 res = &hose->mem_resources[memno++];
822 res->flags = IORESOURCE_MEM;
823 if (pci_space & 0x40000000)
824 res->flags |= IORESOURCE_PREFETCH;
825 res->start = cpu_addr;
826 break;
827 }
828 if (res != NULL) {
829 res->name = dev->full_name;
830 res->end = res->start + size - 1;
831 res->parent = NULL;
832 res->sibling = NULL;
833 res->child = NULL;
834 }
835 }
836
837
838
839
840
841 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
842 unsigned int next = isa_hole + 1;
843 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
844 if (next < memno)
845 memmove(&hose->mem_resources[isa_hole],
846 &hose->mem_resources[next],
847 sizeof(struct resource) * (memno - next));
848 hose->mem_resources[--memno].flags = 0;
849 }
850}
851
852
853int pci_proc_domain(struct pci_bus *bus)
854{
855 struct pci_controller *hose = pci_bus_to_host(bus);
856
857 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
858 return 0;
859 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
860 return hose->global_number != 0;
861 return 1;
862}
863
864void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
865 struct resource *res)
866{
867 resource_size_t offset = 0, mask = (resource_size_t)-1;
868 struct pci_controller *hose = pci_bus_to_host(dev->bus);
869
870 if (!hose)
871 return;
872 if (res->flags & IORESOURCE_IO) {
873 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
874 mask = 0xffffffffu;
875 } else if (res->flags & IORESOURCE_MEM)
876 offset = hose->pci_mem_offset;
877
878 region->start = (res->start - offset) & mask;
879 region->end = (res->end - offset) & mask;
880}
881EXPORT_SYMBOL(pcibios_resource_to_bus);
882
883void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
884 struct pci_bus_region *region)
885{
886 resource_size_t offset = 0, mask = (resource_size_t)-1;
887 struct pci_controller *hose = pci_bus_to_host(dev->bus);
888
889 if (!hose)
890 return;
891 if (res->flags & IORESOURCE_IO) {
892 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
893 mask = 0xffffffffu;
894 } else if (res->flags & IORESOURCE_MEM)
895 offset = hose->pci_mem_offset;
896 res->start = (region->start + offset) & mask;
897 res->end = (region->end + offset) & mask;
898}
899EXPORT_SYMBOL(pcibios_bus_to_resource);
900
901
902static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
903{
904 struct pci_controller *hose = pci_bus_to_host(dev->bus);
905 resource_size_t offset = 0, mask = (resource_size_t)-1;
906
907 if (res->flags & IORESOURCE_IO) {
908 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
909 mask = 0xffffffffu;
910 } else if (res->flags & IORESOURCE_MEM)
911 offset = hose->pci_mem_offset;
912
913 res->start = (res->start + offset) & mask;
914 res->end = (res->end + offset) & mask;
915}
916
917
918
919
920
921static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
922{
923 struct pci_controller *hose = pci_bus_to_host(dev->bus);
924 int i;
925
926 if (!hose) {
927 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
928 pci_name(dev));
929 return;
930 }
931 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
932 struct resource *res = dev->resource + i;
933 if (!res->flags)
934 continue;
935
936
937
938
939
940
941 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
942 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
943 pci_name(dev), i,
944 (unsigned long long)res->start,
945 (unsigned long long)res->end,
946 (unsigned int)res->flags);
947 res->end -= res->start;
948 res->start = 0;
949 res->flags |= IORESOURCE_UNSET;
950 continue;
951 }
952
953 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
954 pci_name(dev), i,
955 (unsigned long long)res->start,\
956 (unsigned long long)res->end,
957 (unsigned int)res->flags);
958
959 fixup_resource(res, dev);
960
961 pr_debug("PCI:%s %016llx-%016llx\n",
962 pci_name(dev),
963 (unsigned long long)res->start,
964 (unsigned long long)res->end);
965 }
966
967
968 if (ppc_md.pcibios_fixup_resources)
969 ppc_md.pcibios_fixup_resources(dev);
970}
971DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
972
973
974
975
976
977
978static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
979 struct resource *res)
980{
981 struct pci_controller *hose = pci_bus_to_host(bus);
982 struct pci_dev *dev = bus->self;
983 resource_size_t offset;
984 u16 command;
985 int i;
986
987
988 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY)
989 return 0;
990
991
992 if (res->flags & IORESOURCE_MEM) {
993
994
995
996 if (res->start != hose->pci_mem_offset)
997 return 0;
998
999
1000
1001
1002 pci_read_config_word(dev, PCI_COMMAND, &command);
1003 if ((command & PCI_COMMAND_MEMORY) == 0)
1004 return 1;
1005
1006
1007
1008
1009
1010 for (i = 0; i < 3; i++) {
1011 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
1012 hose->mem_resources[i].start == hose->pci_mem_offset)
1013 return 0;
1014 }
1015
1016
1017
1018
1019 return 1;
1020 } else {
1021
1022 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1023 if (((res->start - offset) & 0xfffffffful) != 0)
1024 return 0;
1025
1026
1027
1028
1029
1030
1031 pci_read_config_word(dev, PCI_COMMAND, &command);
1032 if (command & PCI_COMMAND_IO)
1033 return 0;
1034
1035
1036
1037
1038 return 1;
1039 }
1040}
1041
1042
1043static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1044{
1045 struct resource *res;
1046 int i;
1047
1048 struct pci_dev *dev = bus->self;
1049
1050 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1051 if ((res = bus->resource[i]) == NULL)
1052 continue;
1053 if (!res->flags)
1054 continue;
1055 if (i >= 3 && bus->self->transparent)
1056 continue;
1057
1058 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1059 pci_name(dev), i,
1060 (unsigned long long)res->start,\
1061 (unsigned long long)res->end,
1062 (unsigned int)res->flags);
1063
1064
1065 fixup_resource(res, dev);
1066
1067
1068
1069
1070 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1071 res->flags = 0;
1072 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1073 } else {
1074
1075 pr_debug("PCI:%s %016llx-%016llx\n",
1076 pci_name(dev),
1077 (unsigned long long)res->start,
1078 (unsigned long long)res->end);
1079 }
1080 }
1081}
1082
1083void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1084{
1085
1086 if (bus->self != NULL)
1087 pcibios_fixup_bridge(bus);
1088
1089
1090
1091
1092 if (ppc_md.pcibios_fixup_bus)
1093 ppc_md.pcibios_fixup_bus(bus);
1094
1095
1096 if (ppc_md.pci_dma_bus_setup)
1097 ppc_md.pci_dma_bus_setup(bus);
1098}
1099
1100void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1101{
1102 struct pci_dev *dev;
1103
1104 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1105 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1106
1107 list_for_each_entry(dev, &bus->devices, bus_list) {
1108 struct dev_archdata *sd = &dev->dev.archdata;
1109
1110
1111 sd->of_node = pci_device_to_OF_node(dev);
1112
1113
1114
1115
1116 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1117
1118
1119 sd->dma_ops = pci_dma_ops;
1120 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1121
1122
1123 if (ppc_md.pci_dma_dev_setup)
1124 ppc_md.pci_dma_dev_setup(dev);
1125
1126
1127 pci_read_irq_line(dev);
1128 if (ppc_md.pci_irq_fixup)
1129 ppc_md.pci_irq_fixup(dev);
1130 }
1131}
1132
1133void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1134{
1135
1136
1137
1138
1139 if (bus->self != NULL)
1140 pci_read_bridge_bases(bus);
1141
1142
1143 pcibios_setup_bus_self(bus);
1144
1145
1146 pcibios_setup_bus_devices(bus);
1147}
1148EXPORT_SYMBOL(pcibios_fixup_bus);
1149
1150static int skip_isa_ioresource_align(struct pci_dev *dev)
1151{
1152 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
1153 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1154 return 1;
1155 return 0;
1156}
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171void pcibios_align_resource(void *data, struct resource *res,
1172 resource_size_t size, resource_size_t align)
1173{
1174 struct pci_dev *dev = data;
1175
1176 if (res->flags & IORESOURCE_IO) {
1177 resource_size_t start = res->start;
1178
1179 if (skip_isa_ioresource_align(dev))
1180 return;
1181 if (start & 0x300) {
1182 start = (start + 0x3ff) & ~0x3ff;
1183 res->start = start;
1184 }
1185 }
1186}
1187EXPORT_SYMBOL(pcibios_align_resource);
1188
1189
1190
1191
1192
1193static int reparent_resources(struct resource *parent,
1194 struct resource *res)
1195{
1196 struct resource *p, **pp;
1197 struct resource **firstpp = NULL;
1198
1199 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1200 if (p->end < res->start)
1201 continue;
1202 if (res->end < p->start)
1203 break;
1204 if (p->start < res->start || p->end > res->end)
1205 return -1;
1206 if (firstpp == NULL)
1207 firstpp = pp;
1208 }
1209 if (firstpp == NULL)
1210 return -1;
1211 res->parent = parent;
1212 res->child = *firstpp;
1213 res->sibling = *pp;
1214 *firstpp = res;
1215 *pp = NULL;
1216 for (p = res->child; p != NULL; p = p->sibling) {
1217 p->parent = res;
1218 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1219 p->name,
1220 (unsigned long long)p->start,
1221 (unsigned long long)p->end, res->name);
1222 }
1223 return 0;
1224}
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259void pcibios_allocate_bus_resources(struct pci_bus *bus)
1260{
1261 struct pci_bus *b;
1262 int i;
1263 struct resource *res, *pr;
1264
1265 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1266 pci_domain_nr(bus), bus->number);
1267
1268 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1269 if ((res = bus->resource[i]) == NULL || !res->flags
1270 || res->start > res->end || res->parent)
1271 continue;
1272 if (bus->parent == NULL)
1273 pr = (res->flags & IORESOURCE_IO) ?
1274 &ioport_resource : &iomem_resource;
1275 else {
1276
1277
1278
1279
1280
1281
1282 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
1283 goto clear_resource;
1284 pr = pci_find_parent_resource(bus->self, res);
1285 if (pr == res) {
1286
1287
1288
1289
1290 continue;
1291 }
1292 }
1293
1294 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1295 "[0x%x], parent %p (%s)\n",
1296 bus->self ? pci_name(bus->self) : "PHB",
1297 bus->number, i,
1298 (unsigned long long)res->start,
1299 (unsigned long long)res->end,
1300 (unsigned int)res->flags,
1301 pr, (pr && pr->name) ? pr->name : "nil");
1302
1303 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1304 if (request_resource(pr, res) == 0)
1305 continue;
1306
1307
1308
1309
1310
1311 if (reparent_resources(pr, res) == 0)
1312 continue;
1313 }
1314 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1315 "%d of PCI bridge %d, will remap\n", i, bus->number);
1316clear_resource:
1317 res->flags = 0;
1318 }
1319
1320 list_for_each_entry(b, &bus->children, node)
1321 pcibios_allocate_bus_resources(b);
1322}
1323
1324static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1325{
1326 struct resource *pr, *r = &dev->resource[idx];
1327
1328 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1329 pci_name(dev), idx,
1330 (unsigned long long)r->start,
1331 (unsigned long long)r->end,
1332 (unsigned int)r->flags);
1333
1334 pr = pci_find_parent_resource(dev, r);
1335 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1336 request_resource(pr, r) < 0) {
1337 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1338 " of device %s, will remap\n", idx, pci_name(dev));
1339 if (pr)
1340 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1341 pr,
1342 (unsigned long long)pr->start,
1343 (unsigned long long)pr->end,
1344 (unsigned int)pr->flags);
1345
1346 r->flags |= IORESOURCE_UNSET;
1347 r->end -= r->start;
1348 r->start = 0;
1349 }
1350}
1351
1352static void __init pcibios_allocate_resources(int pass)
1353{
1354 struct pci_dev *dev = NULL;
1355 int idx, disabled;
1356 u16 command;
1357 struct resource *r;
1358
1359 for_each_pci_dev(dev) {
1360 pci_read_config_word(dev, PCI_COMMAND, &command);
1361 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1362 r = &dev->resource[idx];
1363 if (r->parent)
1364 continue;
1365 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1366 continue;
1367
1368
1369
1370 if (idx == PCI_ROM_RESOURCE )
1371 disabled = 1;
1372 if (r->flags & IORESOURCE_IO)
1373 disabled = !(command & PCI_COMMAND_IO);
1374 else
1375 disabled = !(command & PCI_COMMAND_MEMORY);
1376 if (pass == disabled)
1377 alloc_resource(dev, idx);
1378 }
1379 if (pass)
1380 continue;
1381 r = &dev->resource[PCI_ROM_RESOURCE];
1382 if (r->flags) {
1383
1384
1385
1386 u32 reg;
1387 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1388 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1389 pr_debug("PCI: Switching off ROM of %s\n",
1390 pci_name(dev));
1391 r->flags &= ~IORESOURCE_ROM_ENABLE;
1392 pci_write_config_dword(dev, dev->rom_base_reg,
1393 reg & ~PCI_ROM_ADDRESS_ENABLE);
1394 }
1395 }
1396 }
1397}
1398
1399static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1400{
1401 struct pci_controller *hose = pci_bus_to_host(bus);
1402 resource_size_t offset;
1403 struct resource *res, *pres;
1404 int i;
1405
1406 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1407
1408
1409 if (!(hose->io_resource.flags & IORESOURCE_IO))
1410 goto no_io;
1411 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1412 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1413 BUG_ON(res == NULL);
1414 res->name = "Legacy IO";
1415 res->flags = IORESOURCE_IO;
1416 res->start = offset;
1417 res->end = (offset + 0xfff) & 0xfffffffful;
1418 pr_debug("Candidate legacy IO: %pR\n", res);
1419 if (request_resource(&hose->io_resource, res)) {
1420 printk(KERN_DEBUG
1421 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1422 pci_domain_nr(bus), bus->number, res);
1423 kfree(res);
1424 }
1425
1426 no_io:
1427
1428 offset = hose->pci_mem_offset;
1429 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1430 for (i = 0; i < 3; i++) {
1431 pres = &hose->mem_resources[i];
1432 if (!(pres->flags & IORESOURCE_MEM))
1433 continue;
1434 pr_debug("hose mem res: %pR\n", pres);
1435 if ((pres->start - offset) <= 0xa0000 &&
1436 (pres->end - offset) >= 0xbffff)
1437 break;
1438 }
1439 if (i >= 3)
1440 return;
1441 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1442 BUG_ON(res == NULL);
1443 res->name = "Legacy VGA memory";
1444 res->flags = IORESOURCE_MEM;
1445 res->start = 0xa0000 + offset;
1446 res->end = 0xbffff + offset;
1447 pr_debug("Candidate VGA memory: %pR\n", res);
1448 if (request_resource(pres, res)) {
1449 printk(KERN_DEBUG
1450 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1451 pci_domain_nr(bus), bus->number, res);
1452 kfree(res);
1453 }
1454}
1455
1456void __init pcibios_resource_survey(void)
1457{
1458 struct pci_bus *b;
1459
1460
1461
1462
1463 list_for_each_entry(b, &pci_root_buses, node)
1464 pcibios_allocate_bus_resources(b);
1465
1466 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
1467 pcibios_allocate_resources(0);
1468 pcibios_allocate_resources(1);
1469 }
1470
1471
1472
1473
1474
1475 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1476 list_for_each_entry(b, &pci_root_buses, node)
1477 pcibios_reserve_legacy_regions(b);
1478 }
1479
1480
1481
1482
1483 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1484 pr_debug("PCI: Assigning unassigned resources...\n");
1485 pci_assign_unassigned_resources();
1486 }
1487
1488
1489 if (ppc_md.pcibios_fixup)
1490 ppc_md.pcibios_fixup();
1491}
1492
1493#ifdef CONFIG_HOTPLUG
1494
1495
1496
1497
1498
1499
1500void pcibios_claim_one_bus(struct pci_bus *bus)
1501{
1502 struct pci_dev *dev;
1503 struct pci_bus *child_bus;
1504
1505 list_for_each_entry(dev, &bus->devices, bus_list) {
1506 int i;
1507
1508 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1509 struct resource *r = &dev->resource[i];
1510
1511 if (r->parent || !r->start || !r->flags)
1512 continue;
1513
1514 pr_debug("PCI: Claiming %s: "
1515 "Resource %d: %016llx..%016llx [%x]\n",
1516 pci_name(dev), i,
1517 (unsigned long long)r->start,
1518 (unsigned long long)r->end,
1519 (unsigned int)r->flags);
1520
1521 pci_claim_resource(dev, i);
1522 }
1523 }
1524
1525 list_for_each_entry(child_bus, &bus->children, node)
1526 pcibios_claim_one_bus(child_bus);
1527}
1528
1529
1530
1531
1532
1533
1534
1535
1536void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1537{
1538 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1539 pci_domain_nr(bus), bus->number);
1540
1541
1542 pcibios_allocate_bus_resources(bus);
1543 pcibios_claim_one_bus(bus);
1544
1545
1546 pci_bus_add_devices(bus);
1547
1548
1549 eeh_add_device_tree_late(bus);
1550}
1551EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1552
1553#endif
1554
1555int pcibios_enable_device(struct pci_dev *dev, int mask)
1556{
1557 if (ppc_md.pcibios_enable_device_hook)
1558 if (ppc_md.pcibios_enable_device_hook(dev))
1559 return -EINVAL;
1560
1561 return pci_enable_resources(dev, mask);
1562}
1563
1564void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1565{
1566 struct pci_bus *bus = hose->bus;
1567 struct resource *res;
1568 int i;
1569
1570
1571 bus->resource[0] = res = &hose->io_resource;
1572
1573 if (!res->flags) {
1574 printk(KERN_WARNING "PCI: I/O resource not set for host"
1575 " bridge %s (domain %d)\n",
1576 hose->dn->full_name, hose->global_number);
1577#ifdef CONFIG_PPC32
1578
1579 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1580 res->end = res->start + IO_SPACE_LIMIT;
1581 res->flags = IORESOURCE_IO;
1582#endif
1583 }
1584
1585 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1586 (unsigned long long)res->start,
1587 (unsigned long long)res->end,
1588 (unsigned long)res->flags);
1589
1590
1591 for (i = 0; i < 3; ++i) {
1592 res = &hose->mem_resources[i];
1593 if (!res->flags) {
1594 if (i > 0)
1595 continue;
1596 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1597 "host bridge %s (domain %d)\n",
1598 hose->dn->full_name, hose->global_number);
1599#ifdef CONFIG_PPC32
1600
1601 res->start = hose->pci_mem_offset;
1602 res->end = (resource_size_t)-1LL;
1603 res->flags = IORESOURCE_MEM;
1604#endif
1605 }
1606 bus->resource[i+1] = res;
1607
1608 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1609 (unsigned long long)res->start,
1610 (unsigned long long)res->end,
1611 (unsigned long)res->flags);
1612 }
1613
1614 pr_debug("PCI: PHB MEM offset = %016llx\n",
1615 (unsigned long long)hose->pci_mem_offset);
1616 pr_debug("PCI: PHB IO offset = %08lx\n",
1617 (unsigned long)hose->io_base_virt - _IO_BASE);
1618
1619}
1620
1621
1622
1623
1624
1625#define NULL_PCI_OP(rw, size, type) \
1626static int \
1627null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1628{ \
1629 return PCIBIOS_DEVICE_NOT_FOUND; \
1630}
1631
1632static int
1633null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1634 int len, u32 *val)
1635{
1636 return PCIBIOS_DEVICE_NOT_FOUND;
1637}
1638
1639static int
1640null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1641 int len, u32 val)
1642{
1643 return PCIBIOS_DEVICE_NOT_FOUND;
1644}
1645
1646static struct pci_ops null_pci_ops =
1647{
1648 .read = null_read_config,
1649 .write = null_write_config,
1650};
1651
1652
1653
1654
1655
1656static struct pci_bus *
1657fake_pci_bus(struct pci_controller *hose, int busnr)
1658{
1659 static struct pci_bus bus;
1660
1661 if (hose == 0) {
1662 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1663 }
1664 bus.number = busnr;
1665 bus.sysdata = hose;
1666 bus.ops = hose? hose->ops: &null_pci_ops;
1667 return &bus;
1668}
1669
1670#define EARLY_PCI_OP(rw, size, type) \
1671int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1672 int devfn, int offset, type value) \
1673{ \
1674 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1675 devfn, offset, value); \
1676}
1677
1678EARLY_PCI_OP(read, byte, u8 *)
1679EARLY_PCI_OP(read, word, u16 *)
1680EARLY_PCI_OP(read, dword, u32 *)
1681EARLY_PCI_OP(write, byte, u8)
1682EARLY_PCI_OP(write, word, u16)
1683EARLY_PCI_OP(write, dword, u32)
1684
1685extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1686int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1687 int cap)
1688{
1689 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1690}
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701void __devinit pcibios_scan_phb(struct pci_controller *hose, void *sysdata)
1702{
1703 struct pci_bus *bus;
1704 struct device_node *node = hose->dn;
1705 int mode;
1706
1707 pr_debug("PCI: Scanning PHB %s\n",
1708 node ? node->full_name : "<NO NAME>");
1709
1710
1711 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops,
1712 sysdata);
1713 if (bus == NULL) {
1714 pr_err("Failed to create bus for PCI domain %04x\n",
1715 hose->global_number);
1716 return;
1717 }
1718 bus->secondary = hose->first_busno;
1719 hose->bus = bus;
1720
1721
1722 pcibios_setup_phb_io_space(hose);
1723
1724
1725 pcibios_setup_phb_resources(hose);
1726
1727
1728 mode = PCI_PROBE_NORMAL;
1729 if (node && ppc_md.pci_probe_mode)
1730 mode = ppc_md.pci_probe_mode(bus);
1731 pr_debug(" probe mode: %d\n", mode);
1732 if (mode == PCI_PROBE_DEVTREE) {
1733 bus->subordinate = hose->last_busno;
1734 of_scan_bus(node, bus);
1735 }
1736
1737 if (mode == PCI_PROBE_NORMAL)
1738 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1739}
1740