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25#include <linux/errno.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/console.h>
29#include <linux/pci.h>
30#include <linux/of_platform.h>
31
32#include <asm/prom.h>
33#include <asm/system.h>
34#include <asm/iommu.h>
35#include <asm/machdep.h>
36#include <asm/mpic.h>
37#include <asm/smp.h>
38#include <asm/time.h>
39#include <asm/mmu.h>
40
41#include <pcmcia/ss.h>
42#include <pcmcia/cistpl.h>
43#include <pcmcia/ds.h>
44
45#include "pasemi.h"
46
47
48static void __iomem *reset_reg;
49
50
51
52#define MAX_MCE_REGS 32
53struct mce_regs {
54 char *name;
55 void __iomem *addr;
56};
57
58static struct mce_regs mce_regs[MAX_MCE_REGS];
59static int num_mce_regs;
60static int nmi_virq = NO_IRQ;
61
62
63static void pas_restart(char *cmd)
64{
65
66 smp_send_stop();
67 udelay(10000);
68 printk("Restarting...\n");
69 while (1)
70 out_le32(reset_reg, 0x6000000);
71}
72
73#ifdef CONFIG_SMP
74static raw_spinlock_t timebase_lock;
75static unsigned long timebase;
76
77static void __devinit pas_give_timebase(void)
78{
79 unsigned long flags;
80
81 local_irq_save(flags);
82 hard_irq_disable();
83 __raw_spin_lock(&timebase_lock);
84 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
85 isync();
86 timebase = get_tb();
87 __raw_spin_unlock(&timebase_lock);
88
89 while (timebase)
90 barrier();
91 mtspr(SPRN_TBCTL, TBCTL_RESTART);
92 local_irq_restore(flags);
93}
94
95static void __devinit pas_take_timebase(void)
96{
97 while (!timebase)
98 smp_rmb();
99
100 __raw_spin_lock(&timebase_lock);
101 set_tb(timebase >> 32, timebase & 0xffffffff);
102 timebase = 0;
103 __raw_spin_unlock(&timebase_lock);
104}
105
106struct smp_ops_t pas_smp_ops = {
107 .probe = smp_mpic_probe,
108 .message_pass = smp_mpic_message_pass,
109 .kick_cpu = smp_generic_kick_cpu,
110 .setup_cpu = smp_mpic_setup_cpu,
111 .give_timebase = pas_give_timebase,
112 .take_timebase = pas_take_timebase,
113};
114#endif
115
116void __init pas_setup_arch(void)
117{
118#ifdef CONFIG_SMP
119
120 smp_ops = &pas_smp_ops;
121#endif
122
123 pas_pci_init();
124
125#ifdef CONFIG_DUMMY_CONSOLE
126 conswitchp = &dummy_con;
127#endif
128
129
130
131 reset_reg = ioremap(0xfc101100, 4);
132}
133
134static int __init pas_setup_mce_regs(void)
135{
136 struct pci_dev *dev;
137 int reg;
138
139
140
141 reg = 0;
142
143 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
144 while (dev && reg < MAX_MCE_REGS) {
145 mce_regs[reg].name = kasprintf(GFP_KERNEL,
146 "mc%d_mcdebug_errsta", reg);
147 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
148 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
149 reg++;
150 }
151
152 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
153 if (dev && reg+4 < MAX_MCE_REGS) {
154 mce_regs[reg].name = "iobdbg_IntStatus1";
155 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
156 reg++;
157 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
158 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
159 reg++;
160 mce_regs[reg].name = "iobiom_IntStatus";
161 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
162 reg++;
163 mce_regs[reg].name = "iobiom_IntDbgReg";
164 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
165 reg++;
166 }
167
168 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
169 if (dev && reg+2 < MAX_MCE_REGS) {
170 mce_regs[reg].name = "l2csts_IntStatus";
171 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
172 reg++;
173 mce_regs[reg].name = "l2csts_Cnt";
174 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
175 reg++;
176 }
177
178 num_mce_regs = reg;
179
180 return 0;
181}
182machine_device_initcall(pasemi, pas_setup_mce_regs);
183
184static __init void pas_init_IRQ(void)
185{
186 struct device_node *np;
187 struct device_node *root, *mpic_node;
188 unsigned long openpic_addr;
189 const unsigned int *opprop;
190 int naddr, opplen;
191 int mpic_flags;
192 const unsigned int *nmiprop;
193 struct mpic *mpic;
194
195 mpic_node = NULL;
196
197 for_each_node_by_type(np, "interrupt-controller")
198 if (of_device_is_compatible(np, "open-pic")) {
199 mpic_node = np;
200 break;
201 }
202 if (!mpic_node)
203 for_each_node_by_type(np, "open-pic") {
204 mpic_node = np;
205 break;
206 }
207 if (!mpic_node) {
208 printk(KERN_ERR
209 "Failed to locate the MPIC interrupt controller\n");
210 return;
211 }
212
213
214 root = of_find_node_by_path("/");
215 naddr = of_n_addr_cells(root);
216 opprop = of_get_property(root, "platform-open-pic", &opplen);
217 if (!opprop) {
218 printk(KERN_ERR "No platform-open-pic property.\n");
219 of_node_put(root);
220 return;
221 }
222 openpic_addr = of_read_number(opprop, naddr);
223 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
224
225 mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
226
227 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
228 if (nmiprop)
229 mpic_flags |= MPIC_ENABLE_MCK;
230
231 mpic = mpic_alloc(mpic_node, openpic_addr,
232 mpic_flags, 0, 0, "PASEMI-OPIC");
233 BUG_ON(!mpic);
234
235 mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
236 mpic_init(mpic);
237
238 if (nmiprop) {
239 nmi_virq = irq_create_mapping(NULL, *nmiprop);
240 mpic_irq_set_priority(nmi_virq, 15);
241 set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
242 mpic_unmask_irq(nmi_virq);
243 }
244
245 of_node_put(mpic_node);
246 of_node_put(root);
247}
248
249static void __init pas_progress(char *s, unsigned short hex)
250{
251 printk("[%04x] : %s\n", hex, s ? s : "");
252}
253
254
255static int pas_machine_check_handler(struct pt_regs *regs)
256{
257 int cpu = smp_processor_id();
258 unsigned long srr0, srr1, dsisr;
259 int dump_slb = 0;
260 int i;
261
262 srr0 = regs->nip;
263 srr1 = regs->msr;
264
265 if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
266 printk(KERN_ERR "NMI delivered\n");
267 debugger(regs);
268 mpic_end_irq(nmi_virq);
269 goto out;
270 }
271
272 dsisr = mfspr(SPRN_DSISR);
273 printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
274 printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
275 printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
276 printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
277 mfspr(SPRN_PA6T_MER));
278 printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
279 mfspr(SPRN_PA6T_DER));
280 printk(KERN_ERR "Cause:\n");
281
282 if (srr1 & 0x200000)
283 printk(KERN_ERR "Signalled by SDC\n");
284
285 if (srr1 & 0x100000) {
286 printk(KERN_ERR "Load/Store detected error:\n");
287 if (dsisr & 0x8000)
288 printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
289 if (dsisr & 0x4000)
290 printk(KERN_ERR "LSU snoop response error\n");
291 if (dsisr & 0x2000) {
292 printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
293 dump_slb = 1;
294 }
295 if (dsisr & 0x1000)
296 printk(KERN_ERR "Recoverable Duptags\n");
297 if (dsisr & 0x800)
298 printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
299 if (dsisr & 0x400)
300 printk(KERN_ERR "TLB parity error count overflow\n");
301 }
302
303 if (srr1 & 0x80000)
304 printk(KERN_ERR "Bus Error\n");
305
306 if (srr1 & 0x40000) {
307 printk(KERN_ERR "I-side SLB multiple hit\n");
308 dump_slb = 1;
309 }
310
311 if (srr1 & 0x20000)
312 printk(KERN_ERR "I-cache parity error hit\n");
313
314 if (num_mce_regs == 0)
315 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
316 else
317 printk(KERN_ERR "SoC debug registers:\n");
318
319 for (i = 0; i < num_mce_regs; i++)
320 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
321 in_le32(mce_regs[i].addr));
322
323 if (dump_slb) {
324 unsigned long e, v;
325 int i;
326
327 printk(KERN_ERR "slb contents:\n");
328 for (i = 0; i < mmu_slb_size; i++) {
329 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
330 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
331 printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
332 }
333 }
334
335out:
336
337 return !!(srr1 & 0x2);
338}
339
340static void __init pas_init_early(void)
341{
342 iommu_init_early_pasemi();
343}
344
345#ifdef CONFIG_PCMCIA
346static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
347 void *data)
348{
349 struct device *dev = data;
350 struct device *parent;
351 struct pcmcia_device *pdev = to_pcmcia_dev(dev);
352
353
354 if (action != BUS_NOTIFY_ADD_DEVICE)
355 return 0;
356
357 parent = pdev->socket->dev.parent;
358
359
360
361
362 if (!parent->archdata.of_node)
363 return 0;
364
365 if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf"))
366 return 0;
367
368
369 dev->archdata.dma_ops = &dma_direct_ops;
370
371 return 0;
372}
373
374static struct notifier_block pcmcia_notifier = {
375 .notifier_call = pcmcia_notify,
376};
377
378static inline void pasemi_pcmcia_init(void)
379{
380 extern struct bus_type pcmcia_bus_type;
381
382 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
383}
384
385#else
386
387static inline void pasemi_pcmcia_init(void)
388{
389}
390
391#endif
392
393
394static struct of_device_id pasemi_bus_ids[] = {
395
396 { .type = "localbus", },
397 { .type = "sdc", },
398
399 { .compatible = "pasemi,localbus", },
400 { .compatible = "pasemi,sdc", },
401 {},
402};
403
404static int __init pasemi_publish_devices(void)
405{
406 pasemi_pcmcia_init();
407
408
409 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
410
411 return 0;
412}
413machine_device_initcall(pasemi, pasemi_publish_devices);
414
415
416
417
418
419static int __init pas_probe(void)
420{
421 unsigned long root = of_get_flat_dt_root();
422
423 if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
424 !of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
425 return 0;
426
427 hpte_init_native();
428
429 alloc_iobmap_l2();
430
431 return 1;
432}
433
434define_machine(pasemi) {
435 .name = "PA Semi PWRficient",
436 .probe = pas_probe,
437 .setup_arch = pas_setup_arch,
438 .init_early = pas_init_early,
439 .init_IRQ = pas_init_IRQ,
440 .get_irq = mpic_get_irq,
441 .restart = pas_restart,
442 .get_boot_time = pas_get_boot_time,
443 .calibrate_decr = generic_calibrate_decr,
444 .progress = pas_progress,
445 .machine_check_exception = pas_machine_check_handler,
446};
447
