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12
13#undef DEBUG
14
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22#include <linux/cpufreq.h>
23#include <linux/init.h>
24#include <linux/completion.h>
25#include <linux/mutex.h>
26#include <asm/prom.h>
27#include <asm/machdep.h>
28#include <asm/irq.h>
29#include <asm/sections.h>
30#include <asm/cputable.h>
31#include <asm/time.h>
32#include <asm/smu.h>
33#include <asm/pmac_pfunc.h>
34
35#define DBG(fmt...) pr_debug(fmt)
36
37
38
39#define SCOM_PCR 0x0aa001
40
41#define PCR_HILO_SELECT 0x80000000U
42#define PCR_SPEED_FULL 0x00000000U
43#define PCR_SPEED_HALF 0x00020000U
44#define PCR_SPEED_QUARTER 0x00040000U
45#define PCR_SPEED_MASK 0x000e0000U
46#define PCR_SPEED_SHIFT 17
47#define PCR_FREQ_REQ_VALID 0x00010000U
48#define PCR_VOLT_REQ_VALID 0x00008000U
49#define PCR_TARGET_TIME_MASK 0x00006000U
50#define PCR_STATLAT_MASK 0x00001f00U
51#define PCR_SNOOPLAT_MASK 0x000000f0U
52#define PCR_SNOOPACC_MASK 0x0000000fU
53
54#define SCOM_PSR 0x408001
55
56#define PSR_CMD_RECEIVED 0x2000000000000000U
57#define PSR_CMD_COMPLETED 0x1000000000000000U
58#define PSR_CUR_SPEED_MASK 0x0300000000000000U
59#define PSR_CUR_SPEED_SHIFT (56)
60
61
62
63
64#define CPUFREQ_HIGH 0
65#define CPUFREQ_LOW 1
66
67static struct cpufreq_frequency_table g5_cpu_freqs[] = {
68 {CPUFREQ_HIGH, 0},
69 {CPUFREQ_LOW, 0},
70 {0, CPUFREQ_TABLE_END},
71};
72
73static struct freq_attr* g5_cpu_freqs_attr[] = {
74 &cpufreq_freq_attr_scaling_available_freqs,
75 NULL,
76};
77
78
79
80
81static int g5_pmode_cur;
82
83static void (*g5_switch_volt)(int speed_mode);
84static int (*g5_switch_freq)(int speed_mode);
85static int (*g5_query_freq)(void);
86
87static DEFINE_MUTEX(g5_switch_mutex);
88
89static unsigned long transition_latency;
90
91#ifdef CONFIG_PMAC_SMU
92
93static const u32 *g5_pmode_data;
94static int g5_pmode_max;
95
96static struct smu_sdbp_fvt *g5_fvt_table;
97static int g5_fvt_count;
98static int g5_fvt_cur;
99
100
101
102
103
104static void g5_smu_switch_volt(int speed_mode)
105{
106 struct smu_simple_cmd cmd;
107
108 DECLARE_COMPLETION_ONSTACK(comp);
109 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
110 &comp, 'V', 'S', 'L', 'E', 'W',
111 0xff, g5_fvt_cur+1, speed_mode);
112 wait_for_completion(&comp);
113}
114
115
116
117
118
119static struct pmf_function *pfunc_set_vdnap0;
120static struct pmf_function *pfunc_vdnap0_complete;
121
122static void g5_vdnap_switch_volt(int speed_mode)
123{
124 struct pmf_args args;
125 u32 slew, done = 0;
126 unsigned long timeout;
127
128 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
129 args.count = 1;
130 args.u[0].p = &slew;
131
132 pmf_call_one(pfunc_set_vdnap0, &args);
133
134
135
136
137
138 timeout = jiffies + HZ/10;
139 while(!time_after(jiffies, timeout)) {
140 args.count = 1;
141 args.u[0].p = &done;
142 pmf_call_one(pfunc_vdnap0_complete, &args);
143 if (done)
144 break;
145 msleep(1);
146 }
147 if (done == 0)
148 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
149}
150
151
152
153
154
155static int g5_scom_switch_freq(int speed_mode)
156{
157 unsigned long flags;
158 int to;
159
160
161 if (speed_mode < g5_pmode_cur)
162 g5_switch_volt(speed_mode);
163
164 local_irq_save(flags);
165
166
167 scom970_write(SCOM_PCR, 0);
168
169 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
170
171 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
172 g5_pmode_data[speed_mode]);
173
174
175 for (to = 0; to < 10; to++) {
176 unsigned long psr = scom970_read(SCOM_PSR);
177
178 if ((psr & PSR_CMD_RECEIVED) == 0 &&
179 (((psr >> PSR_CUR_SPEED_SHIFT) ^
180 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
181 == 0)
182 break;
183 if (psr & PSR_CMD_COMPLETED)
184 break;
185 udelay(100);
186 }
187
188 local_irq_restore(flags);
189
190
191 if (speed_mode > g5_pmode_cur)
192 g5_switch_volt(speed_mode);
193
194 g5_pmode_cur = speed_mode;
195 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
196
197 return 0;
198}
199
200static int g5_scom_query_freq(void)
201{
202 unsigned long psr = scom970_read(SCOM_PSR);
203 int i;
204
205 for (i = 0; i <= g5_pmode_max; i++)
206 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
207 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
208 break;
209 return i;
210}
211
212
213
214
215
216static void g5_dummy_switch_volt(int speed_mode)
217{
218}
219
220#endif
221
222
223
224
225
226static struct pmf_function *pfunc_cpu0_volt_high;
227static struct pmf_function *pfunc_cpu0_volt_low;
228static struct pmf_function *pfunc_cpu1_volt_high;
229static struct pmf_function *pfunc_cpu1_volt_low;
230
231static void g5_pfunc_switch_volt(int speed_mode)
232{
233 if (speed_mode == CPUFREQ_HIGH) {
234 if (pfunc_cpu0_volt_high)
235 pmf_call_one(pfunc_cpu0_volt_high, NULL);
236 if (pfunc_cpu1_volt_high)
237 pmf_call_one(pfunc_cpu1_volt_high, NULL);
238 } else {
239 if (pfunc_cpu0_volt_low)
240 pmf_call_one(pfunc_cpu0_volt_low, NULL);
241 if (pfunc_cpu1_volt_low)
242 pmf_call_one(pfunc_cpu1_volt_low, NULL);
243 }
244 msleep(10);
245}
246
247
248
249
250
251static struct pmf_function *pfunc_cpu_setfreq_high;
252static struct pmf_function *pfunc_cpu_setfreq_low;
253static struct pmf_function *pfunc_cpu_getfreq;
254static struct pmf_function *pfunc_slewing_done;
255
256static int g5_pfunc_switch_freq(int speed_mode)
257{
258 struct pmf_args args;
259 u32 done = 0;
260 unsigned long timeout;
261 int rc;
262
263 DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
264
265
266 if (speed_mode < g5_pmode_cur)
267 g5_switch_volt(speed_mode);
268
269
270 if (speed_mode == CPUFREQ_HIGH)
271 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
272 else
273 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
274
275 if (rc)
276 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
277
278
279
280
281
282 timeout = jiffies + HZ/10;
283 while(!time_after(jiffies, timeout)) {
284 args.count = 1;
285 args.u[0].p = &done;
286 pmf_call_one(pfunc_slewing_done, &args);
287 if (done)
288 break;
289 msleep(1);
290 }
291 if (done == 0)
292 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
293
294
295 if (speed_mode > g5_pmode_cur)
296 g5_switch_volt(speed_mode);
297
298 g5_pmode_cur = speed_mode;
299 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
300
301 return 0;
302}
303
304static int g5_pfunc_query_freq(void)
305{
306 struct pmf_args args;
307 u32 val = 0;
308
309 args.count = 1;
310 args.u[0].p = &val;
311 pmf_call_one(pfunc_cpu_getfreq, &args);
312 return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
313}
314
315
316
317
318
319
320static int g5_cpufreq_verify(struct cpufreq_policy *policy)
321{
322 return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
323}
324
325static int g5_cpufreq_target(struct cpufreq_policy *policy,
326 unsigned int target_freq, unsigned int relation)
327{
328 unsigned int newstate = 0;
329 struct cpufreq_freqs freqs;
330 int rc;
331
332 if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
333 target_freq, relation, &newstate))
334 return -EINVAL;
335
336 if (g5_pmode_cur == newstate)
337 return 0;
338
339 mutex_lock(&g5_switch_mutex);
340
341 freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
342 freqs.new = g5_cpu_freqs[newstate].frequency;
343 freqs.cpu = 0;
344
345 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
346 rc = g5_switch_freq(newstate);
347 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
348
349 mutex_unlock(&g5_switch_mutex);
350
351 return rc;
352}
353
354static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
355{
356 return g5_cpu_freqs[g5_pmode_cur].frequency;
357}
358
359static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
360{
361 policy->cpuinfo.transition_latency = transition_latency;
362 policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
363
364
365
366 cpumask_copy(policy->cpus, &cpu_online_map);
367 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
368
369 return cpufreq_frequency_table_cpuinfo(policy,
370 g5_cpu_freqs);
371}
372
373
374static struct cpufreq_driver g5_cpufreq_driver = {
375 .name = "powermac",
376 .owner = THIS_MODULE,
377 .flags = CPUFREQ_CONST_LOOPS,
378 .init = g5_cpufreq_cpu_init,
379 .verify = g5_cpufreq_verify,
380 .target = g5_cpufreq_target,
381 .get = g5_cpufreq_get_speed,
382 .attr = g5_cpu_freqs_attr,
383};
384
385
386#ifdef CONFIG_PMAC_SMU
387
388static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
389{
390 struct device_node *cpunode;
391 unsigned int psize, ssize;
392 unsigned long max_freq;
393 char *freq_method, *volt_method;
394 const u32 *valp;
395 u32 pvr_hi;
396 int use_volts_vdnap = 0;
397 int use_volts_smu = 0;
398 int rc = -ENODEV;
399
400
401 if (machine_is_compatible("PowerMac8,1") ||
402 machine_is_compatible("PowerMac8,2") ||
403 machine_is_compatible("PowerMac9,1"))
404 use_volts_smu = 1;
405 else if (machine_is_compatible("PowerMac11,2"))
406 use_volts_vdnap = 1;
407 else
408 return -ENODEV;
409
410
411 for (cpunode = NULL;
412 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
413 const u32 *reg = of_get_property(cpunode, "reg", NULL);
414 if (reg == NULL || (*reg) != 0)
415 continue;
416 if (!strcmp(cpunode->type, "cpu"))
417 break;
418 }
419 if (cpunode == NULL) {
420 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
421 return -ENODEV;
422 }
423
424
425 valp = of_get_property(cpunode, "cpu-version", NULL);
426 if (!valp) {
427 DBG("No cpu-version property !\n");
428 goto bail_noprops;
429 }
430 pvr_hi = (*valp) >> 16;
431 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
432 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
433 goto bail_noprops;
434 }
435
436
437 g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
438 if (!g5_pmode_data) {
439 DBG("No power-mode-data !\n");
440 goto bail_noprops;
441 }
442 g5_pmode_max = psize / sizeof(u32) - 1;
443
444 if (use_volts_smu) {
445 const struct smu_sdbp_header *shdr;
446
447
448 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
449 if (!shdr)
450 goto bail_noprops;
451 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
452 ssize = (shdr->len * sizeof(u32)) -
453 sizeof(struct smu_sdbp_header);
454 g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
455 g5_fvt_cur = 0;
456
457
458 if (g5_fvt_count < 1 || g5_pmode_max < 1)
459 goto bail_noprops;
460
461 g5_switch_volt = g5_smu_switch_volt;
462 volt_method = "SMU";
463 } else if (use_volts_vdnap) {
464 struct device_node *root;
465
466 root = of_find_node_by_path("/");
467 if (root == NULL) {
468 printk(KERN_ERR "cpufreq: Can't find root of "
469 "device tree\n");
470 goto bail_noprops;
471 }
472 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
473 pfunc_vdnap0_complete =
474 pmf_find_function(root, "slewing-done");
475 if (pfunc_set_vdnap0 == NULL ||
476 pfunc_vdnap0_complete == NULL) {
477 printk(KERN_ERR "cpufreq: Can't find required "
478 "platform function\n");
479 goto bail_noprops;
480 }
481
482 g5_switch_volt = g5_vdnap_switch_volt;
483 volt_method = "GPIO";
484 } else {
485 g5_switch_volt = g5_dummy_switch_volt;
486 volt_method = "none";
487 }
488
489
490
491
492
493
494
495
496 valp = of_get_property(cpunode, "clock-frequency", NULL);
497 if (!valp)
498 return -ENODEV;
499 max_freq = (*valp)/1000;
500 g5_cpu_freqs[0].frequency = max_freq;
501 g5_cpu_freqs[1].frequency = max_freq/2;
502
503
504 transition_latency = 12000;
505 g5_switch_freq = g5_scom_switch_freq;
506 g5_query_freq = g5_scom_query_freq;
507 freq_method = "SCOM";
508
509
510
511
512
513 g5_switch_volt(CPUFREQ_HIGH);
514 msleep(10);
515 g5_pmode_cur = -1;
516 g5_switch_freq(g5_query_freq());
517
518 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
519 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
520 freq_method, volt_method);
521 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
522 g5_cpu_freqs[1].frequency/1000,
523 g5_cpu_freqs[0].frequency/1000,
524 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
525
526 rc = cpufreq_register_driver(&g5_cpufreq_driver);
527
528
529
530
531 return rc;
532
533 bail_noprops:
534 of_node_put(cpunode);
535
536 return rc;
537}
538
539#endif
540
541
542static int __init g5_pm72_cpufreq_init(struct device_node *cpus)
543{
544 struct device_node *cpuid = NULL, *hwclock = NULL, *cpunode = NULL;
545 const u8 *eeprom = NULL;
546 const u32 *valp;
547 u64 max_freq, min_freq, ih, il;
548 int has_volt = 1, rc = 0;
549
550 DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
551 " RackMac3,1...\n");
552
553
554 for (cpunode = NULL;
555 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
556 if (!strcmp(cpunode->type, "cpu"))
557 break;
558 }
559 if (cpunode == NULL) {
560 printk(KERN_ERR "cpufreq: Can't find any CPU node\n");
561 return -ENODEV;
562 }
563
564
565 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
566 if (cpuid != NULL)
567 eeprom = of_get_property(cpuid, "cpuid", NULL);
568 if (eeprom == NULL) {
569 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
570 rc = -ENODEV;
571 goto bail;
572 }
573
574
575 for (hwclock = NULL;
576 (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
577 const char *loc = of_get_property(hwclock,
578 "hwctrl-location", NULL);
579 if (loc == NULL)
580 continue;
581 if (strcmp(loc, "CPU CLOCK"))
582 continue;
583 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
584 continue;
585 break;
586 }
587 if (hwclock == NULL) {
588 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
589 rc = -ENODEV;
590 goto bail;
591 }
592
593 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
594
595
596 pfunc_cpu_getfreq =
597 pmf_find_function(hwclock, "get-frequency");
598 pfunc_cpu_setfreq_high =
599 pmf_find_function(hwclock, "set-frequency-high");
600 pfunc_cpu_setfreq_low =
601 pmf_find_function(hwclock, "set-frequency-low");
602 pfunc_slewing_done =
603 pmf_find_function(hwclock, "slewing-done");
604 pfunc_cpu0_volt_high =
605 pmf_find_function(hwclock, "set-voltage-high-0");
606 pfunc_cpu0_volt_low =
607 pmf_find_function(hwclock, "set-voltage-low-0");
608 pfunc_cpu1_volt_high =
609 pmf_find_function(hwclock, "set-voltage-high-1");
610 pfunc_cpu1_volt_low =
611 pmf_find_function(hwclock, "set-voltage-low-1");
612
613
614 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
615 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
616 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
617 rc = -ENODEV;
618 goto bail;
619 }
620
621
622 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
623 pmf_put_function(pfunc_cpu0_volt_high);
624 pmf_put_function(pfunc_cpu0_volt_low);
625 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
626 has_volt = 0;
627 }
628 if (!has_volt ||
629 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
630 pmf_put_function(pfunc_cpu1_volt_high);
631 pmf_put_function(pfunc_cpu1_volt_low);
632 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
633 }
634
635
636
637
638
639
640
641
642 valp = of_get_property(cpunode, "clock-frequency", NULL);
643 if (!valp) {
644 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
645 rc = -ENODEV;
646 goto bail;
647 }
648
649 max_freq = (*valp)/1000;
650
651
652
653
654
655 ih = *((u32 *)(eeprom + 0x10));
656 il = *((u32 *)(eeprom + 0x20));
657
658
659 if (il == ih) {
660 printk(KERN_WARNING "cpufreq: No low frequency mode available"
661 " on this model !\n");
662 rc = -ENODEV;
663 goto bail;
664 }
665
666 min_freq = 0;
667 if (ih != 0 && il != 0)
668 min_freq = (max_freq * il) / ih;
669
670
671 if (min_freq >= max_freq || min_freq < 1000) {
672 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
673 rc = -ENXIO;
674 goto bail;
675 }
676 g5_cpu_freqs[0].frequency = max_freq;
677 g5_cpu_freqs[1].frequency = min_freq;
678
679
680 transition_latency = CPUFREQ_ETERNAL;
681 g5_switch_volt = g5_pfunc_switch_volt;
682 g5_switch_freq = g5_pfunc_switch_freq;
683 g5_query_freq = g5_pfunc_query_freq;
684
685
686
687
688
689 g5_switch_volt(CPUFREQ_HIGH);
690 msleep(10);
691 g5_pmode_cur = -1;
692 g5_switch_freq(g5_query_freq());
693
694 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
695 printk(KERN_INFO "Frequency method: i2c/pfunc, "
696 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
697 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
698 g5_cpu_freqs[1].frequency/1000,
699 g5_cpu_freqs[0].frequency/1000,
700 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
701
702 rc = cpufreq_register_driver(&g5_cpufreq_driver);
703 bail:
704 if (rc != 0) {
705 pmf_put_function(pfunc_cpu_getfreq);
706 pmf_put_function(pfunc_cpu_setfreq_high);
707 pmf_put_function(pfunc_cpu_setfreq_low);
708 pmf_put_function(pfunc_slewing_done);
709 pmf_put_function(pfunc_cpu0_volt_high);
710 pmf_put_function(pfunc_cpu0_volt_low);
711 pmf_put_function(pfunc_cpu1_volt_high);
712 pmf_put_function(pfunc_cpu1_volt_low);
713 }
714 of_node_put(hwclock);
715 of_node_put(cpuid);
716 of_node_put(cpunode);
717
718 return rc;
719}
720
721static int __init g5_cpufreq_init(void)
722{
723 struct device_node *cpus;
724 int rc = 0;
725
726 cpus = of_find_node_by_path("/cpus");
727 if (cpus == NULL) {
728 DBG("No /cpus node !\n");
729 return -ENODEV;
730 }
731
732 if (machine_is_compatible("PowerMac7,2") ||
733 machine_is_compatible("PowerMac7,3") ||
734 machine_is_compatible("RackMac3,1"))
735 rc = g5_pm72_cpufreq_init(cpus);
736#ifdef CONFIG_PMAC_SMU
737 else
738 rc = g5_neo2_cpufreq_init(cpus);
739#endif
740
741 of_node_put(cpus);
742 return rc;
743}
744
745module_init(g5_cpufreq_init);
746
747
748MODULE_LICENSE("GPL");
749