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19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/spinlock.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <linux/ioport.h>
28#include <linux/pci.h>
29#include <asm/sections.h>
30#include <asm/errno.h>
31#include <asm/ohare.h>
32#include <asm/heathrow.h>
33#include <asm/keylargo.h>
34#include <asm/uninorth.h>
35#include <asm/io.h>
36#include <asm/prom.h>
37#include <asm/machdep.h>
38#include <asm/pmac_feature.h>
39#include <asm/dbdma.h>
40#include <asm/pci-bridge.h>
41#include <asm/pmac_low_i2c.h>
42
43#undef DEBUG_FEATURE
44
45#ifdef DEBUG_FEATURE
46#define DBG(fmt...) printk(KERN_DEBUG fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51#ifdef CONFIG_6xx
52extern int powersave_lowspeed;
53#endif
54
55extern int powersave_nap;
56extern struct device_node *k2_skiplist[2];
57
58
59
60
61
62DEFINE_SPINLOCK(feature_lock);
63
64#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
65#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
66
67
68
69
70
71struct macio_chip macio_chips[MAX_MACIO_CHIPS];
72
73struct macio_chip *macio_find(struct device_node *child, int type)
74{
75 while(child) {
76 int i;
77
78 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
79 if (child == macio_chips[i].of_node &&
80 (!type || macio_chips[i].type == type))
81 return &macio_chips[i];
82 child = child->parent;
83 }
84 return NULL;
85}
86EXPORT_SYMBOL_GPL(macio_find);
87
88static const char *macio_names[] =
89{
90 "Unknown",
91 "Grand Central",
92 "OHare",
93 "OHareII",
94 "Heathrow",
95 "Gatwick",
96 "Paddington",
97 "Keylargo",
98 "Pangea",
99 "Intrepid",
100 "K2",
101 "Shasta",
102};
103
104
105struct device_node *uninorth_node;
106u32 __iomem *uninorth_base;
107
108static u32 uninorth_rev;
109static int uninorth_maj;
110static void __iomem *u3_ht_base;
111
112
113
114
115
116
117typedef long (*feature_call)(struct device_node *node, long param, long value);
118
119struct feature_table_entry {
120 unsigned int selector;
121 feature_call function;
122};
123
124struct pmac_mb_def
125{
126 const char* model_string;
127 const char* model_name;
128 int model_id;
129 struct feature_table_entry* features;
130 unsigned long board_flags;
131};
132static struct pmac_mb_def pmac_mb;
133
134
135
136
137
138static inline int simple_feature_tweak(struct device_node *node, int type,
139 int reg, u32 mask, int value)
140{
141 struct macio_chip* macio;
142 unsigned long flags;
143
144 macio = macio_find(node, type);
145 if (!macio)
146 return -ENODEV;
147 LOCK(flags);
148 if (value)
149 MACIO_BIS(reg, mask);
150 else
151 MACIO_BIC(reg, mask);
152 (void)MACIO_IN32(reg);
153 UNLOCK(flags);
154
155 return 0;
156}
157
158#ifndef CONFIG_POWER4
159
160static long ohare_htw_scc_enable(struct device_node *node, long param,
161 long value)
162{
163 struct macio_chip* macio;
164 unsigned long chan_mask;
165 unsigned long fcr;
166 unsigned long flags;
167 int htw, trans;
168 unsigned long rmask;
169
170 macio = macio_find(node, 0);
171 if (!macio)
172 return -ENODEV;
173 if (!strcmp(node->name, "ch-a"))
174 chan_mask = MACIO_FLAG_SCCA_ON;
175 else if (!strcmp(node->name, "ch-b"))
176 chan_mask = MACIO_FLAG_SCCB_ON;
177 else
178 return -ENODEV;
179
180 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
181 || macio->type == macio_gatwick);
182
183 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
184 pmac_mb.model_id != PMAC_TYPE_YIKES);
185 if (value) {
186#ifdef CONFIG_ADB_PMU
187 if ((param & 0xfff) == PMAC_SCC_IRDA)
188 pmu_enable_irled(1);
189#endif
190 LOCK(flags);
191 fcr = MACIO_IN32(OHARE_FCR);
192
193 if (!(fcr & OH_SCC_ENABLE)) {
194 fcr |= OH_SCC_ENABLE;
195 if (htw) {
196
197
198
199
200
201 if (trans)
202 fcr &= ~HRW_SCC_TRANS_EN_N;
203 MACIO_OUT32(OHARE_FCR, fcr);
204 fcr |= (rmask = HRW_RESET_SCC);
205 MACIO_OUT32(OHARE_FCR, fcr);
206 } else {
207 fcr |= (rmask = OH_SCC_RESET);
208 MACIO_OUT32(OHARE_FCR, fcr);
209 }
210 UNLOCK(flags);
211 (void)MACIO_IN32(OHARE_FCR);
212 mdelay(15);
213 LOCK(flags);
214 fcr &= ~rmask;
215 MACIO_OUT32(OHARE_FCR, fcr);
216 }
217 if (chan_mask & MACIO_FLAG_SCCA_ON)
218 fcr |= OH_SCCA_IO;
219 if (chan_mask & MACIO_FLAG_SCCB_ON)
220 fcr |= OH_SCCB_IO;
221 MACIO_OUT32(OHARE_FCR, fcr);
222 macio->flags |= chan_mask;
223 UNLOCK(flags);
224 if (param & PMAC_SCC_FLAG_XMON)
225 macio->flags |= MACIO_FLAG_SCC_LOCKED;
226 } else {
227 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
228 return -EPERM;
229 LOCK(flags);
230 fcr = MACIO_IN32(OHARE_FCR);
231 if (chan_mask & MACIO_FLAG_SCCA_ON)
232 fcr &= ~OH_SCCA_IO;
233 if (chan_mask & MACIO_FLAG_SCCB_ON)
234 fcr &= ~OH_SCCB_IO;
235 MACIO_OUT32(OHARE_FCR, fcr);
236 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
237 fcr &= ~OH_SCC_ENABLE;
238 if (htw && trans)
239 fcr |= HRW_SCC_TRANS_EN_N;
240 MACIO_OUT32(OHARE_FCR, fcr);
241 }
242 macio->flags &= ~(chan_mask);
243 UNLOCK(flags);
244 mdelay(10);
245#ifdef CONFIG_ADB_PMU
246 if ((param & 0xfff) == PMAC_SCC_IRDA)
247 pmu_enable_irled(0);
248#endif
249 }
250 return 0;
251}
252
253static long ohare_floppy_enable(struct device_node *node, long param,
254 long value)
255{
256 return simple_feature_tweak(node, macio_ohare,
257 OHARE_FCR, OH_FLOPPY_ENABLE, value);
258}
259
260static long ohare_mesh_enable(struct device_node *node, long param, long value)
261{
262 return simple_feature_tweak(node, macio_ohare,
263 OHARE_FCR, OH_MESH_ENABLE, value);
264}
265
266static long ohare_ide_enable(struct device_node *node, long param, long value)
267{
268 switch(param) {
269 case 0:
270
271
272
273 if (value)
274 simple_feature_tweak(node, macio_ohare,
275 OHARE_FCR, OH_IOBUS_ENABLE, 1);
276 return simple_feature_tweak(node, macio_ohare,
277 OHARE_FCR, OH_IDE0_ENABLE, value);
278 case 1:
279 return simple_feature_tweak(node, macio_ohare,
280 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
281 default:
282 return -ENODEV;
283 }
284}
285
286static long ohare_ide_reset(struct device_node *node, long param, long value)
287{
288 switch(param) {
289 case 0:
290 return simple_feature_tweak(node, macio_ohare,
291 OHARE_FCR, OH_IDE0_RESET_N, !value);
292 case 1:
293 return simple_feature_tweak(node, macio_ohare,
294 OHARE_FCR, OH_IDE1_RESET_N, !value);
295 default:
296 return -ENODEV;
297 }
298}
299
300static long ohare_sleep_state(struct device_node *node, long param, long value)
301{
302 struct macio_chip* macio = &macio_chips[0];
303
304 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
305 return -EPERM;
306 if (value == 1) {
307 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
308 } else if (value == 0) {
309 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
310 }
311
312 return 0;
313}
314
315static long heathrow_modem_enable(struct device_node *node, long param,
316 long value)
317{
318 struct macio_chip* macio;
319 u8 gpio;
320 unsigned long flags;
321
322 macio = macio_find(node, macio_unknown);
323 if (!macio)
324 return -ENODEV;
325 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
326 if (!value) {
327 LOCK(flags);
328 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
329 UNLOCK(flags);
330 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
331 mdelay(250);
332 }
333 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
334 pmac_mb.model_id != PMAC_TYPE_YIKES) {
335 LOCK(flags);
336 if (value)
337 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
338 else
339 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
340 UNLOCK(flags);
341 (void)MACIO_IN32(HEATHROW_FCR);
342 mdelay(250);
343 }
344 if (value) {
345 LOCK(flags);
346 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
348 UNLOCK(flags); mdelay(250); LOCK(flags);
349 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
350 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
351 UNLOCK(flags); mdelay(250); LOCK(flags);
352 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
353 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
354 UNLOCK(flags); mdelay(250);
355 }
356 return 0;
357}
358
359static long heathrow_floppy_enable(struct device_node *node, long param,
360 long value)
361{
362 return simple_feature_tweak(node, macio_unknown,
363 HEATHROW_FCR,
364 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
365 value);
366}
367
368static long heathrow_mesh_enable(struct device_node *node, long param,
369 long value)
370{
371 struct macio_chip* macio;
372 unsigned long flags;
373
374 macio = macio_find(node, macio_unknown);
375 if (!macio)
376 return -ENODEV;
377 LOCK(flags);
378
379 if (value)
380 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
381 else
382 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
383 (void)MACIO_IN32(HEATHROW_FCR);
384 udelay(10);
385
386 if (value)
387 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
388 else
389 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
390 (void)MACIO_IN32(HEATHROW_MBCR);
391 udelay(10);
392 UNLOCK(flags);
393
394 return 0;
395}
396
397static long heathrow_ide_enable(struct device_node *node, long param,
398 long value)
399{
400 switch(param) {
401 case 0:
402 return simple_feature_tweak(node, macio_unknown,
403 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
404 case 1:
405 return simple_feature_tweak(node, macio_unknown,
406 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
407 default:
408 return -ENODEV;
409 }
410}
411
412static long heathrow_ide_reset(struct device_node *node, long param,
413 long value)
414{
415 switch(param) {
416 case 0:
417 return simple_feature_tweak(node, macio_unknown,
418 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
419 case 1:
420 return simple_feature_tweak(node, macio_unknown,
421 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
422 default:
423 return -ENODEV;
424 }
425}
426
427static long heathrow_bmac_enable(struct device_node *node, long param,
428 long value)
429{
430 struct macio_chip* macio;
431 unsigned long flags;
432
433 macio = macio_find(node, 0);
434 if (!macio)
435 return -ENODEV;
436 if (value) {
437 LOCK(flags);
438 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
439 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
440 UNLOCK(flags);
441 (void)MACIO_IN32(HEATHROW_FCR);
442 mdelay(10);
443 LOCK(flags);
444 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
445 UNLOCK(flags);
446 (void)MACIO_IN32(HEATHROW_FCR);
447 mdelay(10);
448 } else {
449 LOCK(flags);
450 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
451 UNLOCK(flags);
452 }
453 return 0;
454}
455
456static long heathrow_sound_enable(struct device_node *node, long param,
457 long value)
458{
459 struct macio_chip* macio;
460 unsigned long flags;
461
462
463
464
465 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
466 pmac_mb.model_id == PMAC_TYPE_YIKES)
467 return 0;
468
469 macio = macio_find(node, 0);
470 if (!macio)
471 return -ENODEV;
472 if (value) {
473 LOCK(flags);
474 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
475 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
476 UNLOCK(flags);
477 (void)MACIO_IN32(HEATHROW_FCR);
478 } else {
479 LOCK(flags);
480 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
481 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
482 UNLOCK(flags);
483 }
484 return 0;
485}
486
487static u32 save_fcr[6];
488static u32 save_mbcr;
489static struct dbdma_regs save_dbdma[13];
490static struct dbdma_regs save_alt_dbdma[13];
491
492static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
493{
494 int i;
495
496
497 for (i = 0; i < 13; i++) {
498 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
499 (macio->base + ((0x8000+i*0x100)>>2));
500 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
501 save[i].cmdptr = in_le32(&chan->cmdptr);
502 save[i].intr_sel = in_le32(&chan->intr_sel);
503 save[i].br_sel = in_le32(&chan->br_sel);
504 save[i].wait_sel = in_le32(&chan->wait_sel);
505 }
506}
507
508static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
509{
510 int i;
511
512
513 for (i = 0; i < 13; i++) {
514 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
515 (macio->base + ((0x8000+i*0x100)>>2));
516 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
517 while (in_le32(&chan->status) & ACTIVE)
518 mb();
519 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
520 out_le32(&chan->cmdptr, save[i].cmdptr);
521 out_le32(&chan->intr_sel, save[i].intr_sel);
522 out_le32(&chan->br_sel, save[i].br_sel);
523 out_le32(&chan->wait_sel, save[i].wait_sel);
524 }
525}
526
527static void heathrow_sleep(struct macio_chip *macio, int secondary)
528{
529 if (secondary) {
530 dbdma_save(macio, save_alt_dbdma);
531 save_fcr[2] = MACIO_IN32(0x38);
532 save_fcr[3] = MACIO_IN32(0x3c);
533 } else {
534 dbdma_save(macio, save_dbdma);
535 save_fcr[0] = MACIO_IN32(0x38);
536 save_fcr[1] = MACIO_IN32(0x3c);
537 save_mbcr = MACIO_IN32(0x34);
538
539 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
540 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
541
542
543 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
544 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
545
546
547 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
548 }
549
550 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
551 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
552 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
553 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
554
555
556 (void)MACIO_IN32(HEATHROW_FCR);
557}
558
559static void heathrow_wakeup(struct macio_chip *macio, int secondary)
560{
561 if (secondary) {
562 MACIO_OUT32(0x38, save_fcr[2]);
563 (void)MACIO_IN32(0x38);
564 mdelay(1);
565 MACIO_OUT32(0x3c, save_fcr[3]);
566 (void)MACIO_IN32(0x38);
567 mdelay(10);
568 dbdma_restore(macio, save_alt_dbdma);
569 } else {
570 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
571 (void)MACIO_IN32(0x38);
572 mdelay(1);
573 MACIO_OUT32(0x3c, save_fcr[1]);
574 (void)MACIO_IN32(0x38);
575 mdelay(1);
576 MACIO_OUT32(0x34, save_mbcr);
577 (void)MACIO_IN32(0x38);
578 mdelay(10);
579 dbdma_restore(macio, save_dbdma);
580 }
581}
582
583static long heathrow_sleep_state(struct device_node *node, long param,
584 long value)
585{
586 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
587 return -EPERM;
588 if (value == 1) {
589 if (macio_chips[1].type == macio_gatwick)
590 heathrow_sleep(&macio_chips[0], 1);
591 heathrow_sleep(&macio_chips[0], 0);
592 } else if (value == 0) {
593 heathrow_wakeup(&macio_chips[0], 0);
594 if (macio_chips[1].type == macio_gatwick)
595 heathrow_wakeup(&macio_chips[0], 1);
596 }
597 return 0;
598}
599
600static long core99_scc_enable(struct device_node *node, long param, long value)
601{
602 struct macio_chip* macio;
603 unsigned long flags;
604 unsigned long chan_mask;
605 u32 fcr;
606
607 macio = macio_find(node, 0);
608 if (!macio)
609 return -ENODEV;
610 if (!strcmp(node->name, "ch-a"))
611 chan_mask = MACIO_FLAG_SCCA_ON;
612 else if (!strcmp(node->name, "ch-b"))
613 chan_mask = MACIO_FLAG_SCCB_ON;
614 else
615 return -ENODEV;
616
617 if (value) {
618 int need_reset_scc = 0;
619 int need_reset_irda = 0;
620
621 LOCK(flags);
622 fcr = MACIO_IN32(KEYLARGO_FCR0);
623
624 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
625 fcr |= KL0_SCC_CELL_ENABLE;
626 need_reset_scc = 1;
627 }
628 if (chan_mask & MACIO_FLAG_SCCA_ON) {
629 fcr |= KL0_SCCA_ENABLE;
630
631 if ((param & 0xfff) == PMAC_SCC_I2S1)
632 fcr &= ~KL0_SCC_A_INTF_ENABLE;
633 else
634 fcr |= KL0_SCC_A_INTF_ENABLE;
635 }
636 if (chan_mask & MACIO_FLAG_SCCB_ON) {
637 fcr |= KL0_SCCB_ENABLE;
638
639 if ((param & 0xfff) == PMAC_SCC_IRDA) {
640 fcr &= ~KL0_SCC_B_INTF_ENABLE;
641 fcr |= KL0_IRDA_ENABLE;
642 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
643 fcr |= KL0_IRDA_SOURCE1_SEL;
644 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
645 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
646 need_reset_irda = 1;
647 } else
648 fcr |= KL0_SCC_B_INTF_ENABLE;
649 }
650 MACIO_OUT32(KEYLARGO_FCR0, fcr);
651 macio->flags |= chan_mask;
652 if (need_reset_scc) {
653 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
654 (void)MACIO_IN32(KEYLARGO_FCR0);
655 UNLOCK(flags);
656 mdelay(15);
657 LOCK(flags);
658 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
659 }
660 if (need_reset_irda) {
661 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
662 (void)MACIO_IN32(KEYLARGO_FCR0);
663 UNLOCK(flags);
664 mdelay(15);
665 LOCK(flags);
666 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
667 }
668 UNLOCK(flags);
669 if (param & PMAC_SCC_FLAG_XMON)
670 macio->flags |= MACIO_FLAG_SCC_LOCKED;
671 } else {
672 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
673 return -EPERM;
674 LOCK(flags);
675 fcr = MACIO_IN32(KEYLARGO_FCR0);
676 if (chan_mask & MACIO_FLAG_SCCA_ON)
677 fcr &= ~KL0_SCCA_ENABLE;
678 if (chan_mask & MACIO_FLAG_SCCB_ON) {
679 fcr &= ~KL0_SCCB_ENABLE;
680
681 if ((param & 0xfff) == PMAC_SCC_IRDA) {
682 fcr &= ~KL0_IRDA_ENABLE;
683 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
684 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
685 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
686 }
687 }
688 MACIO_OUT32(KEYLARGO_FCR0, fcr);
689 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
690 fcr &= ~KL0_SCC_CELL_ENABLE;
691 MACIO_OUT32(KEYLARGO_FCR0, fcr);
692 }
693 macio->flags &= ~(chan_mask);
694 UNLOCK(flags);
695 mdelay(10);
696 }
697 return 0;
698}
699
700static long
701core99_modem_enable(struct device_node *node, long param, long value)
702{
703 struct macio_chip* macio;
704 u8 gpio;
705 unsigned long flags;
706
707
708 if (node == NULL) {
709 if (macio_chips[0].type != macio_keylargo)
710 return -ENODEV;
711 node = macio_chips[0].of_node;
712 }
713 macio = macio_find(node, 0);
714 if (!macio)
715 return -ENODEV;
716 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
717 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
718 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
719
720 if (!value) {
721 LOCK(flags);
722 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
723 UNLOCK(flags);
724 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
725 mdelay(250);
726 }
727 LOCK(flags);
728 if (value) {
729 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
730 UNLOCK(flags);
731 (void)MACIO_IN32(KEYLARGO_FCR2);
732 mdelay(250);
733 } else {
734 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
735 UNLOCK(flags);
736 }
737 if (value) {
738 LOCK(flags);
739 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
740 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
741 UNLOCK(flags); mdelay(250); LOCK(flags);
742 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
743 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
744 UNLOCK(flags); mdelay(250); LOCK(flags);
745 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
746 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
747 UNLOCK(flags); mdelay(250);
748 }
749 return 0;
750}
751
752static long
753pangea_modem_enable(struct device_node *node, long param, long value)
754{
755 struct macio_chip* macio;
756 u8 gpio;
757 unsigned long flags;
758
759
760 if (node == NULL) {
761 if (macio_chips[0].type != macio_pangea &&
762 macio_chips[0].type != macio_intrepid)
763 return -ENODEV;
764 node = macio_chips[0].of_node;
765 }
766 macio = macio_find(node, 0);
767 if (!macio)
768 return -ENODEV;
769 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
770 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
771 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
772
773 if (!value) {
774 LOCK(flags);
775 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
776 UNLOCK(flags);
777 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
778 mdelay(250);
779 }
780 LOCK(flags);
781 if (value) {
782 MACIO_OUT8(KL_GPIO_MODEM_POWER,
783 KEYLARGO_GPIO_OUTPUT_ENABLE);
784 UNLOCK(flags);
785 (void)MACIO_IN32(KEYLARGO_FCR2);
786 mdelay(250);
787 } else {
788 MACIO_OUT8(KL_GPIO_MODEM_POWER,
789 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
790 UNLOCK(flags);
791 }
792 if (value) {
793 LOCK(flags);
794 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
795 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
796 UNLOCK(flags); mdelay(250); LOCK(flags);
797 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
798 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
799 UNLOCK(flags); mdelay(250); LOCK(flags);
800 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
801 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
802 UNLOCK(flags); mdelay(250);
803 }
804 return 0;
805}
806
807static long
808core99_ata100_enable(struct device_node *node, long value)
809{
810 unsigned long flags;
811 struct pci_dev *pdev = NULL;
812 u8 pbus, pid;
813 int rc;
814
815 if (uninorth_rev < 0x24)
816 return -ENODEV;
817
818 LOCK(flags);
819 if (value)
820 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
821 else
822 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
823 (void)UN_IN(UNI_N_CLOCK_CNTL);
824 UNLOCK(flags);
825 udelay(20);
826
827 if (value) {
828 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
829 pdev = pci_get_bus_and_slot(pbus, pid);
830 if (pdev == NULL)
831 return 0;
832 rc = pci_enable_device(pdev);
833 if (rc == 0)
834 pci_set_master(pdev);
835 pci_dev_put(pdev);
836 if (rc)
837 return rc;
838 }
839 return 0;
840}
841
842static long
843core99_ide_enable(struct device_node *node, long param, long value)
844{
845
846
847
848 switch(param) {
849 case 0:
850 return simple_feature_tweak(node, macio_unknown,
851 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
852 case 1:
853 return simple_feature_tweak(node, macio_unknown,
854 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
855 case 2:
856 return simple_feature_tweak(node, macio_unknown,
857 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
858 case 3:
859 return core99_ata100_enable(node, value);
860 default:
861 return -ENODEV;
862 }
863}
864
865static long
866core99_ide_reset(struct device_node *node, long param, long value)
867{
868 switch(param) {
869 case 0:
870 return simple_feature_tweak(node, macio_unknown,
871 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
872 case 1:
873 return simple_feature_tweak(node, macio_unknown,
874 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
875 case 2:
876 return simple_feature_tweak(node, macio_unknown,
877 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
878 default:
879 return -ENODEV;
880 }
881}
882
883static long
884core99_gmac_enable(struct device_node *node, long param, long value)
885{
886 unsigned long flags;
887
888 LOCK(flags);
889 if (value)
890 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
891 else
892 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
893 (void)UN_IN(UNI_N_CLOCK_CNTL);
894 UNLOCK(flags);
895 udelay(20);
896
897 return 0;
898}
899
900static long
901core99_gmac_phy_reset(struct device_node *node, long param, long value)
902{
903 unsigned long flags;
904 struct macio_chip *macio;
905
906 macio = &macio_chips[0];
907 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
908 macio->type != macio_intrepid)
909 return -ENODEV;
910
911 LOCK(flags);
912 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
913 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
914 UNLOCK(flags);
915 mdelay(10);
916 LOCK(flags);
917 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET,
918 KEYLARGO_GPIO_OUTOUT_DATA);
919 UNLOCK(flags);
920 mdelay(10);
921
922 return 0;
923}
924
925static long
926core99_sound_chip_enable(struct device_node *node, long param, long value)
927{
928 struct macio_chip* macio;
929 unsigned long flags;
930
931 macio = macio_find(node, 0);
932 if (!macio)
933 return -ENODEV;
934
935
936
937
938
939 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
940 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
941 LOCK(flags);
942 if (value)
943 MACIO_OUT8(KL_GPIO_SOUND_POWER,
944 KEYLARGO_GPIO_OUTPUT_ENABLE |
945 KEYLARGO_GPIO_OUTOUT_DATA);
946 else
947 MACIO_OUT8(KL_GPIO_SOUND_POWER,
948 KEYLARGO_GPIO_OUTPUT_ENABLE);
949 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
950 UNLOCK(flags);
951 }
952 return 0;
953}
954
955static long
956core99_airport_enable(struct device_node *node, long param, long value)
957{
958 struct macio_chip* macio;
959 unsigned long flags;
960 int state;
961
962 macio = macio_find(node, 0);
963 if (!macio)
964 return -ENODEV;
965
966
967
968
969 if (node != macio->of_node &&
970 (!node->parent || node->parent != macio->of_node))
971 return -ENODEV;
972 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
973 if (value == state)
974 return 0;
975 if (value) {
976
977
978
979
980 LOCK(flags);
981 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
982 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
983 UNLOCK(flags);
984 mdelay(10);
985 LOCK(flags);
986 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
987 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
988 UNLOCK(flags);
989
990 mdelay(10);
991
992 LOCK(flags);
993 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
994 (void)MACIO_IN32(KEYLARGO_FCR2);
995 udelay(10);
996 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
997 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
998 udelay(10);
999 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
1000 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1001 udelay(10);
1002 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1003 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1004 udelay(10);
1005 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1006 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1007 udelay(10);
1008 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1009 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1010 UNLOCK(flags);
1011 udelay(10);
1012 MACIO_OUT32(0x1c000, 0);
1013 mdelay(1);
1014 MACIO_OUT8(0x1a3e0, 0x41);
1015 (void)MACIO_IN8(0x1a3e0);
1016 udelay(10);
1017 LOCK(flags);
1018 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1019 (void)MACIO_IN32(KEYLARGO_FCR2);
1020 UNLOCK(flags);
1021 mdelay(100);
1022
1023 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1024 } else {
1025 LOCK(flags);
1026 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1027 (void)MACIO_IN32(KEYLARGO_FCR2);
1028 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1029 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1030 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1031 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1032 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1033 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1034 UNLOCK(flags);
1035
1036 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1037 }
1038 return 0;
1039}
1040
1041#ifdef CONFIG_SMP
1042static long
1043core99_reset_cpu(struct device_node *node, long param, long value)
1044{
1045 unsigned int reset_io = 0;
1046 unsigned long flags;
1047 struct macio_chip *macio;
1048 struct device_node *np;
1049 struct device_node *cpus;
1050 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1051 KL_GPIO_RESET_CPU1,
1052 KL_GPIO_RESET_CPU2,
1053 KL_GPIO_RESET_CPU3 };
1054
1055 macio = &macio_chips[0];
1056 if (macio->type != macio_keylargo)
1057 return -ENODEV;
1058
1059 cpus = of_find_node_by_path("/cpus");
1060 if (cpus == NULL)
1061 return -ENODEV;
1062 for (np = cpus->child; np != NULL; np = np->sibling) {
1063 const u32 *num = of_get_property(np, "reg", NULL);
1064 const u32 *rst = of_get_property(np, "soft-reset", NULL);
1065 if (num == NULL || rst == NULL)
1066 continue;
1067 if (param == *num) {
1068 reset_io = *rst;
1069 break;
1070 }
1071 }
1072 of_node_put(cpus);
1073 if (np == NULL || reset_io == 0)
1074 reset_io = dflt_reset_lines[param];
1075
1076 LOCK(flags);
1077 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1078 (void)MACIO_IN8(reset_io);
1079 udelay(1);
1080 MACIO_OUT8(reset_io, 0);
1081 (void)MACIO_IN8(reset_io);
1082 UNLOCK(flags);
1083
1084 return 0;
1085}
1086#endif
1087
1088static long
1089core99_usb_enable(struct device_node *node, long param, long value)
1090{
1091 struct macio_chip *macio;
1092 unsigned long flags;
1093 const char *prop;
1094 int number;
1095 u32 reg;
1096
1097 macio = &macio_chips[0];
1098 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1099 macio->type != macio_intrepid)
1100 return -ENODEV;
1101
1102 prop = of_get_property(node, "AAPL,clock-id", NULL);
1103 if (!prop)
1104 return -ENODEV;
1105 if (strncmp(prop, "usb0u048", 8) == 0)
1106 number = 0;
1107 else if (strncmp(prop, "usb1u148", 8) == 0)
1108 number = 2;
1109 else if (strncmp(prop, "usb2u248", 8) == 0)
1110 number = 4;
1111 else
1112 return -ENODEV;
1113
1114
1115
1116
1117 LOCK(flags);
1118 if (value) {
1119
1120 if (number == 0) {
1121 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1122 (void)MACIO_IN32(KEYLARGO_FCR0);
1123 UNLOCK(flags);
1124 mdelay(1);
1125 LOCK(flags);
1126 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1127 } else if (number == 2) {
1128 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1129 UNLOCK(flags);
1130 (void)MACIO_IN32(KEYLARGO_FCR0);
1131 mdelay(1);
1132 LOCK(flags);
1133 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1134 } else if (number == 4) {
1135 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1136 UNLOCK(flags);
1137 (void)MACIO_IN32(KEYLARGO_FCR1);
1138 mdelay(1);
1139 LOCK(flags);
1140 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1141 }
1142 if (number < 4) {
1143 reg = MACIO_IN32(KEYLARGO_FCR4);
1144 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1145 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1146 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1147 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1148 MACIO_OUT32(KEYLARGO_FCR4, reg);
1149 (void)MACIO_IN32(KEYLARGO_FCR4);
1150 udelay(10);
1151 } else {
1152 reg = MACIO_IN32(KEYLARGO_FCR3);
1153 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1154 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1155 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1156 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1157 MACIO_OUT32(KEYLARGO_FCR3, reg);
1158 (void)MACIO_IN32(KEYLARGO_FCR3);
1159 udelay(10);
1160 }
1161 if (macio->type == macio_intrepid) {
1162
1163 u32 test0 = 0, test1 = 0;
1164 u32 status0, status1;
1165 int timeout = 1000;
1166
1167 UNLOCK(flags);
1168 switch (number) {
1169 case 0:
1170 test0 = UNI_N_CLOCK_STOPPED_USB0;
1171 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1172 break;
1173 case 2:
1174 test0 = UNI_N_CLOCK_STOPPED_USB1;
1175 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1176 break;
1177 case 4:
1178 test0 = UNI_N_CLOCK_STOPPED_USB2;
1179 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1180 break;
1181 }
1182 do {
1183 if (--timeout <= 0) {
1184 printk(KERN_ERR "core99_usb_enable: "
1185 "Timeout waiting for clocks\n");
1186 break;
1187 }
1188 mdelay(1);
1189 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1190 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1191 } while ((status0 & test0) | (status1 & test1));
1192 LOCK(flags);
1193 }
1194 } else {
1195
1196 if (number < 4) {
1197 reg = MACIO_IN32(KEYLARGO_FCR4);
1198 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1199 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1200 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1201 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1202 MACIO_OUT32(KEYLARGO_FCR4, reg);
1203 (void)MACIO_IN32(KEYLARGO_FCR4);
1204 udelay(1);
1205 } else {
1206 reg = MACIO_IN32(KEYLARGO_FCR3);
1207 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1208 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1209 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1210 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1211 MACIO_OUT32(KEYLARGO_FCR3, reg);
1212 (void)MACIO_IN32(KEYLARGO_FCR3);
1213 udelay(1);
1214 }
1215 if (number == 0) {
1216 if (macio->type != macio_intrepid)
1217 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1218 (void)MACIO_IN32(KEYLARGO_FCR0);
1219 udelay(1);
1220 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1221 (void)MACIO_IN32(KEYLARGO_FCR0);
1222 } else if (number == 2) {
1223 if (macio->type != macio_intrepid)
1224 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1225 (void)MACIO_IN32(KEYLARGO_FCR0);
1226 udelay(1);
1227 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1228 (void)MACIO_IN32(KEYLARGO_FCR0);
1229 } else if (number == 4) {
1230 udelay(1);
1231 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1232 (void)MACIO_IN32(KEYLARGO_FCR1);
1233 }
1234 udelay(1);
1235 }
1236 UNLOCK(flags);
1237
1238 return 0;
1239}
1240
1241static long
1242core99_firewire_enable(struct device_node *node, long param, long value)
1243{
1244 unsigned long flags;
1245 struct macio_chip *macio;
1246
1247 macio = &macio_chips[0];
1248 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1249 macio->type != macio_intrepid)
1250 return -ENODEV;
1251 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1252 return -ENODEV;
1253
1254 LOCK(flags);
1255 if (value) {
1256 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1257 (void)UN_IN(UNI_N_CLOCK_CNTL);
1258 } else {
1259 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1260 (void)UN_IN(UNI_N_CLOCK_CNTL);
1261 }
1262 UNLOCK(flags);
1263 mdelay(1);
1264
1265 return 0;
1266}
1267
1268static long
1269core99_firewire_cable_power(struct device_node *node, long param, long value)
1270{
1271 unsigned long flags;
1272 struct macio_chip *macio;
1273
1274
1275 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1276 return -ENODEV;
1277 macio = &macio_chips[0];
1278 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1279 macio->type != macio_intrepid)
1280 return -ENODEV;
1281 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1282 return -ENODEV;
1283
1284 LOCK(flags);
1285 if (value) {
1286 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1287 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1288 udelay(10);
1289 } else {
1290 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1291 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1292 }
1293 UNLOCK(flags);
1294 mdelay(1);
1295
1296 return 0;
1297}
1298
1299static long
1300intrepid_aack_delay_enable(struct device_node *node, long param, long value)
1301{
1302 unsigned long flags;
1303
1304 if (uninorth_rev < 0xd2)
1305 return -ENODEV;
1306
1307 LOCK(flags);
1308 if (param)
1309 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1310 else
1311 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1312 UNLOCK(flags);
1313
1314 return 0;
1315}
1316
1317
1318#endif
1319
1320static long
1321core99_read_gpio(struct device_node *node, long param, long value)
1322{
1323 struct macio_chip *macio = &macio_chips[0];
1324
1325 return MACIO_IN8(param);
1326}
1327
1328
1329static long
1330core99_write_gpio(struct device_node *node, long param, long value)
1331{
1332 struct macio_chip *macio = &macio_chips[0];
1333
1334 MACIO_OUT8(param, (u8)(value & 0xff));
1335 return 0;
1336}
1337
1338#ifdef CONFIG_POWER4
1339static long g5_gmac_enable(struct device_node *node, long param, long value)
1340{
1341 struct macio_chip *macio = &macio_chips[0];
1342 unsigned long flags;
1343
1344 if (node == NULL)
1345 return -ENODEV;
1346
1347 LOCK(flags);
1348 if (value) {
1349 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1350 mb();
1351 k2_skiplist[0] = NULL;
1352 } else {
1353 k2_skiplist[0] = node;
1354 mb();
1355 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1356 }
1357
1358 UNLOCK(flags);
1359 mdelay(1);
1360
1361 return 0;
1362}
1363
1364static long g5_fw_enable(struct device_node *node, long param, long value)
1365{
1366 struct macio_chip *macio = &macio_chips[0];
1367 unsigned long flags;
1368
1369 if (node == NULL)
1370 return -ENODEV;
1371
1372 LOCK(flags);
1373 if (value) {
1374 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1375 mb();
1376 k2_skiplist[1] = NULL;
1377 } else {
1378 k2_skiplist[1] = node;
1379 mb();
1380 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1381 }
1382
1383 UNLOCK(flags);
1384 mdelay(1);
1385
1386 return 0;
1387}
1388
1389static long g5_mpic_enable(struct device_node *node, long param, long value)
1390{
1391 unsigned long flags;
1392 struct device_node *parent = of_get_parent(node);
1393 int is_u3;
1394
1395 if (parent == NULL)
1396 return 0;
1397 is_u3 = strcmp(parent->name, "u3") == 0 ||
1398 strcmp(parent->name, "u4") == 0;
1399 of_node_put(parent);
1400 if (!is_u3)
1401 return 0;
1402
1403 LOCK(flags);
1404 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1405 UNLOCK(flags);
1406
1407 return 0;
1408}
1409
1410static long g5_eth_phy_reset(struct device_node *node, long param, long value)
1411{
1412 struct macio_chip *macio = &macio_chips[0];
1413 struct device_node *phy;
1414 int need_reset;
1415
1416
1417
1418
1419
1420 phy = of_get_next_child(node, NULL);
1421 if (!phy)
1422 return -ENODEV;
1423 need_reset = of_device_is_compatible(phy, "B5221");
1424 of_node_put(phy);
1425 if (!need_reset)
1426 return 0;
1427
1428
1429 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
1430 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
1431
1432
1433
1434 msleep(10);
1435 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
1436
1437 return 0;
1438}
1439
1440static long g5_i2s_enable(struct device_node *node, long param, long value)
1441{
1442
1443 struct macio_chip *macio = &macio_chips[0];
1444 unsigned long flags;
1445 int cell;
1446 u32 fcrs[3][3] = {
1447 { 0,
1448 K2_FCR1_I2S0_CELL_ENABLE |
1449 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE,
1450 KL3_I2S0_CLK18_ENABLE
1451 },
1452 { KL0_SCC_A_INTF_ENABLE,
1453 K2_FCR1_I2S1_CELL_ENABLE |
1454 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE,
1455 KL3_I2S1_CLK18_ENABLE
1456 },
1457 { KL0_SCC_B_INTF_ENABLE,
1458 SH_FCR1_I2S2_CELL_ENABLE |
1459 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE,
1460 SH_FCR3_I2S2_CLK18_ENABLE
1461 },
1462 };
1463
1464 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1465 return -ENODEV;
1466 if (strncmp(node->name, "i2s-", 4))
1467 return -ENODEV;
1468 cell = node->name[4] - 'a';
1469 switch(cell) {
1470 case 0:
1471 case 1:
1472 break;
1473 case 2:
1474 if (macio->type == macio_shasta)
1475 break;
1476 default:
1477 return -ENODEV;
1478 }
1479
1480 LOCK(flags);
1481 if (value) {
1482 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
1483 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
1484 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
1485 } else {
1486 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
1487 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
1488 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
1489 }
1490 udelay(10);
1491 UNLOCK(flags);
1492
1493 return 0;
1494}
1495
1496
1497#ifdef CONFIG_SMP
1498static long g5_reset_cpu(struct device_node *node, long param, long value)
1499{
1500 unsigned int reset_io = 0;
1501 unsigned long flags;
1502 struct macio_chip *macio;
1503 struct device_node *np;
1504 struct device_node *cpus;
1505
1506 macio = &macio_chips[0];
1507 if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1508 return -ENODEV;
1509
1510 cpus = of_find_node_by_path("/cpus");
1511 if (cpus == NULL)
1512 return -ENODEV;
1513 for (np = cpus->child; np != NULL; np = np->sibling) {
1514 const u32 *num = of_get_property(np, "reg", NULL);
1515 const u32 *rst = of_get_property(np, "soft-reset", NULL);
1516 if (num == NULL || rst == NULL)
1517 continue;
1518 if (param == *num) {
1519 reset_io = *rst;
1520 break;
1521 }
1522 }
1523 of_node_put(cpus);
1524 if (np == NULL || reset_io == 0)
1525 return -ENODEV;
1526
1527 LOCK(flags);
1528 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1529 (void)MACIO_IN8(reset_io);
1530 udelay(1);
1531 MACIO_OUT8(reset_io, 0);
1532 (void)MACIO_IN8(reset_io);
1533 UNLOCK(flags);
1534
1535 return 0;
1536}
1537#endif
1538
1539
1540
1541
1542
1543
1544
1545void g5_phy_disable_cpu1(void)
1546{
1547 if (uninorth_maj == 3)
1548 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1549}
1550#endif
1551
1552#ifndef CONFIG_POWER4
1553
1554
1555#ifdef CONFIG_PM
1556static u32 save_gpio_levels[2];
1557static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
1558static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
1559static u32 save_unin_clock_ctl;
1560
1561static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
1562{
1563 u32 temp;
1564
1565 if (sleep_mode) {
1566 mdelay(1);
1567 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1568 (void)MACIO_IN32(KEYLARGO_FCR0);
1569 mdelay(1);
1570 }
1571
1572 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1573 KL0_SCC_CELL_ENABLE |
1574 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1575 KL0_IRDA_CLK19_ENABLE);
1576
1577 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1578 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1579
1580 MACIO_BIC(KEYLARGO_FCR1,
1581 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1582 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1583 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1584 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1585 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1586 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1587 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1588 KL1_UIDE_ENABLE);
1589
1590 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1591 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1592
1593 temp = MACIO_IN32(KEYLARGO_FCR3);
1594 if (macio->rev >= 2) {
1595 temp |= KL3_SHUTDOWN_PLL2X;
1596 if (sleep_mode)
1597 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1598 }
1599
1600 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1601 KL3_SHUTDOWN_PLLKW35;
1602 if (sleep_mode)
1603 temp |= KL3_SHUTDOWN_PLLKW12;
1604 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1605 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1606 if (sleep_mode)
1607 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1608 MACIO_OUT32(KEYLARGO_FCR3, temp);
1609
1610
1611 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1612}
1613
1614static void pangea_shutdown(struct macio_chip *macio, int sleep_mode)
1615{
1616 u32 temp;
1617
1618 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1619 KL0_SCC_CELL_ENABLE |
1620 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1621
1622 MACIO_BIC(KEYLARGO_FCR1,
1623 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1624 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1625 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1626 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1627 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1628 KL1_UIDE_ENABLE);
1629 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1630 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1631
1632 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1633
1634 temp = MACIO_IN32(KEYLARGO_FCR3);
1635 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1636 KL3_SHUTDOWN_PLLKW35;
1637 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1638 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1639 if (sleep_mode)
1640 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1641 MACIO_OUT32(KEYLARGO_FCR3, temp);
1642
1643
1644 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1645}
1646
1647static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
1648{
1649 u32 temp;
1650
1651 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1652 KL0_SCC_CELL_ENABLE);
1653
1654 MACIO_BIC(KEYLARGO_FCR1,
1655 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1656 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1657 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1658 KL1_EIDE0_ENABLE);
1659 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1660 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1661
1662 temp = MACIO_IN32(KEYLARGO_FCR3);
1663 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1664 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1665 if (sleep_mode)
1666 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1667 MACIO_OUT32(KEYLARGO_FCR3, temp);
1668
1669
1670 (void)MACIO_IN32(KEYLARGO_FCR0);
1671 mdelay(10);
1672}
1673
1674
1675static int
1676core99_sleep(void)
1677{
1678 struct macio_chip *macio;
1679 int i;
1680
1681 macio = &macio_chips[0];
1682 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1683 macio->type != macio_intrepid)
1684 return -ENODEV;
1685
1686
1687
1688
1689 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1690 core99_airport_enable(macio->of_node, 0, 0);
1691
1692
1693 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1694 core99_firewire_enable(NULL, 0, 0);
1695 core99_firewire_cable_power(NULL, 0, 0);
1696 }
1697
1698
1699 if (macio->type == macio_keylargo)
1700 core99_modem_enable(macio->of_node, 0, 0);
1701 else
1702 pangea_modem_enable(macio->of_node, 0, 0);
1703
1704
1705 core99_sound_chip_enable(macio->of_node, 0, 0);
1706
1707
1708
1709
1710
1711
1712 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1713 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1714 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1715 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1716 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1717 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1718
1719
1720 if (macio->type == macio_keylargo)
1721 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1722 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1723 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1724 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1725 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1726 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1727 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1728 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1729
1730
1731 dbdma_save(macio, save_dbdma);
1732
1733
1734
1735
1736 if (macio->type == macio_pangea)
1737 pangea_shutdown(macio, 1);
1738 else if (macio->type == macio_intrepid)
1739 intrepid_shutdown(macio, 1);
1740 else if (macio->type == macio_keylargo)
1741 keylargo_shutdown(macio, 1);
1742
1743
1744
1745
1746
1747 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1748
1749
1750
1751 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1752 ~(UNI_N_CLOCK_CNTL_FW));
1753 udelay(100);
1754 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1755 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1756 mdelay(10);
1757
1758
1759
1760
1761 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1762 MACIO_BIS(0x506e0, 0x00400000);
1763 MACIO_BIS(0x506e0, 0x80000000);
1764 }
1765 return 0;
1766}
1767
1768static int
1769core99_wake_up(void)
1770{
1771 struct macio_chip *macio;
1772 int i;
1773
1774 macio = &macio_chips[0];
1775 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1776 macio->type != macio_intrepid)
1777 return -ENODEV;
1778
1779
1780
1781
1782 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1783 udelay(10);
1784 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1785 udelay(10);
1786
1787
1788
1789
1790
1791 if (macio->type == macio_keylargo) {
1792 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1793 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1794 }
1795 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1796 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1797 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1798 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1799 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1800 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1801 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1802 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1803 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1804 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1805 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1806 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1807 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1808 }
1809
1810 dbdma_restore(macio, save_dbdma);
1811
1812 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1813 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1814 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1815 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1816 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1817 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1818
1819
1820 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1821 MACIO_BIC(0x506e0, 0x00400000);
1822 MACIO_BIC(0x506e0, 0x80000000);
1823 }
1824
1825 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1826 udelay(100);
1827
1828 return 0;
1829}
1830
1831#endif
1832
1833static long
1834core99_sleep_state(struct device_node *node, long param, long value)
1835{
1836
1837
1838
1839 if (param == 1) {
1840 if (value == 1) {
1841 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1842 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1843 } else {
1844 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1845 udelay(10);
1846 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1847 udelay(10);
1848 }
1849 return 0;
1850 }
1851 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1852 return -EPERM;
1853
1854#ifdef CONFIG_PM
1855 if (value == 1)
1856 return core99_sleep();
1857 else if (value == 0)
1858 return core99_wake_up();
1859
1860#endif
1861 return 0;
1862}
1863
1864#endif
1865
1866static long
1867generic_dev_can_wake(struct device_node *node, long param, long value)
1868{
1869
1870
1871
1872
1873 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1874 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1875 return 0;
1876}
1877
1878static long generic_get_mb_info(struct device_node *node, long param, long value)
1879{
1880 switch(param) {
1881 case PMAC_MB_INFO_MODEL:
1882 return pmac_mb.model_id;
1883 case PMAC_MB_INFO_FLAGS:
1884 return pmac_mb.board_flags;
1885 case PMAC_MB_INFO_NAME:
1886
1887 *((const char **)value) = pmac_mb.model_name;
1888 return 0;
1889 }
1890 return -EINVAL;
1891}
1892
1893
1894
1895
1896
1897
1898
1899
1900static struct feature_table_entry any_features[] = {
1901 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1902 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
1903 { 0, NULL }
1904};
1905
1906#ifndef CONFIG_POWER4
1907
1908
1909
1910
1911
1912static struct feature_table_entry ohare_features[] = {
1913 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1914 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1915 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1916 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1917 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1918 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1919 { 0, NULL }
1920};
1921
1922
1923
1924
1925
1926static struct feature_table_entry heathrow_desktop_features[] = {
1927 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1928 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1929 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1930 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1931 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1932 { 0, NULL }
1933};
1934
1935
1936
1937
1938static struct feature_table_entry heathrow_laptop_features[] = {
1939 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1940 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1941 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1942 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1943 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1944 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1945 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1946 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1947 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1948 { 0, NULL }
1949};
1950
1951
1952
1953
1954static struct feature_table_entry paddington_features[] = {
1955 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1956 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1957 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1958 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1959 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1960 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1961 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1962 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1963 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1964 { 0, NULL }
1965};
1966
1967
1968
1969
1970
1971
1972static struct feature_table_entry core99_features[] = {
1973 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1974 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
1975 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
1976 { PMAC_FTR_IDE_RESET, core99_ide_reset },
1977 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
1978 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
1979 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
1980 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
1981 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
1982 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
1983 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
1984#ifdef CONFIG_PM
1985 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
1986#endif
1987#ifdef CONFIG_SMP
1988 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
1989#endif
1990 { PMAC_FTR_READ_GPIO, core99_read_gpio },
1991 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
1992 { 0, NULL }
1993};
1994
1995
1996
1997static struct feature_table_entry rackmac_features[] = {
1998 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
1999 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2000 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2001 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2002 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2003 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2004 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2005 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2006 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2007#ifdef CONFIG_SMP
2008 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2009#endif
2010 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2011 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2012 { 0, NULL }
2013};
2014
2015
2016
2017static struct feature_table_entry pangea_features[] = {
2018 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2019 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2020 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2021 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2022 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2023 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2024 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2025 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2026 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2027 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2028 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2029 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2030 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2031 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2032 { 0, NULL }
2033};
2034
2035
2036
2037static struct feature_table_entry intrepid_features[] = {
2038 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2039 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2040 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2041 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2042 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2043 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2044 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2045 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2046 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2047 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2048 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2049 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2050 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2051 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2052 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2053 { 0, NULL }
2054};
2055
2056#else
2057
2058
2059
2060static struct feature_table_entry g5_features[] = {
2061 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2062 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2063 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2064 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset },
2065 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable },
2066#ifdef CONFIG_SMP
2067 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2068#endif
2069 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2070 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2071 { 0, NULL }
2072};
2073
2074#endif
2075
2076static struct pmac_mb_def pmac_mb_defs[] = {
2077#ifndef CONFIG_POWER4
2078
2079
2080
2081
2082 { "AAPL,8500", "PowerMac 8500/8600",
2083 PMAC_TYPE_PSURGE, NULL,
2084 0
2085 },
2086 { "AAPL,9500", "PowerMac 9500/9600",
2087 PMAC_TYPE_PSURGE, NULL,
2088 0
2089 },
2090 { "AAPL,7200", "PowerMac 7200",
2091 PMAC_TYPE_PSURGE, NULL,
2092 0
2093 },
2094 { "AAPL,7300", "PowerMac 7200/7300",
2095 PMAC_TYPE_PSURGE, NULL,
2096 0
2097 },
2098 { "AAPL,7500", "PowerMac 7500",
2099 PMAC_TYPE_PSURGE, NULL,
2100 0
2101 },
2102 { "AAPL,ShinerESB", "Apple Network Server",
2103 PMAC_TYPE_ANS, NULL,
2104 0
2105 },
2106 { "AAPL,e407", "Alchemy",
2107 PMAC_TYPE_ALCHEMY, NULL,
2108 0
2109 },
2110 { "AAPL,e411", "Gazelle",
2111 PMAC_TYPE_GAZELLE, NULL,
2112 0
2113 },
2114 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2115 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2116 0
2117 },
2118 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2119 PMAC_TYPE_SILK, heathrow_desktop_features,
2120 0
2121 },
2122 { "PowerMac1,1", "Blue&White G3",
2123 PMAC_TYPE_YOSEMITE, paddington_features,
2124 0
2125 },
2126 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2127 PMAC_TYPE_YIKES, paddington_features,
2128 0
2129 },
2130 { "PowerMac2,1", "iMac FireWire",
2131 PMAC_TYPE_FW_IMAC, core99_features,
2132 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2133 },
2134 { "PowerMac2,2", "iMac FireWire",
2135 PMAC_TYPE_FW_IMAC, core99_features,
2136 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2137 },
2138 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2139 PMAC_TYPE_SAWTOOTH, core99_features,
2140 PMAC_MB_OLD_CORE99
2141 },
2142 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2143 PMAC_TYPE_SAWTOOTH, core99_features,
2144 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2145 },
2146 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2147 PMAC_TYPE_SAWTOOTH, core99_features,
2148 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2149 },
2150 { "PowerMac3,4", "PowerMac G4 Silver",
2151 PMAC_TYPE_QUICKSILVER, core99_features,
2152 PMAC_MB_MAY_SLEEP
2153 },
2154 { "PowerMac3,5", "PowerMac G4 Silver",
2155 PMAC_TYPE_QUICKSILVER, core99_features,
2156 PMAC_MB_MAY_SLEEP
2157 },
2158 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2159 PMAC_TYPE_WINDTUNNEL, core99_features,
2160 PMAC_MB_MAY_SLEEP,
2161 },
2162 { "PowerMac4,1", "iMac \"Flower Power\"",
2163 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2164 PMAC_MB_MAY_SLEEP
2165 },
2166 { "PowerMac4,2", "Flat panel iMac",
2167 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2168 PMAC_MB_CAN_SLEEP
2169 },
2170 { "PowerMac4,4", "eMac",
2171 PMAC_TYPE_EMAC, core99_features,
2172 PMAC_MB_MAY_SLEEP
2173 },
2174 { "PowerMac5,1", "PowerMac G4 Cube",
2175 PMAC_TYPE_CUBE, core99_features,
2176 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2177 },
2178 { "PowerMac6,1", "Flat panel iMac",
2179 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2180 PMAC_MB_MAY_SLEEP,
2181 },
2182 { "PowerMac6,3", "Flat panel iMac",
2183 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2184 PMAC_MB_MAY_SLEEP,
2185 },
2186 { "PowerMac6,4", "eMac",
2187 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2188 PMAC_MB_MAY_SLEEP,
2189 },
2190 { "PowerMac10,1", "Mac mini",
2191 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2192 PMAC_MB_MAY_SLEEP,
2193 },
2194 { "iMac,1", "iMac (first generation)",
2195 PMAC_TYPE_ORIG_IMAC, paddington_features,
2196 0
2197 },
2198
2199
2200
2201
2202
2203 { "RackMac1,1", "XServe",
2204 PMAC_TYPE_RACKMAC, rackmac_features,
2205 0,
2206 },
2207 { "RackMac1,2", "XServe rev. 2",
2208 PMAC_TYPE_RACKMAC, rackmac_features,
2209 0,
2210 },
2211
2212
2213
2214
2215
2216 { "AAPL,3400/2400", "PowerBook 3400",
2217 PMAC_TYPE_HOOPER, ohare_features,
2218 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2219 },
2220 { "AAPL,3500", "PowerBook 3500",
2221 PMAC_TYPE_KANGA, ohare_features,
2222 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2223 },
2224 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2225 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2226 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2227 },
2228 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2229 PMAC_TYPE_101_PBOOK, paddington_features,
2230 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2231 },
2232 { "PowerBook2,1", "iBook (first generation)",
2233 PMAC_TYPE_ORIG_IBOOK, core99_features,
2234 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2235 },
2236 { "PowerBook2,2", "iBook FireWire",
2237 PMAC_TYPE_FW_IBOOK, core99_features,
2238 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2239 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2240 },
2241 { "PowerBook3,1", "PowerBook Pismo",
2242 PMAC_TYPE_PISMO, core99_features,
2243 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2244 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2245 },
2246 { "PowerBook3,2", "PowerBook Titanium",
2247 PMAC_TYPE_TITANIUM, core99_features,
2248 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2249 },
2250 { "PowerBook3,3", "PowerBook Titanium II",
2251 PMAC_TYPE_TITANIUM2, core99_features,
2252 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2253 },
2254 { "PowerBook3,4", "PowerBook Titanium III",
2255 PMAC_TYPE_TITANIUM3, core99_features,
2256 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2257 },
2258 { "PowerBook3,5", "PowerBook Titanium IV",
2259 PMAC_TYPE_TITANIUM4, core99_features,
2260 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2261 },
2262 { "PowerBook4,1", "iBook 2",
2263 PMAC_TYPE_IBOOK2, pangea_features,
2264 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2265 },
2266 { "PowerBook4,2", "iBook 2",
2267 PMAC_TYPE_IBOOK2, pangea_features,
2268 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2269 },
2270 { "PowerBook4,3", "iBook 2 rev. 2",
2271 PMAC_TYPE_IBOOK2, pangea_features,
2272 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2273 },
2274 { "PowerBook5,1", "PowerBook G4 17\"",
2275 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2276 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2277 },
2278 { "PowerBook5,2", "PowerBook G4 15\"",
2279 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2280 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2281 },
2282 { "PowerBook5,3", "PowerBook G4 17\"",
2283 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2284 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2285 },
2286 { "PowerBook5,4", "PowerBook G4 15\"",
2287 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2288 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2289 },
2290 { "PowerBook5,5", "PowerBook G4 17\"",
2291 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2292 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2293 },
2294 { "PowerBook5,6", "PowerBook G4 15\"",
2295 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2296 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2297 },
2298 { "PowerBook5,7", "PowerBook G4 17\"",
2299 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2300 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2301 },
2302 { "PowerBook5,8", "PowerBook G4 15\"",
2303 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2304 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
2305 },
2306 { "PowerBook5,9", "PowerBook G4 17\"",
2307 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2308 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
2309 },
2310 { "PowerBook6,1", "PowerBook G4 12\"",
2311 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2312 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2313 },
2314 { "PowerBook6,2", "PowerBook G4",
2315 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2316 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2317 },
2318 { "PowerBook6,3", "iBook G4",
2319 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2320 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2321 },
2322 { "PowerBook6,4", "PowerBook G4 12\"",
2323 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2324 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2325 },
2326 { "PowerBook6,5", "iBook G4",
2327 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2328 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2329 },
2330 { "PowerBook6,7", "iBook G4",
2331 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2332 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2333 },
2334 { "PowerBook6,8", "PowerBook G4 12\"",
2335 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2336 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2337 },
2338#else
2339 { "PowerMac7,2", "PowerMac G5",
2340 PMAC_TYPE_POWERMAC_G5, g5_features,
2341 0,
2342 },
2343#ifdef CONFIG_PPC64
2344 { "PowerMac7,3", "PowerMac G5",
2345 PMAC_TYPE_POWERMAC_G5, g5_features,
2346 0,
2347 },
2348 { "PowerMac8,1", "iMac G5",
2349 PMAC_TYPE_IMAC_G5, g5_features,
2350 0,
2351 },
2352 { "PowerMac9,1", "PowerMac G5",
2353 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2354 0,
2355 },
2356 { "PowerMac11,2", "PowerMac G5 Dual Core",
2357 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2358 0,
2359 },
2360 { "PowerMac12,1", "iMac G5 (iSight)",
2361 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2362 0,
2363 },
2364 { "RackMac3,1", "XServe G5",
2365 PMAC_TYPE_XSERVE_G5, g5_features,
2366 0,
2367 },
2368#endif
2369#endif
2370};
2371
2372
2373
2374
2375long pmac_do_feature_call(unsigned int selector, ...)
2376{
2377 struct device_node *node;
2378 long param, value;
2379 int i;
2380 feature_call func = NULL;
2381 va_list args;
2382
2383 if (pmac_mb.features)
2384 for (i=0; pmac_mb.features[i].function; i++)
2385 if (pmac_mb.features[i].selector == selector) {
2386 func = pmac_mb.features[i].function;
2387 break;
2388 }
2389 if (!func)
2390 for (i=0; any_features[i].function; i++)
2391 if (any_features[i].selector == selector) {
2392 func = any_features[i].function;
2393 break;
2394 }
2395 if (!func)
2396 return -ENODEV;
2397
2398 va_start(args, selector);
2399 node = (struct device_node*)va_arg(args, void*);
2400 param = va_arg(args, long);
2401 value = va_arg(args, long);
2402 va_end(args);
2403
2404 return func(node, param, value);
2405}
2406
2407static int __init probe_motherboard(void)
2408{
2409 int i;
2410 struct macio_chip *macio = &macio_chips[0];
2411 const char *model = NULL;
2412 struct device_node *dt;
2413 int ret = 0;
2414
2415
2416
2417
2418
2419 dt = of_find_node_by_name(NULL, "device-tree");
2420 if (dt != NULL)
2421 model = of_get_property(dt, "model", NULL);
2422 for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) {
2423 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2424 pmac_mb = pmac_mb_defs[i];
2425 goto found;
2426 }
2427 }
2428 for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) {
2429 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2430 pmac_mb = pmac_mb_defs[i];
2431 goto found;
2432 }
2433 }
2434
2435
2436 switch(macio->type) {
2437#ifndef CONFIG_POWER4
2438 case macio_grand_central:
2439 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2440 pmac_mb.model_name = "Unknown PowerSurge";
2441 break;
2442 case macio_ohare:
2443 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2444 pmac_mb.model_name = "Unknown OHare-based";
2445 break;
2446 case macio_heathrow:
2447 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2448 pmac_mb.model_name = "Unknown Heathrow-based";
2449 pmac_mb.features = heathrow_desktop_features;
2450 break;
2451 case macio_paddington:
2452 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2453 pmac_mb.model_name = "Unknown Paddington-based";
2454 pmac_mb.features = paddington_features;
2455 break;
2456 case macio_keylargo:
2457 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2458 pmac_mb.model_name = "Unknown Keylargo-based";
2459 pmac_mb.features = core99_features;
2460 break;
2461 case macio_pangea:
2462 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2463 pmac_mb.model_name = "Unknown Pangea-based";
2464 pmac_mb.features = pangea_features;
2465 break;
2466 case macio_intrepid:
2467 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2468 pmac_mb.model_name = "Unknown Intrepid-based";
2469 pmac_mb.features = intrepid_features;
2470 break;
2471#else
2472 case macio_keylargo2:
2473 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2474 pmac_mb.model_name = "Unknown K2-based";
2475 pmac_mb.features = g5_features;
2476 break;
2477 case macio_shasta:
2478 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
2479 pmac_mb.model_name = "Unknown Shasta-based";
2480 pmac_mb.features = g5_features;
2481 break;
2482#endif
2483 default:
2484 ret = -ENODEV;
2485 goto done;
2486 }
2487found:
2488#ifndef CONFIG_POWER4
2489
2490 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2491 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2492 if (!mach_id_ptr) {
2493 ret = -ENODEV;
2494 goto done;
2495 }
2496
2497
2498
2499
2500 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2501 pmac_mb.model_id = PMAC_TYPE_COMET;
2502 iounmap(mach_id_ptr);
2503 }
2504
2505
2506
2507
2508
2509
2510
2511 while (uninorth_base && uninorth_rev > 3) {
2512 struct device_node *cpus = of_find_node_by_path("/cpus");
2513 struct device_node *np;
2514
2515 if (!cpus || !cpus->child) {
2516 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2517 of_node_put(cpus);
2518 break;
2519 }
2520 np = cpus->child;
2521
2522 if (np->sibling) {
2523 of_node_put(cpus);
2524 break;
2525 }
2526
2527 if (of_get_property(np, "flush-on-lock", NULL)) {
2528 of_node_put(cpus);
2529 break;
2530 }
2531 of_node_put(cpus);
2532 powersave_nap = 1;
2533 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n");
2534 break;
2535 }
2536
2537
2538
2539
2540 powersave_lowspeed = 1;
2541
2542#else
2543 powersave_nap = 1;
2544#endif
2545
2546
2547 if (model && (strncmp(model, "PowerBook", 9) == 0
2548 || strncmp(model, "iBook", 5) == 0))
2549 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2550
2551
2552 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2553done:
2554 of_node_put(dt);
2555 return ret;
2556}
2557
2558
2559
2560static void __init probe_uninorth(void)
2561{
2562 const u32 *addrp;
2563 phys_addr_t address;
2564 unsigned long actrl;
2565
2566
2567 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2568 uninorth_maj = 1;
2569
2570
2571 if (uninorth_node == NULL) {
2572 uninorth_node = of_find_node_by_name(NULL, "u3");
2573 uninorth_maj = 3;
2574 }
2575
2576 if (uninorth_node == NULL) {
2577 uninorth_node = of_find_node_by_name(NULL, "u4");
2578 uninorth_maj = 4;
2579 }
2580 if (uninorth_node == NULL) {
2581 uninorth_maj = 0;
2582 return;
2583 }
2584
2585 addrp = of_get_property(uninorth_node, "reg", NULL);
2586 if (addrp == NULL)
2587 return;
2588 address = of_translate_address(uninorth_node, addrp);
2589 if (address == 0)
2590 return;
2591 uninorth_base = ioremap(address, 0x40000);
2592 if (uninorth_base == NULL)
2593 return;
2594 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2595 if (uninorth_maj == 3 || uninorth_maj == 4) {
2596 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2597 if (u3_ht_base == NULL) {
2598 iounmap(uninorth_base);
2599 return;
2600 }
2601 }
2602
2603 printk(KERN_INFO "Found %s memory controller & host bridge"
2604 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
2605 uninorth_maj == 4 ? "U4" : "UniNorth",
2606 (unsigned int)address, uninorth_rev);
2607 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2608
2609
2610
2611 if (uninorth_rev < 0x11) {
2612 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2613 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2614 UNI_N_ARB_CTRL_QACK_DELAY) <<
2615 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2616 UN_OUT(UNI_N_ARB_CTRL, actrl);
2617 }
2618
2619
2620
2621
2622
2623 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
2624 uninorth_rev == 0xc0)
2625 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2626}
2627
2628static void __init probe_one_macio(const char *name, const char *compat, int type)
2629{
2630 struct device_node* node;
2631 int i;
2632 volatile u32 __iomem *base;
2633 const u32 *addrp, *revp;
2634 phys_addr_t addr;
2635 u64 size;
2636
2637 for (node = NULL; (node = of_find_node_by_name(node, name)) != NULL;) {
2638 if (!compat)
2639 break;
2640 if (of_device_is_compatible(node, compat))
2641 break;
2642 }
2643 if (!node)
2644 return;
2645 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2646 if (!macio_chips[i].of_node)
2647 break;
2648 if (macio_chips[i].of_node == node)
2649 return;
2650 }
2651
2652 if (i >= MAX_MACIO_CHIPS) {
2653 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2654 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2655 return;
2656 }
2657 addrp = of_get_pci_address(node, 0, &size, NULL);
2658 if (addrp == NULL) {
2659 printk(KERN_ERR "pmac_feature: %s: can't find base !\n",
2660 node->full_name);
2661 return;
2662 }
2663 addr = of_translate_address(node, addrp);
2664 if (addr == 0) {
2665 printk(KERN_ERR "pmac_feature: %s, can't translate base !\n",
2666 node->full_name);
2667 return;
2668 }
2669 base = ioremap(addr, (unsigned long)size);
2670 if (!base) {
2671 printk(KERN_ERR "pmac_feature: %s, can't map mac-io chip !\n",
2672 node->full_name);
2673 return;
2674 }
2675 if (type == macio_keylargo || type == macio_keylargo2) {
2676 const u32 *did = of_get_property(node, "device-id", NULL);
2677 if (*did == 0x00000025)
2678 type = macio_pangea;
2679 if (*did == 0x0000003e)
2680 type = macio_intrepid;
2681 if (*did == 0x0000004f)
2682 type = macio_shasta;
2683 }
2684 macio_chips[i].of_node = node;
2685 macio_chips[i].type = type;
2686 macio_chips[i].base = base;
2687 macio_chips[i].flags = MACIO_FLAG_SCCA_ON | MACIO_FLAG_SCCB_ON;
2688 macio_chips[i].name = macio_names[type];
2689 revp = of_get_property(node, "revision-id", NULL);
2690 if (revp)
2691 macio_chips[i].rev = *revp;
2692 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2693 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2694}
2695
2696static int __init
2697probe_macios(void)
2698{
2699
2700 probe_one_macio("gc", NULL, macio_grand_central);
2701 probe_one_macio("ohare", NULL, macio_ohare);
2702 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2703 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2704 probe_one_macio("mac-io", "paddington", macio_paddington);
2705 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2706 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2707 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2708
2709
2710 if (macio_chips[0].type == macio_gatwick
2711 && macio_chips[1].type == macio_heathrow) {
2712 struct macio_chip temp = macio_chips[0];
2713 macio_chips[0] = macio_chips[1];
2714 macio_chips[1] = temp;
2715 }
2716 if (macio_chips[0].type == macio_ohareII
2717 && macio_chips[1].type == macio_ohare) {
2718 struct macio_chip temp = macio_chips[0];
2719 macio_chips[0] = macio_chips[1];
2720 macio_chips[1] = temp;
2721 }
2722 macio_chips[0].lbus.index = 0;
2723 macio_chips[1].lbus.index = 1;
2724
2725 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2726}
2727
2728static void __init
2729initial_serial_shutdown(struct device_node *np)
2730{
2731 int len;
2732 const struct slot_names_prop {
2733 int count;
2734 char name[1];
2735 } *slots;
2736 const char *conn;
2737 int port_type = PMAC_SCC_ASYNC;
2738 int modem = 0;
2739
2740 slots = of_get_property(np, "slot-names", &len);
2741 conn = of_get_property(np, "AAPL,connector", &len);
2742 if (conn && (strcmp(conn, "infrared") == 0))
2743 port_type = PMAC_SCC_IRDA;
2744 else if (of_device_is_compatible(np, "cobalt"))
2745 modem = 1;
2746 else if (slots && slots->count > 0) {
2747 if (strcmp(slots->name, "IrDA") == 0)
2748 port_type = PMAC_SCC_IRDA;
2749 else if (strcmp(slots->name, "Modem") == 0)
2750 modem = 1;
2751 }
2752 if (modem)
2753 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2754 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2755}
2756
2757static void __init
2758set_initial_features(void)
2759{
2760 struct device_node *np;
2761
2762
2763
2764
2765
2766
2767
2768
2769 if (macio_chips[0].type == macio_ohare) {
2770 struct macio_chip *macio = &macio_chips[0];
2771 np = of_find_node_by_name(NULL, "via-pmu");
2772 if (np)
2773 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2774 else
2775 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2776 of_node_put(np);
2777 } else if (macio_chips[1].type == macio_ohare) {
2778 struct macio_chip *macio = &macio_chips[1];
2779 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2780 }
2781
2782#ifdef CONFIG_POWER4
2783 if (macio_chips[0].type == macio_keylargo2 ||
2784 macio_chips[0].type == macio_shasta) {
2785#ifndef CONFIG_SMP
2786
2787
2788
2789
2790 np = of_find_node_by_type(NULL, "cpu");
2791 if (np != NULL)
2792 np = of_find_node_by_type(np, "cpu");
2793 if (np != NULL) {
2794 g5_phy_disable_cpu1();
2795 of_node_put(np);
2796 }
2797#endif
2798
2799
2800
2801 np = of_find_node_by_name(NULL, "ethernet");
2802 while(np) {
2803 if (of_device_is_compatible(np, "K2-GMAC"))
2804 g5_gmac_enable(np, 0, 1);
2805 np = of_find_node_by_name(np, "ethernet");
2806 }
2807
2808
2809
2810
2811
2812
2813 np = of_find_node_by_name(NULL, "firewire");
2814 while(np) {
2815 if (of_device_is_compatible(np, "pci106b,5811")) {
2816 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2817 g5_fw_enable(np, 0, 1);
2818 }
2819 np = of_find_node_by_name(np, "firewire");
2820 }
2821 }
2822#else
2823
2824 if (macio_chips[0].type == macio_keylargo ||
2825 macio_chips[0].type == macio_pangea ||
2826 macio_chips[0].type == macio_intrepid) {
2827
2828
2829
2830 np = of_find_node_by_name(NULL, "ethernet");
2831 while(np) {
2832 if (np->parent
2833 && of_device_is_compatible(np->parent, "uni-north")
2834 && of_device_is_compatible(np, "gmac"))
2835 core99_gmac_enable(np, 0, 1);
2836 np = of_find_node_by_name(np, "ethernet");
2837 }
2838
2839
2840
2841
2842
2843
2844 np = of_find_node_by_name(NULL, "firewire");
2845 while(np) {
2846 if (np->parent
2847 && of_device_is_compatible(np->parent, "uni-north")
2848 && (of_device_is_compatible(np, "pci106b,18") ||
2849 of_device_is_compatible(np, "pci106b,30") ||
2850 of_device_is_compatible(np, "pci11c1,5811"))) {
2851 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2852 core99_firewire_enable(np, 0, 1);
2853 }
2854 np = of_find_node_by_name(np, "firewire");
2855 }
2856
2857
2858 np = of_find_node_by_name(NULL, "ata-6");
2859 while(np) {
2860 if (np->parent
2861 && of_device_is_compatible(np->parent, "uni-north")
2862 && of_device_is_compatible(np, "kauai-ata")) {
2863 core99_ata100_enable(np, 1);
2864 }
2865 np = of_find_node_by_name(np, "ata-6");
2866 }
2867
2868
2869 for_each_node_by_name(np, "radio") {
2870 if (np && np->parent == macio_chips[0].of_node) {
2871 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2872 core99_airport_enable(np, 0, 0);
2873 }
2874 }
2875 of_node_put(np);
2876 }
2877
2878
2879 if (macio_chips[0].of_node)
2880 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2881 macio_chips[0].of_node, 0, 0);
2882
2883
2884 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2885 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2886 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2887 struct macio_chip *macio = &macio_chips[0];
2888 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2889 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2890 }
2891
2892#endif
2893
2894
2895 for_each_node_by_name(np, "ch-a")
2896 initial_serial_shutdown(np);
2897 of_node_put(np);
2898 for_each_node_by_name(np, "ch-b")
2899 initial_serial_shutdown(np);
2900 of_node_put(np);
2901}
2902
2903void __init
2904pmac_feature_init(void)
2905{
2906
2907 probe_uninorth();
2908
2909
2910 if (probe_macios()) {
2911 printk(KERN_WARNING "No mac-io chip found\n");
2912 return;
2913 }
2914
2915
2916 if (probe_motherboard())
2917 printk(KERN_WARNING "Unknown PowerMac !\n");
2918
2919
2920
2921
2922 set_initial_features();
2923}
2924
2925#if 0
2926static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2927{
2928 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2929 int bits[8] = { 8,16,0,32,2,4,0,0 };
2930 int freq = (frq >> 8) & 0xf;
2931
2932 if (freqs[freq] == 0)
2933 printk("%s: Unknown HT link frequency %x\n", name, freq);
2934 else
2935 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2936 name, freqs[freq],
2937 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2938}
2939
2940void __init pmac_check_ht_link(void)
2941{
2942 u32 ufreq, freq, ucfg, cfg;
2943 struct device_node *pcix_node;
2944 u8 px_bus, px_devfn;
2945 struct pci_controller *px_hose;
2946
2947 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND);
2948 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG);
2949 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ);
2950 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2951
2952 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2953 if (pcix_node == NULL) {
2954 printk("No PCI-X bridge found\n");
2955 return;
2956 }
2957 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2958 printk("PCI-X bridge found but not matched to pci\n");
2959 return;
2960 }
2961 px_hose = pci_find_hose_for_OF_device(pcix_node);
2962 if (px_hose == NULL) {
2963 printk("PCI-X bridge found but not matched to host\n");
2964 return;
2965 }
2966 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2967 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2968 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2969 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2970 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2971 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2972}
2973#endif
2974
2975
2976
2977
2978
2979static void (*pmac_early_vresume_proc)(void *data);
2980static void *pmac_early_vresume_data;
2981
2982void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
2983{
2984 if (!machine_is(powermac))
2985 return;
2986 preempt_disable();
2987 pmac_early_vresume_proc = proc;
2988 pmac_early_vresume_data = data;
2989 preempt_enable();
2990}
2991EXPORT_SYMBOL(pmac_set_early_video_resume);
2992
2993void pmac_call_early_video_resume(void)
2994{
2995 if (pmac_early_vresume_proc)
2996 pmac_early_vresume_proc(pmac_early_vresume_data);
2997}
2998
2999
3000
3001
3002
3003static struct pci_dev *pmac_agp_bridge;
3004static int (*pmac_agp_suspend)(struct pci_dev *bridge);
3005static int (*pmac_agp_resume)(struct pci_dev *bridge);
3006
3007void pmac_register_agp_pm(struct pci_dev *bridge,
3008 int (*suspend)(struct pci_dev *bridge),
3009 int (*resume)(struct pci_dev *bridge))
3010{
3011 if (suspend || resume) {
3012 pmac_agp_bridge = bridge;
3013 pmac_agp_suspend = suspend;
3014 pmac_agp_resume = resume;
3015 return;
3016 }
3017 if (bridge != pmac_agp_bridge)
3018 return;
3019 pmac_agp_suspend = pmac_agp_resume = NULL;
3020 return;
3021}
3022EXPORT_SYMBOL(pmac_register_agp_pm);
3023
3024void pmac_suspend_agp_for_card(struct pci_dev *dev)
3025{
3026 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
3027 return;
3028 if (pmac_agp_bridge->bus != dev->bus)
3029 return;
3030 pmac_agp_suspend(pmac_agp_bridge);
3031}
3032EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3033
3034void pmac_resume_agp_for_card(struct pci_dev *dev)
3035{
3036 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3037 return;
3038 if (pmac_agp_bridge->bus != dev->bus)
3039 return;
3040 pmac_agp_resume(pmac_agp_bridge);
3041}
3042EXPORT_SYMBOL(pmac_resume_agp_for_card);
3043
3044int pmac_get_uninorth_variant(void)
3045{
3046 return uninorth_maj;
3047}
3048
