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21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/mmzone.h>
24#include <linux/io.h>
25#include <linux/mm.h>
26
27#include <asm/spu.h>
28#include <asm/spu_priv1.h>
29#include <asm/lv1call.h>
30#include <asm/ps3.h>
31
32#include "../cell/spufs/spufs.h"
33#include "platform.h"
34
35
36
37
38
39
40
41
42
43
44
45enum spe_type {
46 SPE_TYPE_LOGICAL = 0,
47};
48
49
50
51
52
53
54
55struct spe_shadow {
56 u8 padding_0140[0x0140];
57 u64 int_status_class0_RW;
58 u64 int_status_class1_RW;
59 u64 int_status_class2_RW;
60 u8 padding_0158[0x0610-0x0158];
61 u64 mfc_dsisr_RW;
62 u8 padding_0618[0x0620-0x0618];
63 u64 mfc_dar_RW;
64 u8 padding_0628[0x0800-0x0628];
65 u64 mfc_dsipr_R;
66 u8 padding_0808[0x0810-0x0808];
67 u64 mfc_lscrr_R;
68 u8 padding_0818[0x0c00-0x0818];
69 u64 mfc_cer_R;
70 u8 padding_0c08[0x0f00-0x0c08];
71 u64 spe_execution_status;
72 u8 padding_0f08[0x1000-0x0f08];
73};
74
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83
84
85enum spe_ex_state {
86 SPE_EX_STATE_UNEXECUTABLE = 0,
87 SPE_EX_STATE_EXECUTABLE = 2,
88 SPE_EX_STATE_EXECUTED = 3,
89};
90
91
92
93
94
95
96
97
98struct priv1_cache {
99 u64 masks[3];
100 u64 sr1;
101 u64 tclass_id;
102};
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117struct spu_pdata {
118 u64 spe_id;
119 u64 resource_id;
120 u64 priv2_addr;
121 u64 shadow_addr;
122 struct spe_shadow __iomem *shadow;
123 struct priv1_cache cache;
124};
125
126static struct spu_pdata *spu_pdata(struct spu *spu)
127{
128 return spu->pdata;
129}
130
131#define dump_areas(_a, _b, _c, _d, _e) \
132 _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
133static void _dump_areas(unsigned int spe_id, unsigned long priv2,
134 unsigned long problem, unsigned long ls, unsigned long shadow,
135 const char* func, int line)
136{
137 pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
138 pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
139 pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
140 pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
141 pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
142}
143
144inline u64 ps3_get_spe_id(void *arg)
145{
146 return spu_pdata(arg)->spe_id;
147}
148EXPORT_SYMBOL_GPL(ps3_get_spe_id);
149
150static unsigned long get_vas_id(void)
151{
152 u64 id;
153
154 lv1_get_logical_ppe_id(&id);
155 lv1_get_virtual_address_space_id_of_ppe(id, &id);
156
157 return id;
158}
159
160static int __init construct_spu(struct spu *spu)
161{
162 int result;
163 u64 unused;
164 u64 problem_phys;
165 u64 local_store_phys;
166
167 result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
168 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
169 &spu_pdata(spu)->priv2_addr, &problem_phys,
170 &local_store_phys, &unused,
171 &spu_pdata(spu)->shadow_addr,
172 &spu_pdata(spu)->spe_id);
173 spu->problem_phys = problem_phys;
174 spu->local_store_phys = local_store_phys;
175
176 if (result) {
177 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
178 __func__, __LINE__, ps3_result(result));
179 return result;
180 }
181
182 return result;
183}
184
185static void spu_unmap(struct spu *spu)
186{
187 iounmap(spu->priv2);
188 iounmap(spu->problem);
189 iounmap((__force u8 __iomem *)spu->local_store);
190 iounmap(spu_pdata(spu)->shadow);
191}
192
193
194
195
196
197
198
199
200
201
202
203static int __init setup_areas(struct spu *spu)
204{
205 struct table {char* name; unsigned long addr; unsigned long size;};
206 static const unsigned long shadow_flags = _PAGE_NO_CACHE | 3;
207
208 spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
209 sizeof(struct spe_shadow),
210 shadow_flags);
211 if (!spu_pdata(spu)->shadow) {
212 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
213 goto fail_ioremap;
214 }
215
216 spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys,
217 LS_SIZE, _PAGE_NO_CACHE);
218
219 if (!spu->local_store) {
220 pr_debug("%s:%d: ioremap local_store failed\n",
221 __func__, __LINE__);
222 goto fail_ioremap;
223 }
224
225 spu->problem = ioremap(spu->problem_phys,
226 sizeof(struct spu_problem));
227
228 if (!spu->problem) {
229 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
230 goto fail_ioremap;
231 }
232
233 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
234 sizeof(struct spu_priv2));
235
236 if (!spu->priv2) {
237 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
238 goto fail_ioremap;
239 }
240
241 dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
242 spu->problem_phys, spu->local_store_phys,
243 spu_pdata(spu)->shadow_addr);
244 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
245 (unsigned long)spu->problem, (unsigned long)spu->local_store,
246 (unsigned long)spu_pdata(spu)->shadow);
247
248 return 0;
249
250fail_ioremap:
251 spu_unmap(spu);
252
253 return -ENOMEM;
254}
255
256static int __init setup_interrupts(struct spu *spu)
257{
258 int result;
259
260 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
261 0, &spu->irqs[0]);
262
263 if (result)
264 goto fail_alloc_0;
265
266 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
267 1, &spu->irqs[1]);
268
269 if (result)
270 goto fail_alloc_1;
271
272 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
273 2, &spu->irqs[2]);
274
275 if (result)
276 goto fail_alloc_2;
277
278 return result;
279
280fail_alloc_2:
281 ps3_spe_irq_destroy(spu->irqs[1]);
282fail_alloc_1:
283 ps3_spe_irq_destroy(spu->irqs[0]);
284fail_alloc_0:
285 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
286 return result;
287}
288
289static int __init enable_spu(struct spu *spu)
290{
291 int result;
292
293 result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
294 spu_pdata(spu)->resource_id);
295
296 if (result) {
297 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
298 __func__, __LINE__, ps3_result(result));
299 goto fail_enable;
300 }
301
302 result = setup_areas(spu);
303
304 if (result)
305 goto fail_areas;
306
307 result = setup_interrupts(spu);
308
309 if (result)
310 goto fail_interrupts;
311
312 return 0;
313
314fail_interrupts:
315 spu_unmap(spu);
316fail_areas:
317 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
318fail_enable:
319 return result;
320}
321
322static int ps3_destroy_spu(struct spu *spu)
323{
324 int result;
325
326 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
327
328 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
329 BUG_ON(result);
330
331 ps3_spe_irq_destroy(spu->irqs[2]);
332 ps3_spe_irq_destroy(spu->irqs[1]);
333 ps3_spe_irq_destroy(spu->irqs[0]);
334
335 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
336
337 spu_unmap(spu);
338
339 result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
340 BUG_ON(result);
341
342 kfree(spu->pdata);
343 spu->pdata = NULL;
344
345 return 0;
346}
347
348static int __init ps3_create_spu(struct spu *spu, void *data)
349{
350 int result;
351
352 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
353
354 spu->pdata = kzalloc(sizeof(struct spu_pdata),
355 GFP_KERNEL);
356
357 if (!spu->pdata) {
358 result = -ENOMEM;
359 goto fail_malloc;
360 }
361
362 spu_pdata(spu)->resource_id = (unsigned long)data;
363
364
365
366 spu_pdata(spu)->cache.sr1 = 0x33;
367
368 result = construct_spu(spu);
369
370 if (result)
371 goto fail_construct;
372
373
374
375 result = enable_spu(spu);
376
377 if (result)
378 goto fail_enable;
379
380
381
382
383 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
384 != SPE_EX_STATE_EXECUTED)
385 (void)0;
386
387 return result;
388
389fail_enable:
390fail_construct:
391 ps3_destroy_spu(spu);
392fail_malloc:
393 return result;
394}
395
396static int __init ps3_enumerate_spus(int (*fn)(void *data))
397{
398 int result;
399 unsigned int num_resource_id;
400 unsigned int i;
401
402 result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
403
404 pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
405 num_resource_id);
406
407
408
409
410
411
412 for (i = 0; i < num_resource_id; i++) {
413 enum ps3_spu_resource_type resource_type;
414 unsigned int resource_id;
415
416 result = ps3_repository_read_spu_resource_id(i,
417 &resource_type, &resource_id);
418
419 if (result)
420 break;
421
422 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
423 result = fn((void*)(unsigned long)resource_id);
424
425 if (result)
426 break;
427 }
428 }
429
430 if (result) {
431 printk(KERN_WARNING "%s:%d: Error initializing spus\n",
432 __func__, __LINE__);
433 return result;
434 }
435
436 return num_resource_id;
437}
438
439static int ps3_init_affinity(void)
440{
441 return 0;
442}
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457static void ps3_enable_spu(struct spu_context *ctx)
458{
459}
460
461static void ps3_disable_spu(struct spu_context *ctx)
462{
463 ctx->ops->runcntl_stop(ctx);
464}
465
466const struct spu_management_ops spu_management_ps3_ops = {
467 .enumerate_spus = ps3_enumerate_spus,
468 .create_spu = ps3_create_spu,
469 .destroy_spu = ps3_destroy_spu,
470 .enable_spu = ps3_enable_spu,
471 .disable_spu = ps3_disable_spu,
472 .init_affinity = ps3_init_affinity,
473};
474
475
476
477static void int_mask_and(struct spu *spu, int class, u64 mask)
478{
479 u64 old_mask;
480
481
482 old_mask = spu_int_mask_get(spu, class);
483 spu_int_mask_set(spu, class, old_mask & mask);
484}
485
486static void int_mask_or(struct spu *spu, int class, u64 mask)
487{
488 u64 old_mask;
489
490 old_mask = spu_int_mask_get(spu, class);
491 spu_int_mask_set(spu, class, old_mask | mask);
492}
493
494static void int_mask_set(struct spu *spu, int class, u64 mask)
495{
496 spu_pdata(spu)->cache.masks[class] = mask;
497 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
498 spu_pdata(spu)->cache.masks[class]);
499}
500
501static u64 int_mask_get(struct spu *spu, int class)
502{
503 return spu_pdata(spu)->cache.masks[class];
504}
505
506static void int_stat_clear(struct spu *spu, int class, u64 stat)
507{
508
509
510 lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
511 stat, 0);
512}
513
514static u64 int_stat_get(struct spu *spu, int class)
515{
516 u64 stat;
517
518 lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
519 return stat;
520}
521
522static void cpu_affinity_set(struct spu *spu, int cpu)
523{
524
525}
526
527static u64 mfc_dar_get(struct spu *spu)
528{
529 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
530}
531
532static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
533{
534
535}
536
537static u64 mfc_dsisr_get(struct spu *spu)
538{
539 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
540}
541
542static void mfc_sdr_setup(struct spu *spu)
543{
544
545}
546
547static void mfc_sr1_set(struct spu *spu, u64 sr1)
548{
549
550
551 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
552 | MFC_STATE1_PROBLEM_STATE_MASK);
553
554 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
555
556 spu_pdata(spu)->cache.sr1 = sr1;
557 lv1_set_spe_privilege_state_area_1_register(
558 spu_pdata(spu)->spe_id,
559 offsetof(struct spu_priv1, mfc_sr1_RW),
560 spu_pdata(spu)->cache.sr1);
561}
562
563static u64 mfc_sr1_get(struct spu *spu)
564{
565 return spu_pdata(spu)->cache.sr1;
566}
567
568static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
569{
570 spu_pdata(spu)->cache.tclass_id = tclass_id;
571 lv1_set_spe_privilege_state_area_1_register(
572 spu_pdata(spu)->spe_id,
573 offsetof(struct spu_priv1, mfc_tclass_id_RW),
574 spu_pdata(spu)->cache.tclass_id);
575}
576
577static u64 mfc_tclass_id_get(struct spu *spu)
578{
579 return spu_pdata(spu)->cache.tclass_id;
580}
581
582static void tlb_invalidate(struct spu *spu)
583{
584
585}
586
587static void resource_allocation_groupID_set(struct spu *spu, u64 id)
588{
589
590}
591
592static u64 resource_allocation_groupID_get(struct spu *spu)
593{
594 return 0;
595}
596
597static void resource_allocation_enable_set(struct spu *spu, u64 enable)
598{
599
600}
601
602static u64 resource_allocation_enable_get(struct spu *spu)
603{
604 return 0;
605}
606
607const struct spu_priv1_ops spu_priv1_ps3_ops = {
608 .int_mask_and = int_mask_and,
609 .int_mask_or = int_mask_or,
610 .int_mask_set = int_mask_set,
611 .int_mask_get = int_mask_get,
612 .int_stat_clear = int_stat_clear,
613 .int_stat_get = int_stat_get,
614 .cpu_affinity_set = cpu_affinity_set,
615 .mfc_dar_get = mfc_dar_get,
616 .mfc_dsisr_set = mfc_dsisr_set,
617 .mfc_dsisr_get = mfc_dsisr_get,
618 .mfc_sdr_setup = mfc_sdr_setup,
619 .mfc_sr1_set = mfc_sr1_set,
620 .mfc_sr1_get = mfc_sr1_get,
621 .mfc_tclass_id_set = mfc_tclass_id_set,
622 .mfc_tclass_id_get = mfc_tclass_id_get,
623 .tlb_invalidate = tlb_invalidate,
624 .resource_allocation_groupID_set = resource_allocation_groupID_set,
625 .resource_allocation_groupID_get = resource_allocation_groupID_get,
626 .resource_allocation_enable_set = resource_allocation_enable_set,
627 .resource_allocation_enable_get = resource_allocation_enable_get,
628};
629
630void ps3_spu_set_platform(void)
631{
632 spu_priv1_ops = &spu_priv1_ps3_ops;
633 spu_management_ops = &spu_management_ps3_ops;
634}
635