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24#undef DEBUG
25
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/list.h>
29#include <linux/pci.h>
30#include <linux/proc_fs.h>
31#include <linux/rbtree.h>
32#include <linux/seq_file.h>
33#include <linux/spinlock.h>
34#include <linux/of.h>
35
36#include <asm/atomic.h>
37#include <asm/eeh.h>
38#include <asm/eeh_event.h>
39#include <asm/io.h>
40#include <asm/machdep.h>
41#include <asm/ppc-pci.h>
42#include <asm/rtas.h>
43
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83
84#define EEH_MAX_FAILS 2100000
85
86
87#define PCI_BUS_RESET_WAIT_MSEC (60*1000)
88
89
90static int ibm_set_eeh_option;
91static int ibm_set_slot_reset;
92static int ibm_read_slot_reset_state;
93static int ibm_read_slot_reset_state2;
94static int ibm_slot_error_detail;
95static int ibm_get_config_addr_info;
96static int ibm_get_config_addr_info2;
97static int ibm_configure_bridge;
98
99int eeh_subsystem_enabled;
100EXPORT_SYMBOL(eeh_subsystem_enabled);
101
102
103static DEFINE_SPINLOCK(confirm_error_lock);
104
105
106
107
108
109static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
110static DEFINE_SPINLOCK(slot_errbuf_lock);
111static int eeh_error_buf_size;
112
113
114
115
116
117#define EEH_PCI_REGS_LOG_LEN 4096
118static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
119
120
121static unsigned long no_device;
122static unsigned long no_dn;
123static unsigned long no_cfg_addr;
124static unsigned long ignored_check;
125static unsigned long total_mmio_ffs;
126static unsigned long false_positives;
127static unsigned long slot_resets;
128
129#define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
130
131
132
133
134static void rtas_slot_error_detail(struct pci_dn *pdn, int severity,
135 char *driver_log, size_t loglen)
136{
137 int config_addr;
138 unsigned long flags;
139 int rc;
140
141
142 spin_lock_irqsave(&slot_errbuf_lock, flags);
143 memset(slot_errbuf, 0, eeh_error_buf_size);
144
145
146 config_addr = pdn->eeh_config_addr;
147 if (pdn->eeh_pe_config_addr)
148 config_addr = pdn->eeh_pe_config_addr;
149
150 rc = rtas_call(ibm_slot_error_detail,
151 8, 1, NULL, config_addr,
152 BUID_HI(pdn->phb->buid),
153 BUID_LO(pdn->phb->buid),
154 virt_to_phys(driver_log), loglen,
155 virt_to_phys(slot_errbuf),
156 eeh_error_buf_size,
157 severity);
158
159 if (rc == 0)
160 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
161 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
162}
163
164
165
166
167
168
169
170
171
172
173static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
174{
175 struct pci_dev *dev = pdn->pcidev;
176 u32 cfg;
177 int cap, i;
178 int n = 0;
179
180 n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name);
181 printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name);
182
183 rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
184 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
185 printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg);
186
187 rtas_read_config(pdn, PCI_COMMAND, 4, &cfg);
188 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
189 printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg);
190
191 if (!dev) {
192 printk(KERN_WARNING "EEH: no PCI device for this of node\n");
193 return n;
194 }
195
196
197 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
198 rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
199 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
200 printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg);
201
202 rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
203 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
204 printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg);
205 }
206
207
208 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
209 if (cap) {
210 rtas_read_config(pdn, cap, 4, &cfg);
211 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
212 printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg);
213
214 rtas_read_config(pdn, cap+4, 4, &cfg);
215 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
216 printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg);
217 }
218
219
220 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
221 if (cap) {
222 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
223 printk(KERN_WARNING
224 "EEH: PCI-E capabilities and status follow:\n");
225
226 for (i=0; i<=8; i++) {
227 rtas_read_config(pdn, cap+4*i, 4, &cfg);
228 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
229 printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg);
230 }
231
232 cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
233 if (cap) {
234 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
235 printk(KERN_WARNING
236 "EEH: PCI-E AER capability register set follows:\n");
237
238 for (i=0; i<14; i++) {
239 rtas_read_config(pdn, cap+4*i, 4, &cfg);
240 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
241 printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg);
242 }
243 }
244 }
245
246
247 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
248 struct device_node *dn;
249
250 for_each_child_of_node(pdn->node, dn) {
251 pdn = PCI_DN(dn);
252 if (pdn)
253 n += gather_pci_data(pdn, buf+n, len-n);
254 }
255 }
256
257 return n;
258}
259
260void eeh_slot_error_detail(struct pci_dn *pdn, int severity)
261{
262 size_t loglen = 0;
263 pci_regs_buf[0] = 0;
264
265 rtas_pci_enable(pdn, EEH_THAW_MMIO);
266 loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
267
268 rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen);
269}
270
271
272
273
274
275
276static int read_slot_reset_state(struct pci_dn *pdn, int rets[])
277{
278 int token, outputs;
279 int config_addr;
280
281 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
282 token = ibm_read_slot_reset_state2;
283 outputs = 4;
284 } else {
285 token = ibm_read_slot_reset_state;
286 rets[2] = 0;
287 outputs = 3;
288 }
289
290
291 config_addr = pdn->eeh_config_addr;
292 if (pdn->eeh_pe_config_addr)
293 config_addr = pdn->eeh_pe_config_addr;
294
295 return rtas_call(token, 3, outputs, rets, config_addr,
296 BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid));
297}
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312int
313eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs)
314{
315 int rc;
316 int rets[3];
317 int mwait;
318
319 while (1) {
320 rc = read_slot_reset_state(pdn, rets);
321 if (rc) return rc;
322 if (rets[1] == 0) return -1;
323
324 if (rets[0] != 5) return rets[0];
325
326 if (rets[2] == 0) return -1;
327
328 if (max_wait_msecs <= 0) break;
329
330 mwait = rets[2];
331 if (mwait <= 0) {
332 printk (KERN_WARNING
333 "EEH: Firmware returned bad wait value=%d\n", mwait);
334 mwait = 1000;
335 } else if (mwait > 300*1000) {
336 printk (KERN_WARNING
337 "EEH: Firmware is taking too long, time=%d\n", mwait);
338 mwait = 300*1000;
339 }
340 max_wait_msecs -= mwait;
341 msleep (mwait);
342 }
343
344 printk(KERN_WARNING "EEH: Timed out waiting for slot status\n");
345 return -2;
346}
347
348
349
350
351
352static inline unsigned long eeh_token_to_phys(unsigned long token)
353{
354 pte_t *ptep;
355 unsigned long pa;
356
357 ptep = find_linux_pte(init_mm.pgd, token);
358 if (!ptep)
359 return token;
360 pa = pte_pfn(*ptep) << PAGE_SHIFT;
361
362 return pa | (token & (PAGE_SIZE-1));
363}
364
365
366
367
368struct device_node * find_device_pe(struct device_node *dn)
369{
370 while ((dn->parent) && PCI_DN(dn->parent) &&
371 (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
372 dn = dn->parent;
373 }
374 return dn;
375}
376
377
378
379
380
381
382
383
384
385static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
386{
387 struct device_node *dn;
388
389 for_each_child_of_node(parent, dn) {
390 if (PCI_DN(dn)) {
391
392 struct pci_dev *dev = PCI_DN(dn)->pcidev;
393
394 PCI_DN(dn)->eeh_mode |= mode_flag;
395
396 if (dev && dev->driver)
397 dev->error_state = pci_channel_io_frozen;
398
399 __eeh_mark_slot(dn, mode_flag);
400 }
401 }
402}
403
404void eeh_mark_slot (struct device_node *dn, int mode_flag)
405{
406 struct pci_dev *dev;
407 dn = find_device_pe (dn);
408
409
410 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
411 dn = dn->parent;
412
413 PCI_DN(dn)->eeh_mode |= mode_flag;
414
415
416 dev = PCI_DN(dn)->pcidev;
417 if (dev)
418 dev->error_state = pci_channel_io_frozen;
419
420 __eeh_mark_slot(dn, mode_flag);
421}
422
423static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
424{
425 struct device_node *dn;
426
427 for_each_child_of_node(parent, dn) {
428 if (PCI_DN(dn)) {
429 PCI_DN(dn)->eeh_mode &= ~mode_flag;
430 PCI_DN(dn)->eeh_check_count = 0;
431 __eeh_clear_slot(dn, mode_flag);
432 }
433 }
434}
435
436void eeh_clear_slot (struct device_node *dn, int mode_flag)
437{
438 unsigned long flags;
439 spin_lock_irqsave(&confirm_error_lock, flags);
440
441 dn = find_device_pe (dn);
442
443
444 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
445 dn = dn->parent;
446
447 PCI_DN(dn)->eeh_mode &= ~mode_flag;
448 PCI_DN(dn)->eeh_check_count = 0;
449 __eeh_clear_slot(dn, mode_flag);
450 spin_unlock_irqrestore(&confirm_error_lock, flags);
451}
452
453
454
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460
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463
464
465
466
467
468int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
469{
470 int ret;
471 int rets[3];
472 unsigned long flags;
473 struct pci_dn *pdn;
474 int rc = 0;
475 const char *location;
476
477 total_mmio_ffs++;
478
479 if (!eeh_subsystem_enabled)
480 return 0;
481
482 if (!dn) {
483 no_dn++;
484 return 0;
485 }
486 dn = find_device_pe(dn);
487 pdn = PCI_DN(dn);
488
489
490 if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
491 pdn->eeh_mode & EEH_MODE_NOCHECK) {
492 ignored_check++;
493 pr_debug("EEH: Ignored check (%x) for %s %s\n",
494 pdn->eeh_mode, pci_name (dev), dn->full_name);
495 return 0;
496 }
497
498 if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) {
499 no_cfg_addr++;
500 return 0;
501 }
502
503
504
505
506
507
508
509 spin_lock_irqsave(&confirm_error_lock, flags);
510 rc = 1;
511 if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
512 pdn->eeh_check_count ++;
513 if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) {
514 location = of_get_property(dn, "ibm,loc-code", NULL);
515 printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
516 "location=%s driver=%s pci addr=%s\n",
517 pdn->eeh_check_count, location,
518 dev->driver->name, pci_name(dev));
519 printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
520 dev->driver->name);
521 dump_stack();
522 }
523 goto dn_unlock;
524 }
525
526
527
528
529
530
531
532
533 ret = read_slot_reset_state(pdn, rets);
534
535
536 if (ret != 0) {
537 printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n",
538 ret, dn->full_name);
539 false_positives++;
540 pdn->eeh_false_positives ++;
541 rc = 0;
542 goto dn_unlock;
543 }
544
545
546
547 if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) {
548 false_positives++;
549 pdn->eeh_false_positives ++;
550 rc = 0;
551 goto dn_unlock;
552 }
553
554
555 if (rets[1] != 1) {
556 printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n",
557 ret, dn->full_name);
558 false_positives++;
559 pdn->eeh_false_positives ++;
560 rc = 0;
561 goto dn_unlock;
562 }
563
564
565 if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) {
566 false_positives++;
567 pdn->eeh_false_positives ++;
568 rc = 0;
569 goto dn_unlock;
570 }
571
572 slot_resets++;
573
574
575
576
577 eeh_mark_slot (dn, EEH_MODE_ISOLATED);
578 spin_unlock_irqrestore(&confirm_error_lock, flags);
579
580 eeh_send_failure_event (dn, dev);
581
582
583
584
585 dump_stack();
586 return 1;
587
588dn_unlock:
589 spin_unlock_irqrestore(&confirm_error_lock, flags);
590 return rc;
591}
592
593EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
594
595
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605
606
607unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
608{
609 unsigned long addr;
610 struct pci_dev *dev;
611 struct device_node *dn;
612
613
614 addr = eeh_token_to_phys((unsigned long __force) token);
615 dev = pci_get_device_by_addr(addr);
616 if (!dev) {
617 no_device++;
618 return val;
619 }
620
621 dn = pci_device_to_OF_node(dev);
622 eeh_dn_check_failure (dn, dev);
623
624 pci_dev_put(dev);
625 return val;
626}
627
628EXPORT_SYMBOL(eeh_check_failure);
629
630
631
632
633
634
635
636
637
638int
639rtas_pci_enable(struct pci_dn *pdn, int function)
640{
641 int config_addr;
642 int rc;
643
644
645 config_addr = pdn->eeh_config_addr;
646 if (pdn->eeh_pe_config_addr)
647 config_addr = pdn->eeh_pe_config_addr;
648
649 rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
650 config_addr,
651 BUID_HI(pdn->phb->buid),
652 BUID_LO(pdn->phb->buid),
653 function);
654
655 if (rc)
656 printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n",
657 function, rc, pdn->node->full_name);
658
659 rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC);
660 if ((rc == 4) && (function == EEH_THAW_MMIO))
661 return 0;
662
663 return rc;
664}
665
666
667
668
669
670
671
672
673
674
675
676
677
678static void
679rtas_pci_slot_reset(struct pci_dn *pdn, int state)
680{
681 int config_addr;
682 int rc;
683
684 BUG_ON (pdn==NULL);
685
686 if (!pdn->phb) {
687 printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
688 pdn->node->full_name);
689 return;
690 }
691
692
693 config_addr = pdn->eeh_config_addr;
694 if (pdn->eeh_pe_config_addr)
695 config_addr = pdn->eeh_pe_config_addr;
696
697 rc = rtas_call(ibm_set_slot_reset,4,1, NULL,
698 config_addr,
699 BUID_HI(pdn->phb->buid),
700 BUID_LO(pdn->phb->buid),
701 state);
702 if (rc)
703 printk (KERN_WARNING "EEH: Unable to reset the failed slot,"
704 " (%d) #RST=%d dn=%s\n",
705 rc, state, pdn->node->full_name);
706}
707
708
709
710
711
712
713
714
715
716int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
717{
718 struct device_node *dn = pci_device_to_OF_node(dev);
719 struct pci_dn *pdn = PCI_DN(dn);
720
721 switch (state) {
722 case pcie_deassert_reset:
723 rtas_pci_slot_reset(pdn, 0);
724 break;
725 case pcie_hot_reset:
726 rtas_pci_slot_reset(pdn, 1);
727 break;
728 case pcie_warm_reset:
729 rtas_pci_slot_reset(pdn, 3);
730 break;
731 default:
732 return -EINVAL;
733 };
734
735 return 0;
736}
737
738
739
740
741
742
743
744
745static void __rtas_set_slot_reset(struct pci_dn *pdn)
746{
747 struct pci_dev *dev = pdn->pcidev;
748
749
750
751
752 if (dev->needs_freset)
753 rtas_pci_slot_reset(pdn, 3);
754 else
755 rtas_pci_slot_reset(pdn, 1);
756
757
758
759
760#define PCI_BUS_RST_HOLD_TIME_MSEC 250
761 msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
762
763
764
765
766 eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED);
767
768 rtas_pci_slot_reset (pdn, 0);
769
770
771
772
773#define PCI_BUS_SETTLE_TIME_MSEC 1800
774 msleep (PCI_BUS_SETTLE_TIME_MSEC);
775}
776
777int rtas_set_slot_reset(struct pci_dn *pdn)
778{
779 int i, rc;
780
781
782 for (i=0; i<3; i++) {
783 __rtas_set_slot_reset(pdn);
784
785 rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC);
786 if (rc == 0)
787 return 0;
788
789 if (rc < 0) {
790 printk(KERN_ERR "EEH: unrecoverable slot failure %s\n",
791 pdn->node->full_name);
792 return -1;
793 }
794 printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n",
795 i+1, pdn->node->full_name, rc);
796 }
797
798 return -1;
799}
800
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811
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815
816
817
818static inline void __restore_bars (struct pci_dn *pdn)
819{
820 int i;
821 u32 cmd;
822
823 if (NULL==pdn->phb) return;
824 for (i=4; i<10; i++) {
825 rtas_write_config(pdn, i*4, 4, pdn->config_space[i]);
826 }
827
828
829 rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]);
830
831#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
832#define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)])
833
834 rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1,
835 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
836
837 rtas_write_config (pdn, PCI_LATENCY_TIMER, 1,
838 SAVED_BYTE(PCI_LATENCY_TIMER));
839
840
841 rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
842
843
844
845 rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
846 if (pdn->config_space[1] & PCI_COMMAND_PARITY)
847 cmd |= PCI_COMMAND_PARITY;
848 else
849 cmd &= ~PCI_COMMAND_PARITY;
850 if (pdn->config_space[1] & PCI_COMMAND_SERR)
851 cmd |= PCI_COMMAND_SERR;
852 else
853 cmd &= ~PCI_COMMAND_SERR;
854 rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
855}
856
857
858
859
860
861
862
863void eeh_restore_bars(struct pci_dn *pdn)
864{
865 struct device_node *dn;
866 if (!pdn)
867 return;
868
869 if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code))
870 __restore_bars (pdn);
871
872 for_each_child_of_node(pdn->node, dn)
873 eeh_restore_bars (PCI_DN(dn));
874}
875
876
877
878
879
880
881
882
883
884static void eeh_save_bars(struct pci_dn *pdn)
885{
886 int i;
887
888 if (!pdn )
889 return;
890
891 for (i = 0; i < 16; i++)
892 rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]);
893}
894
895void
896rtas_configure_bridge(struct pci_dn *pdn)
897{
898 int config_addr;
899 int rc;
900
901
902 config_addr = pdn->eeh_config_addr;
903 if (pdn->eeh_pe_config_addr)
904 config_addr = pdn->eeh_pe_config_addr;
905
906 rc = rtas_call(ibm_configure_bridge,3,1, NULL,
907 config_addr,
908 BUID_HI(pdn->phb->buid),
909 BUID_LO(pdn->phb->buid));
910 if (rc) {
911 printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n",
912 rc, pdn->node->full_name);
913 }
914}
915
916
917
918
919
920
921
922#define EEH_ENABLE 1
923
924struct eeh_early_enable_info {
925 unsigned int buid_hi;
926 unsigned int buid_lo;
927};
928
929static int get_pe_addr (int config_addr,
930 struct eeh_early_enable_info *info)
931{
932 unsigned int rets[3];
933 int ret;
934
935
936 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
937
938 ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
939 config_addr, info->buid_hi, info->buid_lo, 1);
940 if (ret || (rets[0]==0))
941 return 0;
942
943 ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
944 config_addr, info->buid_hi, info->buid_lo, 0);
945 if (ret)
946 return 0;
947 return rets[0];
948 }
949
950
951 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
952 ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets,
953 config_addr, info->buid_hi, info->buid_lo, 0);
954 if (ret)
955 return 0;
956 return rets[0];
957 }
958 return 0;
959}
960
961
962static void *early_enable_eeh(struct device_node *dn, void *data)
963{
964 unsigned int rets[3];
965 struct eeh_early_enable_info *info = data;
966 int ret;
967 const u32 *class_code = of_get_property(dn, "class-code", NULL);
968 const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
969 const u32 *device_id = of_get_property(dn, "device-id", NULL);
970 const u32 *regs;
971 int enable;
972 struct pci_dn *pdn = PCI_DN(dn);
973
974 pdn->class_code = 0;
975 pdn->eeh_mode = 0;
976 pdn->eeh_check_count = 0;
977 pdn->eeh_freeze_count = 0;
978 pdn->eeh_false_positives = 0;
979
980 if (!of_device_is_available(dn))
981 return NULL;
982
983
984 if (!class_code || !vendor_id || !device_id)
985 return NULL;
986
987
988 if (dn->type && !strcmp(dn->type, "isa")) {
989 pdn->eeh_mode |= EEH_MODE_NOCHECK;
990 return NULL;
991 }
992 pdn->class_code = *class_code;
993
994
995
996 regs = of_get_property(dn, "reg", NULL);
997 if (regs) {
998
999
1000 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
1001 regs[0], info->buid_hi, info->buid_lo,
1002 EEH_ENABLE);
1003
1004 enable = 0;
1005 if (ret == 0) {
1006 pdn->eeh_config_addr = regs[0];
1007
1008
1009
1010 pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info);
1011
1012
1013
1014
1015
1016 ret = read_slot_reset_state(pdn, rets);
1017 if ((ret == 0) && (rets[1] == 1))
1018 enable = 1;
1019 }
1020
1021 if (enable) {
1022 eeh_subsystem_enabled = 1;
1023 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
1024
1025 pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n",
1026 dn->full_name, pdn->eeh_config_addr,
1027 pdn->eeh_pe_config_addr);
1028 } else {
1029
1030
1031
1032 if (dn->parent && PCI_DN(dn->parent)
1033 && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
1034
1035 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
1036 pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr;
1037 return NULL;
1038 }
1039 }
1040 } else {
1041 printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
1042 dn->full_name);
1043 }
1044
1045 eeh_save_bars(pdn);
1046 return NULL;
1047}
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062void __init eeh_init(void)
1063{
1064 struct device_node *phb, *np;
1065 struct eeh_early_enable_info info;
1066
1067 spin_lock_init(&confirm_error_lock);
1068 spin_lock_init(&slot_errbuf_lock);
1069
1070 np = of_find_node_by_path("/rtas");
1071 if (np == NULL)
1072 return;
1073
1074 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
1075 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
1076 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
1077 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
1078 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
1079 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
1080 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
1081 ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
1082
1083 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
1084 return;
1085
1086 eeh_error_buf_size = rtas_token("rtas-error-log-max");
1087 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
1088 eeh_error_buf_size = 1024;
1089 }
1090 if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
1091 printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated "
1092 "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
1093 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
1094 }
1095
1096
1097 for (phb = of_find_node_by_name(NULL, "pci"); phb;
1098 phb = of_find_node_by_name(phb, "pci")) {
1099 unsigned long buid;
1100
1101 buid = get_phb_buid(phb);
1102 if (buid == 0 || PCI_DN(phb) == NULL)
1103 continue;
1104
1105 info.buid_lo = BUID_LO(buid);
1106 info.buid_hi = BUID_HI(buid);
1107 traverse_pci_devices(phb, early_enable_eeh, &info);
1108 }
1109
1110 if (eeh_subsystem_enabled)
1111 printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
1112 else
1113 printk(KERN_WARNING "EEH: No capable adapters found\n");
1114}
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128static void eeh_add_device_early(struct device_node *dn)
1129{
1130 struct pci_controller *phb;
1131 struct eeh_early_enable_info info;
1132
1133 if (!dn || !PCI_DN(dn))
1134 return;
1135 phb = PCI_DN(dn)->phb;
1136
1137
1138 if (NULL == phb || 0 == phb->buid)
1139 return;
1140
1141 info.buid_hi = BUID_HI(phb->buid);
1142 info.buid_lo = BUID_LO(phb->buid);
1143 early_enable_eeh(dn, &info);
1144}
1145
1146void eeh_add_device_tree_early(struct device_node *dn)
1147{
1148 struct device_node *sib;
1149
1150 for_each_child_of_node(dn, sib)
1151 eeh_add_device_tree_early(sib);
1152 eeh_add_device_early(dn);
1153}
1154EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1155
1156
1157
1158
1159
1160
1161
1162
1163static void eeh_add_device_late(struct pci_dev *dev)
1164{
1165 struct device_node *dn;
1166 struct pci_dn *pdn;
1167
1168 if (!dev || !eeh_subsystem_enabled)
1169 return;
1170
1171 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1172
1173 dn = pci_device_to_OF_node(dev);
1174 pdn = PCI_DN(dn);
1175 if (pdn->pcidev == dev) {
1176 pr_debug("EEH: Already referenced !\n");
1177 return;
1178 }
1179 WARN_ON(pdn->pcidev);
1180
1181 pci_dev_get (dev);
1182 pdn->pcidev = dev;
1183
1184 pci_addr_cache_insert_device(dev);
1185 eeh_sysfs_add_device(dev);
1186}
1187
1188void eeh_add_device_tree_late(struct pci_bus *bus)
1189{
1190 struct pci_dev *dev;
1191
1192 list_for_each_entry(dev, &bus->devices, bus_list) {
1193 eeh_add_device_late(dev);
1194 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1195 struct pci_bus *subbus = dev->subordinate;
1196 if (subbus)
1197 eeh_add_device_tree_late(subbus);
1198 }
1199 }
1200}
1201EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213static void eeh_remove_device(struct pci_dev *dev)
1214{
1215 struct device_node *dn;
1216 if (!dev || !eeh_subsystem_enabled)
1217 return;
1218
1219
1220 pr_debug("EEH: Removing device %s\n", pci_name(dev));
1221
1222 dn = pci_device_to_OF_node(dev);
1223 if (PCI_DN(dn)->pcidev == NULL) {
1224 pr_debug("EEH: Not referenced !\n");
1225 return;
1226 }
1227 PCI_DN(dn)->pcidev = NULL;
1228 pci_dev_put (dev);
1229
1230 pci_addr_cache_remove_device(dev);
1231 eeh_sysfs_remove_device(dev);
1232}
1233
1234void eeh_remove_bus_device(struct pci_dev *dev)
1235{
1236 struct pci_bus *bus = dev->subordinate;
1237 struct pci_dev *child, *tmp;
1238
1239 eeh_remove_device(dev);
1240
1241 if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1242 list_for_each_entry_safe(child, tmp, &bus->devices, bus_list)
1243 eeh_remove_bus_device(child);
1244 }
1245}
1246EXPORT_SYMBOL_GPL(eeh_remove_bus_device);
1247
1248static int proc_eeh_show(struct seq_file *m, void *v)
1249{
1250 if (0 == eeh_subsystem_enabled) {
1251 seq_printf(m, "EEH Subsystem is globally disabled\n");
1252 seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs);
1253 } else {
1254 seq_printf(m, "EEH Subsystem is enabled\n");
1255 seq_printf(m,
1256 "no device=%ld\n"
1257 "no device node=%ld\n"
1258 "no config address=%ld\n"
1259 "check not wanted=%ld\n"
1260 "eeh_total_mmio_ffs=%ld\n"
1261 "eeh_false_positives=%ld\n"
1262 "eeh_slot_resets=%ld\n",
1263 no_device, no_dn, no_cfg_addr,
1264 ignored_check, total_mmio_ffs,
1265 false_positives,
1266 slot_resets);
1267 }
1268
1269 return 0;
1270}
1271
1272static int proc_eeh_open(struct inode *inode, struct file *file)
1273{
1274 return single_open(file, proc_eeh_show, NULL);
1275}
1276
1277static const struct file_operations proc_eeh_operations = {
1278 .open = proc_eeh_open,
1279 .read = seq_read,
1280 .llseek = seq_lseek,
1281 .release = single_release,
1282};
1283
1284static int __init eeh_init_proc(void)
1285{
1286 if (machine_is(pseries))
1287 proc_create("ppc64/eeh", 0, NULL, &proc_eeh_operations);
1288 return 0;
1289}
1290__initcall(eeh_init_proc);
1291