1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30#include <linux/init.h>
31#include <linux/types.h>
32#include <linux/slab.h>
33#include <linux/mm.h>
34#include <linux/spinlock.h>
35#include <linux/string.h>
36#include <linux/pci.h>
37#include <linux/dma-mapping.h>
38#include <linux/vmalloc.h>
39#include <linux/suspend.h>
40#include <linux/lmb.h>
41#include <asm/io.h>
42#include <asm/prom.h>
43#include <asm/iommu.h>
44#include <asm/pci-bridge.h>
45#include <asm/machdep.h>
46#include <asm/abs_addr.h>
47#include <asm/cacheflush.h>
48#include <asm/ppc-pci.h>
49
50#include "dart.h"
51
52
53unsigned long dart_tablebase;
54static unsigned long dart_tablesize;
55
56
57static u32 *dart_vbase;
58#ifdef CONFIG_PM
59static u32 *dart_copy;
60#endif
61
62
63static unsigned int __iomem *dart;
64
65
66static unsigned int dart_emptyval;
67
68static struct iommu_table iommu_table_dart;
69static int iommu_table_dart_inited;
70static int dart_dirty;
71static int dart_is_u4;
72
73#define DBG(...)
74
75static inline void dart_tlb_invalidate_all(void)
76{
77 unsigned long l = 0;
78 unsigned int reg, inv_bit;
79 unsigned long limit;
80
81 DBG("dart: flush\n");
82
83
84
85
86
87
88
89
90 limit = 0;
91
92 inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
93retry:
94 l = 0;
95 reg = DART_IN(DART_CNTL);
96 reg |= inv_bit;
97 DART_OUT(DART_CNTL, reg);
98
99 while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
100 l++;
101 if (l == (1L << limit)) {
102 if (limit < 4) {
103 limit++;
104 reg = DART_IN(DART_CNTL);
105 reg &= ~inv_bit;
106 DART_OUT(DART_CNTL, reg);
107 goto retry;
108 } else
109 panic("DART: TLB did not flush after waiting a long "
110 "time. Buggy U3 ?");
111 }
112}
113
114static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
115{
116 unsigned int reg;
117 unsigned int l, limit;
118
119 reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
120 (bus_rpn & DART_CNTL_U4_IONE_MASK);
121 DART_OUT(DART_CNTL, reg);
122
123 limit = 0;
124wait_more:
125 l = 0;
126 while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
127 rmb();
128 l++;
129 }
130
131 if (l == (1L << limit)) {
132 if (limit < 4) {
133 limit++;
134 goto wait_more;
135 } else
136 panic("DART: TLB did not flush after waiting a long "
137 "time. Buggy U4 ?");
138 }
139}
140
141static void dart_flush(struct iommu_table *tbl)
142{
143 mb();
144 if (dart_dirty) {
145 dart_tlb_invalidate_all();
146 dart_dirty = 0;
147 }
148}
149
150static int dart_build(struct iommu_table *tbl, long index,
151 long npages, unsigned long uaddr,
152 enum dma_data_direction direction,
153 struct dma_attrs *attrs)
154{
155 unsigned int *dp;
156 unsigned int rpn;
157 long l;
158
159 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
160
161 dp = ((unsigned int*)tbl->it_base) + index;
162
163
164
165
166 l = npages;
167 while (l--) {
168 rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
169
170 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
171
172 uaddr += DART_PAGE_SIZE;
173 }
174
175
176 mb();
177 in_be32((unsigned __iomem *)dp);
178 mb();
179
180 if (dart_is_u4) {
181 rpn = index;
182 while (npages--)
183 dart_tlb_invalidate_one(rpn++);
184 } else {
185 dart_dirty = 1;
186 }
187 return 0;
188}
189
190
191static void dart_free(struct iommu_table *tbl, long index, long npages)
192{
193 unsigned int *dp;
194
195
196
197
198
199
200 DBG("dart: free at: %lx, %lx\n", index, npages);
201
202 dp = ((unsigned int *)tbl->it_base) + index;
203
204 while (npages--)
205 *(dp++) = dart_emptyval;
206}
207
208
209static int __init dart_init(struct device_node *dart_node)
210{
211 unsigned int i;
212 unsigned long tmp, base, size;
213 struct resource r;
214
215 if (dart_tablebase == 0 || dart_tablesize == 0) {
216 printk(KERN_INFO "DART: table not allocated, using "
217 "direct DMA\n");
218 return -ENODEV;
219 }
220
221 if (of_address_to_resource(dart_node, 0, &r))
222 panic("DART: can't get register base ! ");
223
224
225
226
227
228 flush_dcache_phys_range(dart_tablebase,
229 dart_tablebase + dart_tablesize);
230
231
232
233
234
235 tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
236 dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
237 DARTMAP_RPNMASK);
238
239
240 dart = ioremap(r.start, r.end - r.start + 1);
241 if (dart == NULL)
242 panic("DART: Cannot map registers!");
243
244
245 dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
246
247
248 for (i = 0; i < dart_tablesize/4; i++)
249 dart_vbase[i] = dart_emptyval;
250
251
252 base = dart_tablebase >> DART_PAGE_SHIFT;
253 size = dart_tablesize >> DART_PAGE_SHIFT;
254 if (dart_is_u4) {
255 size &= DART_SIZE_U4_SIZE_MASK;
256 DART_OUT(DART_BASE_U4, base);
257 DART_OUT(DART_SIZE_U4, size);
258 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
259 } else {
260 size &= DART_CNTL_U3_SIZE_MASK;
261 DART_OUT(DART_CNTL,
262 DART_CNTL_U3_ENABLE |
263 (base << DART_CNTL_U3_BASE_SHIFT) |
264 (size << DART_CNTL_U3_SIZE_SHIFT));
265 }
266
267
268 dart_tlb_invalidate_all();
269
270 printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
271 dart_is_u4 ? "U4" : "U3");
272
273 return 0;
274}
275
276static void iommu_table_dart_setup(void)
277{
278 iommu_table_dart.it_busno = 0;
279 iommu_table_dart.it_offset = 0;
280
281 iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
282
283
284 iommu_table_dart.it_base = (unsigned long)dart_vbase;
285 iommu_table_dart.it_index = 0;
286 iommu_table_dart.it_blocksize = 1;
287 iommu_init_table(&iommu_table_dart, -1);
288
289
290
291
292 set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
293}
294
295static void pci_dma_dev_setup_dart(struct pci_dev *dev)
296{
297
298
299
300 set_iommu_table_base(&dev->dev, &iommu_table_dart);
301}
302
303static void pci_dma_bus_setup_dart(struct pci_bus *bus)
304{
305 struct device_node *dn;
306
307 if (!iommu_table_dart_inited) {
308 iommu_table_dart_inited = 1;
309 iommu_table_dart_setup();
310 }
311
312 dn = pci_bus_to_OF_node(bus);
313
314 if (dn)
315 PCI_DN(dn)->iommu_table = &iommu_table_dart;
316}
317
318void __init iommu_init_early_dart(void)
319{
320 struct device_node *dn;
321
322
323 dn = of_find_compatible_node(NULL, "dart", "u3-dart");
324 if (dn == NULL) {
325 dn = of_find_compatible_node(NULL, "dart", "u4-dart");
326 if (dn == NULL)
327 goto bail;
328 dart_is_u4 = 1;
329 }
330
331
332 ppc_md.tce_build = dart_build;
333 ppc_md.tce_free = dart_free;
334 ppc_md.tce_flush = dart_flush;
335
336
337 if (dart_init(dn) == 0) {
338 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart;
339 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart;
340
341
342 set_pci_dma_ops(&dma_iommu_ops);
343 return;
344 }
345
346 bail:
347
348 ppc_md.pci_dma_dev_setup = NULL;
349 ppc_md.pci_dma_bus_setup = NULL;
350
351
352 set_pci_dma_ops(&dma_direct_ops);
353}
354
355#ifdef CONFIG_PM
356static void iommu_dart_save(void)
357{
358 memcpy(dart_copy, dart_vbase, 2*1024*1024);
359}
360
361static void iommu_dart_restore(void)
362{
363 memcpy(dart_vbase, dart_copy, 2*1024*1024);
364 dart_tlb_invalidate_all();
365}
366
367static int __init iommu_init_late_dart(void)
368{
369 unsigned long tbasepfn;
370 struct page *p;
371
372
373
374 if (!dart_tablebase)
375 return 0;
376
377 tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT;
378 register_nosave_region_late(tbasepfn,
379 tbasepfn + ((1<<24) >> PAGE_SHIFT));
380
381
382
383
384
385 p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT);
386 BUG_ON(!p);
387 dart_copy = page_address(p);
388
389 ppc_md.iommu_save = iommu_dart_save;
390 ppc_md.iommu_restore = iommu_dart_restore;
391
392 return 0;
393}
394
395late_initcall(iommu_init_late_dart);
396#endif
397
398void __init alloc_dart_table(void)
399{
400
401
402
403
404
405
406
407 if (iommu_is_off)
408 return;
409
410 if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull)
411 return;
412
413
414 dart_tablesize = 1UL << 21;
415
416
417
418 dart_tablebase = (unsigned long)
419 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
420
421 printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase);
422}
423