LXR linux/arch/powerpc/sysdev/ppc4xx

   1/*
   2 * PPC4xx gpio driver
   3 *
   4 * Copyright (c) 2008 Harris Corporation
   5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   6 * Copyright (c) MontaVista Software, Inc. 2008.
   7 *
   8 * Author: Steve Falco <sfalco@harris.com>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2
  12 * as published by the Free Software Foundation.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24#include <linux/kernel.h>
  25#include <linux/init.h>
  26#include <linux/spinlock.h>
  27#include <linux/io.h>
  28#include <linux/of.h>
  29#include <linux/of_gpio.h>
  30#include <linux/gpio.h>
  31#include <linux/types.h>
  32
  33#define GPIO_MASK(gpio)         (0x80000000 >> (gpio))
  34#define GPIO_MASK2(gpio)        (0xc0000000 >> ((gpio) * 2))
  35
  36/* Physical GPIO register layout */
  37struct ppc4xx_gpio {
  38        __be32 or;
  39        __be32 tcr;
  40        __be32 osrl;
  41        __be32 osrh;
  42        __be32 tsrl;
  43        __be32 tsrh;
  44        __be32 odr;
  45        __be32 ir;
  46        __be32 rr1;
  47        __be32 rr2;
  48        __be32 rr3;
  49        __be32 reserved1;
  50        __be32 isr1l;
  51        __be32 isr1h;
  52        __be32 isr2l;
  53        __be32 isr2h;
  54        __be32 isr3l;
  55        __be32 isr3h;
  56};
  57
  58struct ppc4xx_gpio_chip {
  59        struct of_mm_gpio_chip mm_gc;
  60        spinlock_t lock;
  61};
  62
  63/*
  64 * GPIO LIB API implementation for GPIOs
  65 *
  66 * There are a maximum of 32 gpios in each gpio controller.
  67 */
  68
  69static inline struct ppc4xx_gpio_chip *
  70to_ppc4xx_gpiochip(struct of_mm_gpio_chip *mm_gc)
  71{
  72        return container_of(mm_gc, struct ppc4xx_gpio_chip, mm_gc);
  73}
  74
  75static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  76{
  77        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  78        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
  79
  80        return in_be32(&regs->ir) & GPIO_MASK(gpio);
  81}
  82
  83static inline void
  84__ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  85{
  86        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  87        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
  88
  89        if (val)
  90                setbits32(&regs->or, GPIO_MASK(gpio));
  91        else
  92                clrbits32(&regs->or, GPIO_MASK(gpio));
  93}
  94
  95static void
  96ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  97{
  98        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  99        struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
 100        unsigned long flags;
 101
 102        spin_lock_irqsave(&chip->lock, flags);
 103
 104        __ppc4xx_gpio_set(gc, gpio, val);
 105
 106        spin_unlock_irqrestore(&chip->lock, flags);
 107
 108        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
 109}
 110
 111static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 112{
 113        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 114        struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
 115        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 116        unsigned long flags;
 117
 118        spin_lock_irqsave(&chip->lock, flags);
 119
 120        /* Disable open-drain function */
 121        clrbits32(&regs->odr, GPIO_MASK(gpio));
 122
 123        /* Float the pin */
 124        clrbits32(&regs->tcr, GPIO_MASK(gpio));
 125
 126        /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
 127        if (gpio < 16) {
 128                clrbits32(&regs->osrl, GPIO_MASK2(gpio));
 129                clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
 130        } else {
 131                clrbits32(&regs->osrh, GPIO_MASK2(gpio));
 132                clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
 133        }
 134
 135        spin_unlock_irqrestore(&chip->lock, flags);
 136
 137        return 0;
 138}
 139
 140static int
 141ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 142{
 143        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 144        struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
 145        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 146        unsigned long flags;
 147
 148        spin_lock_irqsave(&chip->lock, flags);
 149
 150        /* First set initial value */
 151        __ppc4xx_gpio_set(gc, gpio, val);
 152
 153        /* Disable open-drain function */
 154        clrbits32(&regs->odr, GPIO_MASK(gpio));
 155
 156        /* Drive the pin */
 157        setbits32(&regs->tcr, GPIO_MASK(gpio));
 158
 159        /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
 160        if (gpio < 16) {
 161                clrbits32(&regs->osrl, GPIO_MASK2(gpio));
 162                clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
 163        } else {
 164                clrbits32(&regs->osrh, GPIO_MASK2(gpio));
 165                clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
 166        }
 167
 168        spin_unlock_irqrestore(&chip->lock, flags);
 169
 170        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
 171
 172        return 0;
 173}
 174
 175static int __init ppc4xx_add_gpiochips(void)
 176{
 177        struct device_node *np;
 178
 179        for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
 180                int ret;
 181                struct ppc4xx_gpio_chip *ppc4xx_gc;
 182                struct of_mm_gpio_chip *mm_gc;
 183                struct of_gpio_chip *of_gc;
 184                struct gpio_chip *gc;
 185
 186                ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
 187                if (!ppc4xx_gc) {
 188                        ret = -ENOMEM;
 189                        goto err;
 190                }
 191
 192                spin_lock_init(&ppc4xx_gc->lock);
 193
 194                mm_gc = &ppc4xx_gc->mm_gc;
 195                of_gc = &mm_gc->of_gc;
 196                gc = &of_gc->gc;
 197
 198                of_gc->gpio_cells = 2;
 199                gc->ngpio = 32;
 200                gc->direction_input = ppc4xx_gpio_dir_in;
 201                gc->direction_output = ppc4xx_gpio_dir_out;
 202                gc->get = ppc4xx_gpio_get;
 203                gc->set = ppc4xx_gpio_set;
 204
 205                ret = of_mm_gpiochip_add(np, mm_gc);
 206                if (ret)
 207                        goto err;
 208                continue;
 209err:
 210                pr_err("%s: registration failed with status %d\n",
 211                       np->full_name, ret);
 212                kfree(ppc4xx_gc);
 213                /* try others anyway */
 214        }
 215        return 0;
 216}
 217arch_initcall(ppc4xx_add_gpiochips);
 218