1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/reboot.h>
21#include <linux/slab.h>
22#include <linux/stddef.h>
23#include <linux/sched.h>
24#include <linux/signal.h>
25#include <linux/sysdev.h>
26#include <linux/device.h>
27#include <linux/bootmem.h>
28#include <linux/spinlock.h>
29#include <asm/irq.h>
30#include <asm/io.h>
31#include <asm/prom.h>
32#include <asm/qe_ic.h>
33
34#include "qe_ic.h"
35
36static DEFINE_SPINLOCK(qe_ic_lock);
37
38static struct qe_ic_info qe_ic_info[] = {
39 [1] = {
40 .mask = 0x00008000,
41 .mask_reg = QEIC_CIMR,
42 .pri_code = 0,
43 .pri_reg = QEIC_CIPWCC,
44 },
45 [2] = {
46 .mask = 0x00004000,
47 .mask_reg = QEIC_CIMR,
48 .pri_code = 1,
49 .pri_reg = QEIC_CIPWCC,
50 },
51 [3] = {
52 .mask = 0x00002000,
53 .mask_reg = QEIC_CIMR,
54 .pri_code = 2,
55 .pri_reg = QEIC_CIPWCC,
56 },
57 [10] = {
58 .mask = 0x00000040,
59 .mask_reg = QEIC_CIMR,
60 .pri_code = 1,
61 .pri_reg = QEIC_CIPZCC,
62 },
63 [11] = {
64 .mask = 0x00000020,
65 .mask_reg = QEIC_CIMR,
66 .pri_code = 2,
67 .pri_reg = QEIC_CIPZCC,
68 },
69 [12] = {
70 .mask = 0x00000010,
71 .mask_reg = QEIC_CIMR,
72 .pri_code = 3,
73 .pri_reg = QEIC_CIPZCC,
74 },
75 [13] = {
76 .mask = 0x00000008,
77 .mask_reg = QEIC_CIMR,
78 .pri_code = 4,
79 .pri_reg = QEIC_CIPZCC,
80 },
81 [14] = {
82 .mask = 0x00000004,
83 .mask_reg = QEIC_CIMR,
84 .pri_code = 5,
85 .pri_reg = QEIC_CIPZCC,
86 },
87 [15] = {
88 .mask = 0x00000002,
89 .mask_reg = QEIC_CIMR,
90 .pri_code = 6,
91 .pri_reg = QEIC_CIPZCC,
92 },
93 [20] = {
94 .mask = 0x10000000,
95 .mask_reg = QEIC_CRIMR,
96 .pri_code = 3,
97 .pri_reg = QEIC_CIPRTA,
98 },
99 [25] = {
100 .mask = 0x00800000,
101 .mask_reg = QEIC_CRIMR,
102 .pri_code = 0,
103 .pri_reg = QEIC_CIPRTB,
104 },
105 [26] = {
106 .mask = 0x00400000,
107 .mask_reg = QEIC_CRIMR,
108 .pri_code = 1,
109 .pri_reg = QEIC_CIPRTB,
110 },
111 [27] = {
112 .mask = 0x00200000,
113 .mask_reg = QEIC_CRIMR,
114 .pri_code = 2,
115 .pri_reg = QEIC_CIPRTB,
116 },
117 [28] = {
118 .mask = 0x00100000,
119 .mask_reg = QEIC_CRIMR,
120 .pri_code = 3,
121 .pri_reg = QEIC_CIPRTB,
122 },
123 [32] = {
124 .mask = 0x80000000,
125 .mask_reg = QEIC_CIMR,
126 .pri_code = 0,
127 .pri_reg = QEIC_CIPXCC,
128 },
129 [33] = {
130 .mask = 0x40000000,
131 .mask_reg = QEIC_CIMR,
132 .pri_code = 1,
133 .pri_reg = QEIC_CIPXCC,
134 },
135 [34] = {
136 .mask = 0x20000000,
137 .mask_reg = QEIC_CIMR,
138 .pri_code = 2,
139 .pri_reg = QEIC_CIPXCC,
140 },
141 [35] = {
142 .mask = 0x10000000,
143 .mask_reg = QEIC_CIMR,
144 .pri_code = 3,
145 .pri_reg = QEIC_CIPXCC,
146 },
147 [36] = {
148 .mask = 0x08000000,
149 .mask_reg = QEIC_CIMR,
150 .pri_code = 4,
151 .pri_reg = QEIC_CIPXCC,
152 },
153 [40] = {
154 .mask = 0x00800000,
155 .mask_reg = QEIC_CIMR,
156 .pri_code = 0,
157 .pri_reg = QEIC_CIPYCC,
158 },
159 [41] = {
160 .mask = 0x00400000,
161 .mask_reg = QEIC_CIMR,
162 .pri_code = 1,
163 .pri_reg = QEIC_CIPYCC,
164 },
165 [42] = {
166 .mask = 0x00200000,
167 .mask_reg = QEIC_CIMR,
168 .pri_code = 2,
169 .pri_reg = QEIC_CIPYCC,
170 },
171 [43] = {
172 .mask = 0x00100000,
173 .mask_reg = QEIC_CIMR,
174 .pri_code = 3,
175 .pri_reg = QEIC_CIPYCC,
176 },
177};
178
179static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
180{
181 return in_be32(base + (reg >> 2));
182}
183
184static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
185 u32 value)
186{
187 out_be32(base + (reg >> 2), value);
188}
189
190static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
191{
192 return irq_desc[virq].chip_data;
193}
194
195#define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
196
197static void qe_ic_unmask_irq(unsigned int virq)
198{
199 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
200 unsigned int src = virq_to_hw(virq);
201 unsigned long flags;
202 u32 temp;
203
204 spin_lock_irqsave(&qe_ic_lock, flags);
205
206 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
207 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
208 temp | qe_ic_info[src].mask);
209
210 spin_unlock_irqrestore(&qe_ic_lock, flags);
211}
212
213static void qe_ic_mask_irq(unsigned int virq)
214{
215 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
216 unsigned int src = virq_to_hw(virq);
217 unsigned long flags;
218 u32 temp;
219
220 spin_lock_irqsave(&qe_ic_lock, flags);
221
222 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
223 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
224 temp & ~qe_ic_info[src].mask);
225
226
227
228
229
230
231
232
233
234 mb();
235
236 spin_unlock_irqrestore(&qe_ic_lock, flags);
237}
238
239static struct irq_chip qe_ic_irq_chip = {
240 .typename = " QEIC ",
241 .unmask = qe_ic_unmask_irq,
242 .mask = qe_ic_mask_irq,
243 .mask_ack = qe_ic_mask_irq,
244};
245
246static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
247{
248
249 return h->of_node == NULL || h->of_node == node;
250}
251
252static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
253 irq_hw_number_t hw)
254{
255 struct qe_ic *qe_ic = h->host_data;
256 struct irq_chip *chip;
257
258 if (qe_ic_info[hw].mask == 0) {
259 printk(KERN_ERR "Can't map reserved IRQ \n");
260 return -EINVAL;
261 }
262
263 chip = &qe_ic->hc_irq;
264
265 set_irq_chip_data(virq, qe_ic);
266 get_irq_desc(virq)->status |= IRQ_LEVEL;
267
268 set_irq_chip_and_handler(virq, chip, handle_level_irq);
269
270 return 0;
271}
272
273static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
274 u32 * intspec, unsigned int intsize,
275 irq_hw_number_t * out_hwirq,
276 unsigned int *out_flags)
277{
278 *out_hwirq = intspec[0];
279 if (intsize > 1)
280 *out_flags = intspec[1];
281 else
282 *out_flags = IRQ_TYPE_NONE;
283 return 0;
284}
285
286static struct irq_host_ops qe_ic_host_ops = {
287 .match = qe_ic_host_match,
288 .map = qe_ic_host_map,
289 .xlate = qe_ic_host_xlate,
290};
291
292
293unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
294{
295 int irq;
296
297 BUG_ON(qe_ic == NULL);
298
299
300 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
301
302 if (irq == 0)
303 return NO_IRQ;
304
305 return irq_linear_revmap(qe_ic->irqhost, irq);
306}
307
308
309unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
310{
311 int irq;
312
313 BUG_ON(qe_ic == NULL);
314
315
316 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
317
318 if (irq == 0)
319 return NO_IRQ;
320
321 return irq_linear_revmap(qe_ic->irqhost, irq);
322}
323
324void __init qe_ic_init(struct device_node *node, unsigned int flags,
325 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
326 void (*high_handler)(unsigned int irq, struct irq_desc *desc))
327{
328 struct qe_ic *qe_ic;
329 struct resource res;
330 u32 temp = 0, ret, high_active = 0;
331
332 ret = of_address_to_resource(node, 0, &res);
333 if (ret)
334 return;
335
336 qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
337 if (qe_ic == NULL)
338 return;
339
340 qe_ic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
341 NR_QE_IC_INTS, &qe_ic_host_ops, 0);
342 if (qe_ic->irqhost == NULL) {
343 kfree(qe_ic);
344 return;
345 }
346
347 qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
348
349 qe_ic->irqhost->host_data = qe_ic;
350 qe_ic->hc_irq = qe_ic_irq_chip;
351
352 qe_ic->virq_high = irq_of_parse_and_map(node, 0);
353 qe_ic->virq_low = irq_of_parse_and_map(node, 1);
354
355 if (qe_ic->virq_low == NO_IRQ) {
356 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
357 kfree(qe_ic);
358 return;
359 }
360
361
362
363 if (flags & QE_IC_SPREADMODE_GRP_W)
364 temp |= CICR_GWCC;
365 if (flags & QE_IC_SPREADMODE_GRP_X)
366 temp |= CICR_GXCC;
367 if (flags & QE_IC_SPREADMODE_GRP_Y)
368 temp |= CICR_GYCC;
369 if (flags & QE_IC_SPREADMODE_GRP_Z)
370 temp |= CICR_GZCC;
371 if (flags & QE_IC_SPREADMODE_GRP_RISCA)
372 temp |= CICR_GRTA;
373 if (flags & QE_IC_SPREADMODE_GRP_RISCB)
374 temp |= CICR_GRTB;
375
376
377 if (flags & QE_IC_HIGH_SIGNAL) {
378 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
379 high_active = 1;
380 }
381
382 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
383
384 set_irq_data(qe_ic->virq_low, qe_ic);
385 set_irq_chained_handler(qe_ic->virq_low, low_handler);
386
387 if (qe_ic->virq_high != NO_IRQ &&
388 qe_ic->virq_high != qe_ic->virq_low) {
389 set_irq_data(qe_ic->virq_high, qe_ic);
390 set_irq_chained_handler(qe_ic->virq_high, high_handler);
391 }
392}
393
394void qe_ic_set_highest_priority(unsigned int virq, int high)
395{
396 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
397 unsigned int src = virq_to_hw(virq);
398 u32 temp = 0;
399
400 temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
401
402 temp &= ~CICR_HP_MASK;
403 temp |= src << CICR_HP_SHIFT;
404
405 temp &= ~CICR_HPIT_MASK;
406 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
407
408 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
409}
410
411
412int qe_ic_set_priority(unsigned int virq, unsigned int priority)
413{
414 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
415 unsigned int src = virq_to_hw(virq);
416 u32 temp;
417
418 if (priority > 8 || priority == 0)
419 return -EINVAL;
420 if (src > 127)
421 return -EINVAL;
422 if (qe_ic_info[src].pri_reg == 0)
423 return -EINVAL;
424
425 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
426
427 if (priority < 4) {
428 temp &= ~(0x7 << (32 - priority * 3));
429 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
430 } else {
431 temp &= ~(0x7 << (24 - priority * 3));
432 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
433 }
434
435 qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
436
437 return 0;
438}
439
440
441int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
442{
443 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
444 unsigned int src = virq_to_hw(virq);
445 u32 temp, control_reg = QEIC_CICNR, shift = 0;
446
447 if (priority > 2 || priority == 0)
448 return -EINVAL;
449
450 switch (qe_ic_info[src].pri_reg) {
451 case QEIC_CIPZCC:
452 shift = CICNR_ZCC1T_SHIFT;
453 break;
454 case QEIC_CIPWCC:
455 shift = CICNR_WCC1T_SHIFT;
456 break;
457 case QEIC_CIPYCC:
458 shift = CICNR_YCC1T_SHIFT;
459 break;
460 case QEIC_CIPXCC:
461 shift = CICNR_XCC1T_SHIFT;
462 break;
463 case QEIC_CIPRTA:
464 shift = CRICR_RTA1T_SHIFT;
465 control_reg = QEIC_CRICR;
466 break;
467 case QEIC_CIPRTB:
468 shift = CRICR_RTB1T_SHIFT;
469 control_reg = QEIC_CRICR;
470 break;
471 default:
472 return -EINVAL;
473 }
474
475 shift += (2 - priority) * 2;
476 temp = qe_ic_read(qe_ic->regs, control_reg);
477 temp &= ~(SIGNAL_MASK << shift);
478 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
479 qe_ic_write(qe_ic->regs, control_reg, temp);
480
481 return 0;
482}
483
484static struct sysdev_class qe_ic_sysclass = {
485 .name = "qe_ic",
486};
487
488static struct sys_device device_qe_ic = {
489 .id = 0,
490 .cls = &qe_ic_sysclass,
491};
492
493static int __init init_qe_ic_sysfs(void)
494{
495 int rc;
496
497 printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
498
499 rc = sysdev_class_register(&qe_ic_sysclass);
500 if (rc) {
501 printk(KERN_ERR "Failed registering qe_ic sys class\n");
502 return -ENODEV;
503 }
504 rc = sysdev_register(&device_qe_ic);
505 if (rc) {
506 printk(KERN_ERR "Failed registering qe_ic sys device\n");
507 return -ENODEV;
508 }
509 return 0;
510}
511
512subsys_initcall(init_qe_ic_sysfs);
513
