LXR linux/arch/sh/include/asm/irq.h

   1#ifndef __ASM_SH_IRQ_H
   2#define __ASM_SH_IRQ_H
   3
   4#include <asm/machvec.h>
   5
   6/*
   7 * A sane default based on a reasonable vector table size, platforms are
   8 * advised to cap this at the hard limit that they're interested in
   9 * through the machvec.
  10 */
  11#define NR_IRQS                 256
  12#define NR_IRQS_LEGACY          8       /* Legacy external IRQ0-7 */
  13
  14/*
  15 * Convert back and forth between INTEVT and IRQ values.
  16 */
  17#ifdef CONFIG_CPU_HAS_INTEVT
  18#define evt2irq(evt)            (((evt) >> 5) - 16)
  19#define irq2evt(irq)            (((irq) + 16) << 5)
  20#else
  21#define evt2irq(evt)            (evt)
  22#define irq2evt(irq)            (irq)
  23#endif
  24
  25/*
  26 * Simple Mask Register Support
  27 */
  28extern void make_maskreg_irq(unsigned int irq);
  29extern unsigned short *irq_mask_register;
  30
  31/*
  32 * PINT IRQs
  33 */
  34void init_IRQ_pint(void);
  35void make_imask_irq(unsigned int irq);
  36
  37static inline int generic_irq_demux(int irq)
  38{
  39        return irq;
  40}
  41
  42#define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
  43
  44void init_IRQ(void);
  45asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs);
  46
  47#ifdef CONFIG_IRQSTACKS
  48extern void irq_ctx_init(int cpu);
  49extern void irq_ctx_exit(int cpu);
  50# define __ARCH_HAS_DO_SOFTIRQ
  51#else
  52# define irq_ctx_init(cpu) do { } while (0)
  53# define irq_ctx_exit(cpu) do { } while (0)
  54#endif
  55
  56#include <asm-generic/irq.h>
  57#ifdef CONFIG_CPU_SH5
  58#include <cpu/irq.h>
  59#endif
  60
  61#endif /* __ASM_SH_IRQ_H */
  62