LXR linux/arch/sh/include/asm/system.h

   1#ifndef __ASM_SH_SYSTEM_H
   2#define __ASM_SH_SYSTEM_H
   3
   4/*
   5 * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
   6 * Copyright (C) 2002 Paul Mundt
   7 */
   8
   9#include <linux/irqflags.h>
  10#include <linux/compiler.h>
  11#include <linux/linkage.h>
  12#include <asm/types.h>
  13#include <asm/ptrace.h>
  14
  15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
  16
  17/*
  18 * A brief note on ctrl_barrier(), the control register write barrier.
  19 *
  20 * Legacy SH cores typically require a sequence of 8 nops after
  21 * modification of a control register in order for the changes to take
  22 * effect. On newer cores (like the sh4a and sh5) this is accomplished
  23 * with icbi.
  24 *
  25 * Also note that on sh4a in the icbi case we can forego a synco for the
  26 * write barrier, as it's not necessary for control registers.
  27 *
  28 * Historically we have only done this type of barrier for the MMUCR, but
  29 * it's also necessary for the CCR, so we make it generic here instead.
  30 */
  31#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
  32#define mb()            __asm__ __volatile__ ("synco": : :"memory")
  33#define rmb()           mb()
  34#define wmb()           __asm__ __volatile__ ("synco": : :"memory")
  35#define ctrl_barrier()  __icbi(0xa8000000)
  36#define read_barrier_depends()  do { } while(0)
  37#else
  38#define mb()            __asm__ __volatile__ ("": : :"memory")
  39#define rmb()           mb()
  40#define wmb()           __asm__ __volatile__ ("": : :"memory")
  41#define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
  42#define read_barrier_depends()  do { } while(0)
  43#endif
  44
  45#ifdef CONFIG_SMP
  46#define smp_mb()        mb()
  47#define smp_rmb()       rmb()
  48#define smp_wmb()       wmb()
  49#define smp_read_barrier_depends()      read_barrier_depends()
  50#else
  51#define smp_mb()        barrier()
  52#define smp_rmb()       barrier()
  53#define smp_wmb()       barrier()
  54#define smp_read_barrier_depends()      do { } while(0)
  55#endif
  56
  57#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
  58
  59#ifdef CONFIG_GUSA_RB
  60#include <asm/cmpxchg-grb.h>
  61#elif defined(CONFIG_CPU_SH4A)
  62#include <asm/cmpxchg-llsc.h>
  63#else
  64#include <asm/cmpxchg-irq.h>
  65#endif
  66
  67extern void __xchg_called_with_bad_pointer(void);
  68
  69#define __xchg(ptr, x, size)                            \
  70({                                                      \
  71        unsigned long __xchg__res;                      \
  72        volatile void *__xchg_ptr = (ptr);              \
  73        switch (size) {                                 \
  74        case 4:                                         \
  75                __xchg__res = xchg_u32(__xchg_ptr, x);  \
  76                break;                                  \
  77        case 1:                                         \
  78                __xchg__res = xchg_u8(__xchg_ptr, x);   \
  79                break;                                  \
  80        default:                                        \
  81                __xchg_called_with_bad_pointer();       \
  82                __xchg__res = x;                        \
  83                break;                                  \
  84        }                                               \
  85                                                        \
  86        __xchg__res;                                    \
  87})
  88
  89#define xchg(ptr,x)     \
  90        ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
  91
  92/* This function doesn't exist, so you'll get a linker error
  93 * if something tries to do an invalid cmpxchg(). */
  94extern void __cmpxchg_called_with_bad_pointer(void);
  95
  96#define __HAVE_ARCH_CMPXCHG 1
  97
  98static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
  99                unsigned long new, int size)
 100{
 101        switch (size) {
 102        case 4:
 103                return __cmpxchg_u32(ptr, old, new);
 104        }
 105        __cmpxchg_called_with_bad_pointer();
 106        return old;
 107}
 108
 109#define cmpxchg(ptr,o,n)                                                 \
 110  ({                                                                     \
 111     __typeof__(*(ptr)) _o_ = (o);                                       \
 112     __typeof__(*(ptr)) _n_ = (n);                                       \
 113     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 114                                    (unsigned long)_n_, sizeof(*(ptr))); \
 115  })
 116
 117extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
 118void free_initmem(void);
 119void free_initrd_mem(unsigned long start, unsigned long end);
 120
 121extern void *set_exception_table_vec(unsigned int vec, void *handler);
 122
 123static inline void *set_exception_table_evt(unsigned int evt, void *handler)
 124{
 125        return set_exception_table_vec(evt >> 5, handler);
 126}
 127
 128/*
 129 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
 130 */
 131#ifdef CONFIG_CPU_SH2A
 132extern unsigned int instruction_size(unsigned int insn);
 133#elif defined(CONFIG_SUPERH32)
 134#define instruction_size(insn)  (2)
 135#else
 136#define instruction_size(insn)  (4)
 137#endif
 138
 139extern unsigned long cached_to_uncached;
 140
 141extern struct dentry *sh_debugfs_root;
 142
 143void per_cpu_trap_init(void);
 144void default_idle(void);
 145void cpu_idle_wait(void);
 146
 147asmlinkage void break_point_trap(void);
 148
 149#ifdef CONFIG_SUPERH32
 150#define BUILD_TRAP_HANDLER(name)                                        \
 151asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
 152                                    unsigned long r6, unsigned long r7, \
 153                                    struct pt_regs __regs)
 154
 155#define TRAP_HANDLER_DECL                               \
 156        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);  \
 157        unsigned int vec = regs->tra;                   \
 158        (void)vec;
 159#else
 160#define BUILD_TRAP_HANDLER(name)        \
 161asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
 162#define TRAP_HANDLER_DECL
 163#endif
 164
 165BUILD_TRAP_HANDLER(address_error);
 166BUILD_TRAP_HANDLER(debug);
 167BUILD_TRAP_HANDLER(bug);
 168BUILD_TRAP_HANDLER(breakpoint);
 169BUILD_TRAP_HANDLER(singlestep);
 170BUILD_TRAP_HANDLER(fpu_error);
 171BUILD_TRAP_HANDLER(fpu_state_restore);
 172BUILD_TRAP_HANDLER(nmi);
 173
 174#ifdef CONFIG_BUG
 175extern void handle_BUG(struct pt_regs *);
 176#endif
 177
 178#define arch_align_stack(x) (x)
 179
 180struct mem_access {
 181        unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt);
 182        unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt);
 183};
 184
 185#ifdef CONFIG_SUPERH32
 186# include "system_32.h"
 187#else
 188# include "system_64.h"
 189#endif
 190
 191#endif
 192