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11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/io.h>
15#include <linux/sh_timer.h>
16#include <linux/serial_sci.h>
17
18static struct resource rtc_resources[] = {
19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
22 .flags = IORESOURCE_IO,
23 },
24 [1] = {
25
26 .start = 20,
27 .flags = IORESOURCE_IRQ,
28 },
29};
30
31static struct platform_device rtc_device = {
32 .name = "sh-rtc",
33 .id = -1,
34 .num_resources = ARRAY_SIZE(rtc_resources),
35 .resource = rtc_resources,
36};
37
38static struct plat_sci_port sci_platform_data[] = {
39 {
40#ifndef CONFIG_SH_RTS7751R2D
41 .mapbase = 0xffe00000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCI,
44 .irqs = { 23, 23, 23, 0 },
45 }, {
46#endif
47 .mapbase = 0xffe80000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIF,
50 .irqs = { 40, 40, 40, 40 },
51 }, {
52 .flags = 0,
53 }
54};
55
56static struct platform_device sci_device = {
57 .name = "sh-sci",
58 .id = -1,
59 .dev = {
60 .platform_data = sci_platform_data,
61 },
62};
63
64static struct sh_timer_config tmu0_platform_data = {
65 .name = "TMU0",
66 .channel_offset = 0x04,
67 .timer_bit = 0,
68 .clk = "peripheral_clk",
69 .clockevent_rating = 200,
70};
71
72static struct resource tmu0_resources[] = {
73 [0] = {
74 .name = "TMU0",
75 .start = 0xffd80008,
76 .end = 0xffd80013,
77 .flags = IORESOURCE_MEM,
78 },
79 [1] = {
80 .start = 16,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct platform_device tmu0_device = {
86 .name = "sh_tmu",
87 .id = 0,
88 .dev = {
89 .platform_data = &tmu0_platform_data,
90 },
91 .resource = tmu0_resources,
92 .num_resources = ARRAY_SIZE(tmu0_resources),
93};
94
95static struct sh_timer_config tmu1_platform_data = {
96 .name = "TMU1",
97 .channel_offset = 0x10,
98 .timer_bit = 1,
99 .clk = "peripheral_clk",
100 .clocksource_rating = 200,
101};
102
103static struct resource tmu1_resources[] = {
104 [0] = {
105 .name = "TMU1",
106 .start = 0xffd80014,
107 .end = 0xffd8001f,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = 17,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device tmu1_device = {
117 .name = "sh_tmu",
118 .id = 1,
119 .dev = {
120 .platform_data = &tmu1_platform_data,
121 },
122 .resource = tmu1_resources,
123 .num_resources = ARRAY_SIZE(tmu1_resources),
124};
125
126static struct sh_timer_config tmu2_platform_data = {
127 .name = "TMU2",
128 .channel_offset = 0x1c,
129 .timer_bit = 2,
130 .clk = "peripheral_clk",
131};
132
133static struct resource tmu2_resources[] = {
134 [0] = {
135 .name = "TMU2",
136 .start = 0xffd80020,
137 .end = 0xffd8002f,
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = 18,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device tmu2_device = {
147 .name = "sh_tmu",
148 .id = 2,
149 .dev = {
150 .platform_data = &tmu2_platform_data,
151 },
152 .resource = tmu2_resources,
153 .num_resources = ARRAY_SIZE(tmu2_resources),
154};
155
156
157#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
158 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
159 defined(CONFIG_CPU_SUBTYPE_SH7751R)
160
161static struct sh_timer_config tmu3_platform_data = {
162 .name = "TMU3",
163 .channel_offset = 0x04,
164 .timer_bit = 0,
165 .clk = "peripheral_clk",
166};
167
168static struct resource tmu3_resources[] = {
169 [0] = {
170 .name = "TMU3",
171 .start = 0xfe100008,
172 .end = 0xfe100013,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = {
176 .start = 72,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device tmu3_device = {
182 .name = "sh_tmu",
183 .id = 3,
184 .dev = {
185 .platform_data = &tmu3_platform_data,
186 },
187 .resource = tmu3_resources,
188 .num_resources = ARRAY_SIZE(tmu3_resources),
189};
190
191static struct sh_timer_config tmu4_platform_data = {
192 .name = "TMU4",
193 .channel_offset = 0x10,
194 .timer_bit = 1,
195 .clk = "peripheral_clk",
196};
197
198static struct resource tmu4_resources[] = {
199 [0] = {
200 .name = "TMU4",
201 .start = 0xfe100014,
202 .end = 0xfe10001f,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = 76,
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211static struct platform_device tmu4_device = {
212 .name = "sh_tmu",
213 .id = 4,
214 .dev = {
215 .platform_data = &tmu4_platform_data,
216 },
217 .resource = tmu4_resources,
218 .num_resources = ARRAY_SIZE(tmu4_resources),
219};
220
221#endif
222
223static struct platform_device *sh7750_devices[] __initdata = {
224 &rtc_device,
225 &sci_device,
226 &tmu0_device,
227 &tmu1_device,
228 &tmu2_device,
229#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
230 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
231 defined(CONFIG_CPU_SUBTYPE_SH7751R)
232 &tmu3_device,
233 &tmu4_device,
234#endif
235};
236
237static int __init sh7750_devices_setup(void)
238{
239 return platform_add_devices(sh7750_devices,
240 ARRAY_SIZE(sh7750_devices));
241}
242arch_initcall(sh7750_devices_setup);
243
244static struct platform_device *sh7750_early_devices[] __initdata = {
245 &tmu0_device,
246 &tmu1_device,
247 &tmu2_device,
248#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
249 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
250 defined(CONFIG_CPU_SUBTYPE_SH7751R)
251 &tmu3_device,
252 &tmu4_device,
253#endif
254};
255
256void __init plat_early_device_setup(void)
257{
258 early_platform_add_devices(sh7750_early_devices,
259 ARRAY_SIZE(sh7750_early_devices));
260}
261
262enum {
263 UNUSED = 0,
264
265
266 IRL0, IRL1, IRL2, IRL3,
267 HUDI, GPIOI, DMAC,
268 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
269 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
270 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
271
272
273 PCIC1,
274};
275
276static struct intc_vect vectors[] __initdata = {
277 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
278 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
279 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
280 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
281 INTC_VECT(RTC, 0x4c0),
282 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
283 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
284 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
285 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
286 INTC_VECT(WDT, 0x560),
287 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
288};
289
290static struct intc_prio_reg prio_registers[] __initdata = {
291 { 0xffd00004, 0, 16, 4, { TMU0, TMU1, TMU2, RTC } },
292 { 0xffd00008, 0, 16, 4, { WDT, REF, SCI1, 0 } },
293 { 0xffd0000c, 0, 16, 4, { GPIOI, DMAC, SCIF, HUDI } },
294 { 0xffd00010, 0, 16, 4, { IRL0, IRL1, IRL2, IRL3 } },
295 { 0xfe080000, 0, 32, 4, { 0, 0, 0, 0,
296 TMU4, TMU3,
297 PCIC1, PCIC0_PCISERR } },
298};
299
300static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
301 NULL, prio_registers, NULL);
302
303
304#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
305 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
306 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
307 defined(CONFIG_CPU_SUBTYPE_SH7091)
308static struct intc_vect vectors_dma4[] __initdata = {
309 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
310 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
311 INTC_VECT(DMAC, 0x6c0),
312};
313
314static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
315 vectors_dma4, NULL,
316 NULL, prio_registers, NULL);
317#endif
318
319
320#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
321static struct intc_vect vectors_dma8[] __initdata = {
322 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
323 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
324 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
325 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
326 INTC_VECT(DMAC, 0x6c0),
327};
328
329static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
330 vectors_dma8, NULL,
331 NULL, prio_registers, NULL);
332#endif
333
334
335#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
336 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
337 defined(CONFIG_CPU_SUBTYPE_SH7751R)
338static struct intc_vect vectors_tmu34[] __initdata = {
339 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
340};
341
342static struct intc_mask_reg mask_registers[] __initdata = {
343 { 0xfe080040, 0xfe080060, 32,
344 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
345 0, 0, 0, 0, 0, 0, TMU4, TMU3,
346 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
347 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
348 PCIC1_PCIDMA3, PCIC0_PCISERR } },
349};
350
351static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
352 vectors_tmu34, NULL,
353 mask_registers, prio_registers, NULL);
354#endif
355
356
357static struct intc_vect vectors_irlm[] __initdata = {
358 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
359 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
360};
361
362static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
363 NULL, prio_registers, NULL);
364
365
366#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
367static struct intc_vect vectors_pci[] __initdata = {
368 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
369 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
370 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
371 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
372};
373
374static struct intc_group groups_pci[] __initdata = {
375 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
376 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
377};
378
379static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
380 mask_registers, prio_registers, NULL);
381#endif
382
383#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
384 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
385 defined(CONFIG_CPU_SUBTYPE_SH7091)
386void __init plat_irq_setup(void)
387{
388
389
390
391
392 register_intc_controller(&intc_desc);
393 register_intc_controller(&intc_desc_dma4);
394}
395#endif
396
397#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
398void __init plat_irq_setup(void)
399{
400 register_intc_controller(&intc_desc);
401 register_intc_controller(&intc_desc_dma8);
402 register_intc_controller(&intc_desc_tmu34);
403}
404#endif
405
406#if defined(CONFIG_CPU_SUBTYPE_SH7751)
407void __init plat_irq_setup(void)
408{
409 register_intc_controller(&intc_desc);
410 register_intc_controller(&intc_desc_dma4);
411 register_intc_controller(&intc_desc_tmu34);
412 register_intc_controller(&intc_desc_pci);
413}
414#endif
415
416#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
417void __init plat_irq_setup(void)
418{
419 register_intc_controller(&intc_desc);
420 register_intc_controller(&intc_desc_dma8);
421 register_intc_controller(&intc_desc_tmu34);
422 register_intc_controller(&intc_desc_pci);
423}
424#endif
425
426#define INTC_ICR 0xffd00000UL
427#define INTC_ICR_IRLM (1<<7)
428
429void __init plat_irq_setup_pins(int mode)
430{
431#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
432 BUG();
433 return;
434#endif
435
436 switch (mode) {
437 case IRQ_MODE_IRQ:
438 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
439 register_intc_controller(&intc_desc_irlm);
440 break;
441 default:
442 BUG();
443 }
444}
445
