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10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/sh_timer.h>
14#include <linux/serial_sci.h>
15#include <linux/io.h>
16
17enum {
18 UNUSED = 0,
19
20
21 IRL0, IRL1, IRL2, IRL3,
22 HUDI, GPIOI, DMAC,
23 IRQ4, IRQ5, IRQ6, IRQ7,
24 HCAN20, HCAN21,
25 SSI0, SSI1,
26 HAC0, HAC1,
27 I2C0, I2C1,
28 USB, LCDC,
29 DMABRG0, DMABRG1, DMABRG2,
30 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
31 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
32 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
33 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
34 HSPI,
35 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
36 MFI, ADC, CMT,
37 TMU0, TMU1, TMU2,
38 WDT, REF,
39
40
41 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
42};
43
44static struct intc_vect vectors[] __initdata = {
45 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
46 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
47 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
48 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
49 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
50 INTC_VECT(DMAC, 0x6c0),
51 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
52 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
53 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
54 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
55 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
56 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
57 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
58 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
59 INTC_VECT(DMABRG2, 0xac0),
60 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
61 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
62 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
63 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
64 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
65 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
66 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
67 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
68 INTC_VECT(HSPI, 0xc80),
69 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
70 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
71 INTC_VECT(MFI, 0xe80),
72 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
73 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
74 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
75 INTC_VECT(WDT, 0x560),
76 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
77};
78
79static struct intc_group groups[] __initdata = {
80 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
81 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
82 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
83 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
84 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
85 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
86};
87
88static struct intc_mask_reg mask_registers[] __initdata = {
89 { 0xfe080040, 0xfe080060, 32,
90 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
91 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
92 0, DMABRG0, DMABRG1, DMABRG2,
93 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
94 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
95 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
96 { 0xfe080044, 0xfe080064, 32,
97 { 0, 0, 0, 0, 0, 0, 0, 0,
98 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
99 HSPI, MMCIF0, MMCIF1, MMCIF2,
100 MMCIF3, 0, 0, 0, 0, 0, 0, 0,
101 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
102};
103
104static struct intc_prio_reg prio_registers[] __initdata = {
105 { 0xffd00004, 0, 16, 4, { TMU0, TMU1, TMU2 } },
106 { 0xffd00008, 0, 16, 4, { WDT, REF, 0, 0 } },
107 { 0xffd0000c, 0, 16, 4, { GPIOI, DMAC, 0, HUDI } },
108 { 0xffd00010, 0, 16, 4, { IRL0, IRL1, IRL2, IRL3 } },
109 { 0xfe080000, 0, 32, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
110 { 0xfe080004, 0, 32, 4, { HCAN20, HCAN21, SSI0, SSI1,
111 HAC0, HAC1, I2C0, I2C1 } },
112 { 0xfe080008, 0, 32, 4, { USB, LCDC, DMABRG, SCIF0,
113 SCIF1, SCIF2, SIM, HSPI } },
114 { 0xfe08000c, 0, 32, 4, { 0, 0, MMCIF, 0,
115 MFI, 0, ADC, CMT } },
116};
117
118static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
119 mask_registers, prio_registers, NULL);
120
121static struct intc_vect vectors_irq[] __initdata = {
122 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
123 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
124};
125
126static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
127 mask_registers, prio_registers, NULL);
128
129static struct plat_sci_port sci_platform_data[] = {
130 {
131 .mapbase = 0xfe600000,
132 .flags = UPF_BOOT_AUTOCONF,
133 .type = PORT_SCIF,
134 .irqs = { 52, 53, 55, 54 },
135 }, {
136 .mapbase = 0xfe610000,
137 .flags = UPF_BOOT_AUTOCONF,
138 .type = PORT_SCIF,
139 .irqs = { 72, 73, 75, 74 },
140 }, {
141 .mapbase = 0xfe620000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .type = PORT_SCIF,
144 .irqs = { 76, 77, 79, 78 },
145 }, {
146 .mapbase = 0xfe480000,
147 .flags = UPF_BOOT_AUTOCONF,
148 .type = PORT_SCI,
149 .irqs = { 80, 81, 82, 0 },
150 }, {
151 .flags = 0,
152 }
153};
154
155static struct platform_device sci_device = {
156 .name = "sh-sci",
157 .id = -1,
158 .dev = {
159 .platform_data = sci_platform_data,
160 },
161};
162
163static struct sh_timer_config tmu0_platform_data = {
164 .name = "TMU0",
165 .channel_offset = 0x04,
166 .timer_bit = 0,
167 .clk = "peripheral_clk",
168 .clockevent_rating = 200,
169};
170
171static struct resource tmu0_resources[] = {
172 [0] = {
173 .name = "TMU0",
174 .start = 0xffd80008,
175 .end = 0xffd80013,
176 .flags = IORESOURCE_MEM,
177 },
178 [1] = {
179 .start = 16,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device tmu0_device = {
185 .name = "sh_tmu",
186 .id = 0,
187 .dev = {
188 .platform_data = &tmu0_platform_data,
189 },
190 .resource = tmu0_resources,
191 .num_resources = ARRAY_SIZE(tmu0_resources),
192};
193
194static struct sh_timer_config tmu1_platform_data = {
195 .name = "TMU1",
196 .channel_offset = 0x10,
197 .timer_bit = 1,
198 .clk = "peripheral_clk",
199 .clocksource_rating = 200,
200};
201
202static struct resource tmu1_resources[] = {
203 [0] = {
204 .name = "TMU1",
205 .start = 0xffd80014,
206 .end = 0xffd8001f,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = 17,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device tmu1_device = {
216 .name = "sh_tmu",
217 .id = 1,
218 .dev = {
219 .platform_data = &tmu1_platform_data,
220 },
221 .resource = tmu1_resources,
222 .num_resources = ARRAY_SIZE(tmu1_resources),
223};
224
225static struct sh_timer_config tmu2_platform_data = {
226 .name = "TMU2",
227 .channel_offset = 0x1c,
228 .timer_bit = 2,
229 .clk = "peripheral_clk",
230};
231
232static struct resource tmu2_resources[] = {
233 [0] = {
234 .name = "TMU2",
235 .start = 0xffd80020,
236 .end = 0xffd8002f,
237 .flags = IORESOURCE_MEM,
238 },
239 [1] = {
240 .start = 18,
241 .flags = IORESOURCE_IRQ,
242 },
243};
244
245static struct platform_device tmu2_device = {
246 .name = "sh_tmu",
247 .id = 2,
248 .dev = {
249 .platform_data = &tmu2_platform_data,
250 },
251 .resource = tmu2_resources,
252 .num_resources = ARRAY_SIZE(tmu2_resources),
253};
254
255
256static struct platform_device *sh7760_devices[] __initdata = {
257 &sci_device,
258 &tmu0_device,
259 &tmu1_device,
260 &tmu2_device,
261};
262
263static int __init sh7760_devices_setup(void)
264{
265 return platform_add_devices(sh7760_devices,
266 ARRAY_SIZE(sh7760_devices));
267}
268arch_initcall(sh7760_devices_setup);
269
270static struct platform_device *sh7760_early_devices[] __initdata = {
271 &tmu0_device,
272 &tmu1_device,
273 &tmu2_device,
274};
275
276void __init plat_early_device_setup(void)
277{
278 early_platform_add_devices(sh7760_early_devices,
279 ARRAY_SIZE(sh7760_early_devices));
280}
281
282#define INTC_ICR 0xffd00000UL
283#define INTC_ICR_IRLM (1 << 7)
284
285void __init plat_irq_setup_pins(int mode)
286{
287 switch (mode) {
288 case IRQ_MODE_IRQ:
289 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
290 register_intc_controller(&intc_desc_irq);
291 break;
292 default:
293 BUG();
294 }
295}
296
297void __init plat_irq_setup(void)
298{
299 register_intc_controller(&intc_desc);
300}
301
