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21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28
29#define FRQCRA 0xa4150000
30#define FRQCRB 0xa4150004
31#define VCLKCR 0xa4150048
32#define FCLKACR 0xa4150008
33#define FCLKBCR 0xa415000c
34#define IRDACLKCR 0xa4150018
35#define PLLCR 0xa4150024
36#define SPUCLKCR 0xa415003c
37#define FLLFRQ 0xa4150050
38#define LSTATS 0xa4150060
39
40
41static struct clk r_clk = {
42 .name = "rclk",
43 .id = -1,
44 .rate = 32768,
45};
46
47
48
49
50
51struct clk extal_clk = {
52 .name = "extal",
53 .id = -1,
54 .rate = 33333333,
55};
56
57
58static unsigned long fll_recalc(struct clk *clk)
59{
60 unsigned long mult = 0;
61 unsigned long div = 1;
62
63 if (__raw_readl(PLLCR) & 0x1000)
64 mult = __raw_readl(FLLFRQ) & 0x3ff;
65
66 if (__raw_readl(FLLFRQ) & 0x4000)
67 div = 2;
68
69 return (clk->parent->rate * mult) / div;
70}
71
72static struct clk_ops fll_clk_ops = {
73 .recalc = fll_recalc,
74};
75
76static struct clk fll_clk = {
77 .name = "fll_clk",
78 .id = -1,
79 .ops = &fll_clk_ops,
80 .parent = &r_clk,
81 .flags = CLK_ENABLE_ON_INIT,
82};
83
84static unsigned long pll_recalc(struct clk *clk)
85{
86 unsigned long mult = 1;
87
88 if (__raw_readl(PLLCR) & 0x4000)
89 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
90
91 return clk->parent->rate * mult;
92}
93
94static struct clk_ops pll_clk_ops = {
95 .recalc = pll_recalc,
96};
97
98static struct clk pll_clk = {
99 .name = "pll_clk",
100 .id = -1,
101 .ops = &pll_clk_ops,
102 .flags = CLK_ENABLE_ON_INIT,
103};
104
105
106static unsigned long div3_recalc(struct clk *clk)
107{
108 return clk->parent->rate / 3;
109}
110
111static struct clk_ops div3_clk_ops = {
112 .recalc = div3_recalc,
113};
114
115static struct clk div3_clk = {
116 .name = "div3_clk",
117 .id = -1,
118 .ops = &div3_clk_ops,
119 .parent = &pll_clk,
120};
121
122struct clk *main_clks[] = {
123 &r_clk,
124 &extal_clk,
125 &fll_clk,
126 &pll_clk,
127 &div3_clk,
128};
129
130static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
131
132static struct clk_div_mult_table div4_table = {
133 .divisors = divisors,
134 .nr_divisors = ARRAY_SIZE(divisors),
135};
136
137enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
138
139#define DIV4(_str, _reg, _bit, _mask, _flags) \
140 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
141
142struct clk div4_clks[DIV4_NR] = {
143 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
144 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
145 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
146 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
147 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
148};
149
150struct clk div6_clks[] = {
151 SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
152 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
153 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
154 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
155 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
156};
157
158#define R_CLK (&r_clk)
159#define P_CLK (&div4_clks[DIV4_P])
160#define B_CLK (&div4_clks[DIV4_B])
161#define I_CLK (&div4_clks[DIV4_I])
162#define SH_CLK (&div4_clks[DIV4_SH])
163
164static struct clk mstp_clks[] = {
165 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
166 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
167 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
168 SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
171 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
173 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
174 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
175 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
176 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
177 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
178 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
179 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
180 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
181 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
182 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
183 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
184 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
185 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
186 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
187 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
188 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
189 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
190
191 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
192 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
193 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0),
194 SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0),
195
196 SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0),
197 SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0),
198 SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0),
199 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
200 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
201 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
202 SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0),
203 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0),
204 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
205 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
206 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
207 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0),
208 SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0),
209 SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0),
210 SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0),
211 SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0),
212 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
213 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
214 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0),
215 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0),
216 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0),
217 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
218 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
219};
220
221int __init arch_clk_init(void)
222{
223 int k, ret = 0;
224
225
226 if (__raw_readl(PLLCR) & 0x1000)
227 pll_clk.parent = &fll_clk;
228 else
229 pll_clk.parent = &extal_clk;
230
231 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
232 ret = clk_register(main_clks[k]);
233
234 if (!ret)
235 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
236
237 if (!ret)
238 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
239
240 if (!ret)
241 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
242
243 return ret;
244}
245
