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12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/serial.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17#include <linux/serial_sci.h>
18
19static struct resource rtc_resources[] = {
20 [0] = {
21 .start = 0xffe80000,
22 .end = 0xffe80000 + 0x58 - 1,
23 .flags = IORESOURCE_IO,
24 },
25 [1] = {
26
27 .start = 20,
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32static struct platform_device rtc_device = {
33 .name = "sh-rtc",
34 .id = -1,
35 .num_resources = ARRAY_SIZE(rtc_resources),
36 .resource = rtc_resources,
37};
38
39static struct plat_sci_port sci_platform_data[] = {
40 {
41 .mapbase = 0xffe00000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 40, 40, 40, 40 },
45 }, {
46 .mapbase = 0xffe08000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .type = PORT_SCIF,
49 .irqs = { 76, 76, 76, 76 },
50 }, {
51 .mapbase = 0xffe10000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .type = PORT_SCIF,
54 .irqs = { 104, 104, 104, 104 },
55 }, {
56 .flags = 0,
57 }
58};
59
60static struct platform_device sci_device = {
61 .name = "sh-sci",
62 .id = -1,
63 .dev = {
64 .platform_data = sci_platform_data,
65 },
66};
67
68static struct resource usb_ohci_resources[] = {
69 [0] = {
70 .start = 0xffec8000,
71 .end = 0xffec80ff,
72 .flags = IORESOURCE_MEM,
73 },
74 [1] = {
75 .start = 83,
76 .end = 83,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static u64 usb_ohci_dma_mask = 0xffffffffUL;
82static struct platform_device usb_ohci_device = {
83 .name = "sh_ohci",
84 .id = -1,
85 .dev = {
86 .dma_mask = &usb_ohci_dma_mask,
87 .coherent_dma_mask = 0xffffffff,
88 },
89 .num_resources = ARRAY_SIZE(usb_ohci_resources),
90 .resource = usb_ohci_resources,
91};
92
93static struct resource usbf_resources[] = {
94 [0] = {
95 .start = 0xffec0000,
96 .end = 0xffec00ff,
97 .flags = IORESOURCE_MEM,
98 },
99 [1] = {
100 .start = 84,
101 .end = 84,
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106static struct platform_device usbf_device = {
107 .name = "sh_udc",
108 .id = -1,
109 .dev = {
110 .dma_mask = NULL,
111 .coherent_dma_mask = 0xffffffff,
112 },
113 .num_resources = ARRAY_SIZE(usbf_resources),
114 .resource = usbf_resources,
115};
116
117static struct sh_timer_config tmu0_platform_data = {
118 .name = "TMU0",
119 .channel_offset = 0x04,
120 .timer_bit = 0,
121 .clk = "peripheral_clk",
122 .clockevent_rating = 200,
123};
124
125static struct resource tmu0_resources[] = {
126 [0] = {
127 .name = "TMU0",
128 .start = 0xffd80008,
129 .end = 0xffd80013,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = 28,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device tmu0_device = {
139 .name = "sh_tmu",
140 .id = 0,
141 .dev = {
142 .platform_data = &tmu0_platform_data,
143 },
144 .resource = tmu0_resources,
145 .num_resources = ARRAY_SIZE(tmu0_resources),
146};
147
148static struct sh_timer_config tmu1_platform_data = {
149 .name = "TMU1",
150 .channel_offset = 0x10,
151 .timer_bit = 1,
152 .clk = "peripheral_clk",
153 .clocksource_rating = 200,
154};
155
156static struct resource tmu1_resources[] = {
157 [0] = {
158 .name = "TMU1",
159 .start = 0xffd80014,
160 .end = 0xffd8001f,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 29,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device tmu1_device = {
170 .name = "sh_tmu",
171 .id = 1,
172 .dev = {
173 .platform_data = &tmu1_platform_data,
174 },
175 .resource = tmu1_resources,
176 .num_resources = ARRAY_SIZE(tmu1_resources),
177};
178
179static struct sh_timer_config tmu2_platform_data = {
180 .name = "TMU2",
181 .channel_offset = 0x1c,
182 .timer_bit = 2,
183 .clk = "peripheral_clk",
184};
185
186static struct resource tmu2_resources[] = {
187 [0] = {
188 .name = "TMU2",
189 .start = 0xffd80020,
190 .end = 0xffd8002f,
191 .flags = IORESOURCE_MEM,
192 },
193 [1] = {
194 .start = 30,
195 .flags = IORESOURCE_IRQ,
196 },
197};
198
199static struct platform_device tmu2_device = {
200 .name = "sh_tmu",
201 .id = 2,
202 .dev = {
203 .platform_data = &tmu2_platform_data,
204 },
205 .resource = tmu2_resources,
206 .num_resources = ARRAY_SIZE(tmu2_resources),
207};
208
209static struct sh_timer_config tmu3_platform_data = {
210 .name = "TMU3",
211 .channel_offset = 0x04,
212 .timer_bit = 0,
213 .clk = "peripheral_clk",
214};
215
216static struct resource tmu3_resources[] = {
217 [0] = {
218 .name = "TMU3",
219 .start = 0xffd88008,
220 .end = 0xffd88013,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = 96,
225 .flags = IORESOURCE_IRQ,
226 },
227};
228
229static struct platform_device tmu3_device = {
230 .name = "sh_tmu",
231 .id = 3,
232 .dev = {
233 .platform_data = &tmu3_platform_data,
234 },
235 .resource = tmu3_resources,
236 .num_resources = ARRAY_SIZE(tmu3_resources),
237};
238
239static struct sh_timer_config tmu4_platform_data = {
240 .name = "TMU4",
241 .channel_offset = 0x10,
242 .timer_bit = 1,
243 .clk = "peripheral_clk",
244};
245
246static struct resource tmu4_resources[] = {
247 [0] = {
248 .name = "TMU4",
249 .start = 0xffd88014,
250 .end = 0xffd8801f,
251 .flags = IORESOURCE_MEM,
252 },
253 [1] = {
254 .start = 97,
255 .flags = IORESOURCE_IRQ,
256 },
257};
258
259static struct platform_device tmu4_device = {
260 .name = "sh_tmu",
261 .id = 4,
262 .dev = {
263 .platform_data = &tmu4_platform_data,
264 },
265 .resource = tmu4_resources,
266 .num_resources = ARRAY_SIZE(tmu4_resources),
267};
268
269static struct sh_timer_config tmu5_platform_data = {
270 .name = "TMU5",
271 .channel_offset = 0x1c,
272 .timer_bit = 2,
273 .clk = "peripheral_clk",
274};
275
276static struct resource tmu5_resources[] = {
277 [0] = {
278 .name = "TMU5",
279 .start = 0xffd88020,
280 .end = 0xffd8802b,
281 .flags = IORESOURCE_MEM,
282 },
283 [1] = {
284 .start = 98,
285 .flags = IORESOURCE_IRQ,
286 },
287};
288
289static struct platform_device tmu5_device = {
290 .name = "sh_tmu",
291 .id = 5,
292 .dev = {
293 .platform_data = &tmu5_platform_data,
294 },
295 .resource = tmu5_resources,
296 .num_resources = ARRAY_SIZE(tmu5_resources),
297};
298
299static struct platform_device *sh7763_devices[] __initdata = {
300 &tmu0_device,
301 &tmu1_device,
302 &tmu2_device,
303 &tmu3_device,
304 &tmu4_device,
305 &tmu5_device,
306 &rtc_device,
307 &sci_device,
308 &usb_ohci_device,
309 &usbf_device,
310};
311
312static int __init sh7763_devices_setup(void)
313{
314 return platform_add_devices(sh7763_devices,
315 ARRAY_SIZE(sh7763_devices));
316}
317arch_initcall(sh7763_devices_setup);
318
319static struct platform_device *sh7763_early_devices[] __initdata = {
320 &tmu0_device,
321 &tmu1_device,
322 &tmu2_device,
323 &tmu3_device,
324 &tmu4_device,
325 &tmu5_device,
326};
327
328void __init plat_early_device_setup(void)
329{
330 early_platform_add_devices(sh7763_early_devices,
331 ARRAY_SIZE(sh7763_early_devices));
332}
333
334enum {
335 UNUSED = 0,
336
337
338
339 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
340 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
341 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
342 IRL_HHLL, IRL_HHLH, IRL_HHHL,
343
344 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
345 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
346 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
347 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
348 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
349 USBH, USBF, TPU, PCC, MMCIF, SIM,
350 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
351 SCIF2, GPIO,
352
353
354
355 TMU012, TMU345,
356};
357
358static struct intc_vect vectors[] __initdata = {
359 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
360 INTC_VECT(RTC, 0x4c0),
361 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
362 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
363 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
364 INTC_VECT(LCDC, 0x620),
365 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
366 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
367 INTC_VECT(DMAC, 0x6c0),
368 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
369 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
370 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
371 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
372 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
373 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
374 INTC_VECT(HAC, 0x980),
375 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
376 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
377 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
378 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
379 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
380 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
381 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
382 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
383 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
384 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
385 INTC_VECT(USBF, 0xca0),
386 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
387 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
388 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
389 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
390 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
391 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
392 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
393 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
394 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
395 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
396 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
397 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
398 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
399};
400
401static struct intc_group groups[] __initdata = {
402 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
403 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
404};
405
406static struct intc_mask_reg mask_registers[] __initdata = {
407 { 0xffd40038, 0xffd4003c, 32,
408 { 0, 0, 0, 0, 0, 0, GPIO, 0,
409 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
410 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
411 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
412 { 0xffd400d0, 0xffd400d4, 32,
413 { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
414 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
415 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
416 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
417};
418
419static struct intc_prio_reg prio_registers[] __initdata = {
420 { 0xffd40000, 0, 32, 8, { TMU0, TMU1,
421 TMU2, TMU2_TICPI } },
422 { 0xffd40004, 0, 32, 8, { TMU3, TMU4, TMU5, RTC } },
423 { 0xffd40008, 0, 32, 8, { SCIF0, SCIF1, WDT } },
424 { 0xffd4000c, 0, 32, 8, { HUDI, DMAC, ADC } },
425 { 0xffd40010, 0, 32, 8, { CMT, HAC,
426 PCISERR, PCIINTA } },
427 { 0xffd40014, 0, 32, 8, { PCIINTB, PCIINTC,
428 PCIINTD, PCIC5 } },
429 { 0xffd40018, 0, 32, 8, { SIOF0, USBF, MMCIF, SSI0 } },
430 { 0xffd4001c, 0, 32, 8, { SCIF2, GPIO } },
431 { 0xffd400a0, 0, 32, 8, { SSI3, SSI2, SSI1, 0 } },
432 { 0xffd400a4, 0, 32, 8, { LCDC, 0, IIC1, IIC0 } },
433 { 0xffd400a8, 0, 32, 8, { TPU, SIM, SIOF2, SIOF1 } },
434 { 0xffd400ac, 0, 32, 8, { PCC } },
435 { 0xffd400b0, 0, 32, 8, { 0, 0, USBH, GETHER } },
436 { 0xffd400b4, 0, 32, 8, { 0, 0, STIF1, STIF0 } },
437};
438
439static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
440 mask_registers, prio_registers, NULL);
441
442
443static struct intc_vect irq_vectors[] __initdata = {
444 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
445 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
446 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
447 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
448};
449
450static struct intc_mask_reg irq_mask_registers[] __initdata = {
451 { 0xffd00044, 0xffd00064, 32,
452 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
453};
454
455static struct intc_prio_reg irq_prio_registers[] __initdata = {
456 { 0xffd00010, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
457 IRQ4, IRQ5, IRQ6, IRQ7 } },
458};
459
460static struct intc_sense_reg irq_sense_registers[] __initdata = {
461 { 0xffd0001c, 32, 2, { IRQ0, IRQ1, IRQ2, IRQ3,
462 IRQ4, IRQ5, IRQ6, IRQ7 } },
463};
464
465static struct intc_mask_reg irq_ack_registers[] __initdata = {
466 { 0xffd00024, 0, 32,
467 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
468};
469
470static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
471 NULL, irq_mask_registers, irq_prio_registers,
472 irq_sense_registers, irq_ack_registers);
473
474
475
476static struct intc_vect irl_vectors[] __initdata = {
477 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
478 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
479 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
480 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
481 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
482 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
483 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
484 INTC_VECT(IRL_HHHL, 0x3c0),
485};
486
487static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
488 { 0xffd40080, 0xffd40084, 32,
489 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
490 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
491 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
492 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
493};
494
495static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
496 { 0xffd40080, 0xffd40084, 32,
497 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
498 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
499 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
500 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
501 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
502};
503
504static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
505 NULL, irl7654_mask_registers, NULL, NULL);
506
507static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
508 NULL, irl3210_mask_registers, NULL, NULL);
509
510#define INTC_ICR0 0xffd00000
511#define INTC_INTMSK0 0xffd00044
512#define INTC_INTMSK1 0xffd00048
513#define INTC_INTMSK2 0xffd40080
514#define INTC_INTMSKCLR1 0xffd00068
515#define INTC_INTMSKCLR2 0xffd40084
516
517void __init plat_irq_setup(void)
518{
519
520 ctrl_outl(0xff000000, INTC_INTMSK0);
521
522
523 ctrl_outl(0xc0000000, INTC_INTMSK1);
524 ctrl_outl(0xfffefffe, INTC_INTMSK2);
525
526 register_intc_controller(&intc_desc);
527}
528
529void __init plat_irq_setup_pins(int mode)
530{
531 switch (mode) {
532 case IRQ_MODE_IRQ:
533
534 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
535 register_intc_controller(&intc_irq_desc);
536 break;
537 case IRQ_MODE_IRL7654:
538
539 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
540 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
541 break;
542 case IRQ_MODE_IRL3210:
543
544 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
545 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
546 break;
547 case IRQ_MODE_IRL7654_MASK:
548
549 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
550 register_intc_controller(&intc_irl7654_desc);
551 break;
552 case IRQ_MODE_IRL3210_MASK:
553
554 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
555 register_intc_controller(&intc_irl3210_desc);
556 break;
557 default:
558 BUG();
559 }
560}
561
