1#ifndef _ASM_SPARC64_TOPOLOGY_H
2#define _ASM_SPARC64_TOPOLOGY_H
3
4#ifdef CONFIG_NUMA
5
6#include <asm/mmzone.h>
7
8static inline int cpu_to_node(int cpu)
9{
10 return numa_cpu_lookup_table[cpu];
11}
12
13#define parent_node(node) (node)
14
15#define cpumask_of_node(node) (&numa_cpumask_lookup_table[node])
16
17struct pci_bus;
18#ifdef CONFIG_PCI
19extern int pcibus_to_node(struct pci_bus *pbus);
20#else
21static inline int pcibus_to_node(struct pci_bus *pbus)
22{
23 return -1;
24}
25#endif
26
27#define cpumask_of_pcibus(bus) \
28 (pcibus_to_node(bus) == -1 ? \
29 cpu_all_mask : \
30 cpumask_of_node(pcibus_to_node(bus)))
31
32#define SD_NODE_INIT (struct sched_domain) { \
33 .min_interval = 8, \
34 .max_interval = 32, \
35 .busy_factor = 32, \
36 .imbalance_pct = 125, \
37 .cache_nice_tries = 2, \
38 .busy_idx = 3, \
39 .idle_idx = 2, \
40 .newidle_idx = 0, \
41 .wake_idx = 0, \
42 .forkexec_idx = 0, \
43 .flags = SD_LOAD_BALANCE \
44 | SD_BALANCE_FORK \
45 | SD_BALANCE_EXEC \
46 | SD_SERIALIZE, \
47 .last_balance = jiffies, \
48 .balance_interval = 1, \
49}
50
51#else
52
53#include <asm-generic/topology.h>
54
55#endif
56
57#ifdef CONFIG_SMP
58#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
59#define topology_core_id(cpu) (cpu_data(cpu).core_id)
60#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
61#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu))
62#define mc_capable() (sparc64_multi_core)
63#define smt_capable() (sparc64_multi_core)
64#endif
65
66#define cpu_coregroup_mask(cpu) (&cpu_core_map[cpu])
67
68#endif
69