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67#include <linux/types.h>
68#include <linux/sched.h>
69#include <linux/mm.h>
70#include <asm/uaccess.h>
71
72#include "sfp-util_32.h"
73#include <math-emu/soft-fp.h>
74#include <math-emu/single.h>
75#include <math-emu/double.h>
76#include <math-emu/quad.h>
77
78#define FLOATFUNC(x) extern int x(void *,void *,void *)
79
80
81
82
83
84#define FSQRTQ 0x02b
85#define FADDQ 0x043
86#define FSUBQ 0x047
87#define FMULQ 0x04b
88#define FDIVQ 0x04f
89#define FDMULQ 0x06e
90#define FQTOS 0x0c7
91#define FQTOD 0x0cb
92#define FITOQ 0x0cc
93#define FSTOQ 0x0cd
94#define FDTOQ 0x0ce
95#define FQTOI 0x0d3
96#define FCMPQ 0x053
97#define FCMPEQ 0x057
98
99#define FSQRTS 0x029
100#define FSQRTD 0x02a
101#define FADDS 0x041
102#define FADDD 0x042
103#define FSUBS 0x045
104#define FSUBD 0x046
105#define FMULS 0x049
106#define FMULD 0x04a
107#define FDIVS 0x04d
108#define FDIVD 0x04e
109#define FSMULD 0x069
110#define FDTOS 0x0c6
111#define FSTOD 0x0c9
112#define FSTOI 0x0d1
113#define FDTOI 0x0d2
114#define FABSS 0x009
115#define FCMPS 0x051
116#define FCMPES 0x055
117#define FCMPD 0x052
118#define FCMPED 0x056
119#define FMOVS 0x001
120#define FNEGS 0x005
121#define FITOS 0x0c4
122#define FITOD 0x0c8
123
124#define FSR_TEM_SHIFT 23UL
125#define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
126#define FSR_AEXC_SHIFT 5UL
127#define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
128#define FSR_CEXC_SHIFT 0UL
129#define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
130
131static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
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140
141
142int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
143{
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161
162 int i;
163 int retcode = 0;
164 unsigned long insn;
165
166#ifdef DEBUG_MATHEMU
167 printk("In do_mathemu()... pc is %08lx\n", regs->pc);
168 printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
169 for (i = 0; i < fpt->thread.fpqdepth; i++)
170 printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
171 (unsigned long)fpt->thread.fpqueue[i].insn_addr);
172#endif
173
174 if (fpt->thread.fpqdepth == 0) {
175#ifdef DEBUG_MATHEMU
176 printk("precise trap at %08lx\n", regs->pc);
177#endif
178 if (!get_user(insn, (u32 __user *) regs->pc)) {
179 retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
180 if (retcode) {
181
182 regs->pc = regs->npc;
183 regs->npc += 4;
184 }
185 }
186 return retcode;
187 }
188
189
190 for (i = 0; i < fpt->thread.fpqdepth; i++) {
191 retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
192 if (!retcode)
193 break;
194 }
195
196 if (retcode)
197 fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
198 else
199 fpt->thread.fsr &= ~0x3000;
200 fpt->thread.fpqdepth = 0;
201
202 return retcode;
203}
204
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211
212
213static inline int record_exception(unsigned long *pfsr, int eflag)
214{
215 unsigned long fsr = *pfsr;
216 int would_trap;
217
218
219 would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
220
221
222 if (would_trap != 0) {
223 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
224 if ((eflag & (eflag - 1)) != 0) {
225 if (eflag & FP_EX_INVALID)
226 eflag = FP_EX_INVALID;
227 else if (eflag & FP_EX_OVERFLOW)
228 eflag = FP_EX_OVERFLOW;
229 else if (eflag & FP_EX_UNDERFLOW)
230 eflag = FP_EX_UNDERFLOW;
231 else if (eflag & FP_EX_DIVZERO)
232 eflag = FP_EX_DIVZERO;
233 else if (eflag & FP_EX_INEXACT)
234 eflag = FP_EX_INEXACT;
235 }
236 }
237
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242
243
244 fsr &= ~(FSR_CEXC_MASK);
245 fsr |= ((long)eflag << FSR_CEXC_SHIFT);
246
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250
251
252
253 if (would_trap == 0)
254 fsr |= ((long)eflag << FSR_AEXC_SHIFT);
255
256
257 if (would_trap != 0)
258 fsr |= (1UL << 14);
259
260 *pfsr = fsr;
261
262 return (would_trap ? 0 : 1);
263}
264
265typedef union {
266 u32 s;
267 u64 d;
268 u64 q[2];
269} *argp;
270
271static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
272{
273
274 int type = 0;
275
276
277
278#define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
279 int freg;
280 argp rs1 = NULL, rs2 = NULL, rd = NULL;
281 FP_DECL_EX;
282 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
283 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
284 FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
285 int IR;
286 long fsr;
287
288#ifdef DEBUG_MATHEMU
289 printk("In do_mathemu(), emulating %08lx\n", insn);
290#endif
291
292 if ((insn & 0xc1f80000) == 0x81a00000) {
293 switch ((insn >> 5) & 0x1ff) {
294 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
295 case FADDQ:
296 case FSUBQ:
297 case FMULQ:
298 case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
299 case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
300 case FQTOS: TYPE(3,1,1,3,1,0,0); break;
301 case FQTOD: TYPE(3,2,1,3,1,0,0); break;
302 case FITOQ: TYPE(3,3,1,1,0,0,0); break;
303 case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
304 case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
305 case FQTOI: TYPE(3,1,0,3,1,0,0); break;
306 case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
307 case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
308 case FADDD:
309 case FSUBD:
310 case FMULD:
311 case FDIVD: TYPE(2,2,1,2,1,2,1); break;
312 case FADDS:
313 case FSUBS:
314 case FMULS:
315 case FDIVS: TYPE(2,1,1,1,1,1,1); break;
316 case FSMULD: TYPE(2,2,1,1,1,1,1); break;
317 case FDTOS: TYPE(2,1,1,2,1,0,0); break;
318 case FSTOD: TYPE(2,2,1,1,1,0,0); break;
319 case FSTOI: TYPE(2,1,0,1,1,0,0); break;
320 case FDTOI: TYPE(2,1,0,2,1,0,0); break;
321 case FITOS: TYPE(2,1,1,1,0,0,0); break;
322 case FITOD: TYPE(2,2,1,1,0,0,0); break;
323 case FMOVS:
324 case FABSS:
325 case FNEGS: TYPE(2,1,0,1,0,0,0); break;
326 }
327 } else if ((insn & 0xc1f80000) == 0x81a80000) {
328 switch ((insn >> 5) & 0x1ff) {
329 case FCMPS: TYPE(3,0,0,1,1,1,1); break;
330 case FCMPES: TYPE(3,0,0,1,1,1,1); break;
331 case FCMPD: TYPE(3,0,0,2,1,2,1); break;
332 case FCMPED: TYPE(3,0,0,2,1,2,1); break;
333 case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
334 case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
335 }
336 }
337
338 if (!type) {
339#ifdef DEBUG_MATHEMU
340 printk("attempt to emulate unrecognised FPop!\n");
341#endif
342 return 0;
343 }
344
345
346 freg = (*pfsr >> 14) & 0xf;
347
348 *pfsr &= ~0x1c000;
349
350 freg = ((insn >> 14) & 0x1f);
351 switch (type & 0x3) {
352 case 3:
353 if (freg & 3) {
354
355 *pfsr |= (6 << 14);
356 return 0;
357 }
358
359 case 2:
360 if (freg & 1) {
361 *pfsr |= (6 << 14);
362 return 0;
363 }
364 }
365 rs1 = (argp)&fregs[freg];
366 switch (type & 0x7) {
367 case 7: FP_UNPACK_QP (QA, rs1); break;
368 case 6: FP_UNPACK_DP (DA, rs1); break;
369 case 5: FP_UNPACK_SP (SA, rs1); break;
370 }
371 freg = (insn & 0x1f);
372 switch ((type >> 3) & 0x3) {
373 case 3:
374 if (freg & 3) {
375
376 *pfsr |= (6 << 14);
377 return 0;
378 }
379
380 case 2:
381 if (freg & 1) {
382 *pfsr |= (6 << 14);
383 return 0;
384 }
385 }
386 rs2 = (argp)&fregs[freg];
387 switch ((type >> 3) & 0x7) {
388 case 7: FP_UNPACK_QP (QB, rs2); break;
389 case 6: FP_UNPACK_DP (DB, rs2); break;
390 case 5: FP_UNPACK_SP (SB, rs2); break;
391 }
392 freg = ((insn >> 25) & 0x1f);
393 switch ((type >> 6) & 0x3) {
394 case 0:
395 if (freg) {
396
397 *pfsr |= (6 << 14);
398 return 0;
399 }
400 break;
401 case 3:
402 if (freg & 3) {
403
404 *pfsr |= (6 << 14);
405 return 0;
406 }
407
408 case 2:
409 if (freg & 1) {
410 *pfsr |= (6 << 14);
411 return 0;
412 }
413
414 case 1:
415 rd = (void *)&fregs[freg];
416 break;
417 }
418#ifdef DEBUG_MATHEMU
419 printk("executing insn...\n");
420#endif
421
422 switch ((insn >> 5) & 0x1ff) {
423
424 case FADDS: FP_ADD_S (SR, SA, SB); break;
425 case FADDD: FP_ADD_D (DR, DA, DB); break;
426 case FADDQ: FP_ADD_Q (QR, QA, QB); break;
427
428 case FSUBS: FP_SUB_S (SR, SA, SB); break;
429 case FSUBD: FP_SUB_D (DR, DA, DB); break;
430 case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
431
432 case FMULS: FP_MUL_S (SR, SA, SB); break;
433 case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
434 FP_CONV (D, S, 2, 1, DB, SB);
435 case FMULD: FP_MUL_D (DR, DA, DB); break;
436 case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
437 FP_CONV (Q, D, 4, 2, QB, DB);
438 case FMULQ: FP_MUL_Q (QR, QA, QB); break;
439
440 case FDIVS: FP_DIV_S (SR, SA, SB); break;
441 case FDIVD: FP_DIV_D (DR, DA, DB); break;
442 case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
443
444 case FSQRTS: FP_SQRT_S (SR, SB); break;
445 case FSQRTD: FP_SQRT_D (DR, DB); break;
446 case FSQRTQ: FP_SQRT_Q (QR, QB); break;
447
448 case FMOVS: rd->s = rs2->s; break;
449 case FABSS: rd->s = rs2->s & 0x7fffffff; break;
450 case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
451
452 case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
453 case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
454 case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
455
456 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
457 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
458 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
459
460 case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
461 case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
462 case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
463 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
464 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
465 case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
466
467 case FCMPS:
468 case FCMPES:
469 FP_CMP_S(IR, SB, SA, 3);
470 if (IR == 3 &&
471 (((insn >> 5) & 0x1ff) == FCMPES ||
472 FP_ISSIGNAN_S(SA) ||
473 FP_ISSIGNAN_S(SB)))
474 FP_SET_EXCEPTION (FP_EX_INVALID);
475 break;
476 case FCMPD:
477 case FCMPED:
478 FP_CMP_D(IR, DB, DA, 3);
479 if (IR == 3 &&
480 (((insn >> 5) & 0x1ff) == FCMPED ||
481 FP_ISSIGNAN_D(DA) ||
482 FP_ISSIGNAN_D(DB)))
483 FP_SET_EXCEPTION (FP_EX_INVALID);
484 break;
485 case FCMPQ:
486 case FCMPEQ:
487 FP_CMP_Q(IR, QB, QA, 3);
488 if (IR == 3 &&
489 (((insn >> 5) & 0x1ff) == FCMPEQ ||
490 FP_ISSIGNAN_Q(QA) ||
491 FP_ISSIGNAN_Q(QB)))
492 FP_SET_EXCEPTION (FP_EX_INVALID);
493 }
494 if (!FP_INHIBIT_RESULTS) {
495 switch ((type >> 6) & 0x7) {
496 case 0: fsr = *pfsr;
497 if (IR == -1) IR = 2;
498
499 fsr &= ~0xc00; fsr |= (IR << 10); break;
500 *pfsr = fsr;
501 break;
502 case 1: rd->s = IR; break;
503 case 5: FP_PACK_SP (rd, SR); break;
504 case 6: FP_PACK_DP (rd, DR); break;
505 case 7: FP_PACK_QP (rd, QR); break;
506 }
507 }
508 if (_fex == 0)
509 return 1;
510 return record_exception(pfsr, _fex);
511}
512