1#ifndef _ASM_X86_APICDEF_H
2#define _ASM_X86_APICDEF_H
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10
11#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
12#define APIC_DEFAULT_PHYS_BASE 0xfee00000
13
14#define APIC_ID 0x20
15
16#define APIC_LVR 0x30
17#define APIC_LVR_MASK 0xFF00FF
18#define APIC_LVR_DIRECTED_EOI (1 << 24)
19#define GET_APIC_VERSION(x) ((x) & 0xFFu)
20#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
21#ifdef CONFIG_X86_32
22# define APIC_INTEGRATED(x) ((x) & 0xF0u)
23#else
24# define APIC_INTEGRATED(x) (1)
25#endif
26#define APIC_XAPIC(x) ((x) >= 0x14)
27#define APIC_EXT_SPACE(x) ((x) & 0x80000000)
28#define APIC_TASKPRI 0x80
29#define APIC_TPRI_MASK 0xFFu
30#define APIC_ARBPRI 0x90
31#define APIC_ARBPRI_MASK 0xFFu
32#define APIC_PROCPRI 0xA0
33#define APIC_EOI 0xB0
34#define APIC_EIO_ACK 0x0
35#define APIC_RRR 0xC0
36#define APIC_LDR 0xD0
37#define APIC_LDR_MASK (0xFFu << 24)
38#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
39#define SET_APIC_LOGICAL_ID(x) (((x) << 24))
40#define APIC_ALL_CPUS 0xFFu
41#define APIC_DFR 0xE0
42#define APIC_DFR_CLUSTER 0x0FFFFFFFul
43#define APIC_DFR_FLAT 0xFFFFFFFFul
44#define APIC_SPIV 0xF0
45#define APIC_SPIV_DIRECTED_EOI (1 << 12)
46#define APIC_SPIV_FOCUS_DISABLED (1 << 9)
47#define APIC_SPIV_APIC_ENABLED (1 << 8)
48#define APIC_ISR 0x100
49#define APIC_ISR_NR 0x8
50#define APIC_TMR 0x180
51#define APIC_IRR 0x200
52#define APIC_ESR 0x280
53#define APIC_ESR_SEND_CS 0x00001
54#define APIC_ESR_RECV_CS 0x00002
55#define APIC_ESR_SEND_ACC 0x00004
56#define APIC_ESR_RECV_ACC 0x00008
57#define APIC_ESR_SENDILL 0x00020
58#define APIC_ESR_RECVILL 0x00040
59#define APIC_ESR_ILLREGA 0x00080
60#define APIC_LVTCMCI 0x2f0
61#define APIC_ICR 0x300
62#define APIC_DEST_SELF 0x40000
63#define APIC_DEST_ALLINC 0x80000
64#define APIC_DEST_ALLBUT 0xC0000
65#define APIC_ICR_RR_MASK 0x30000
66#define APIC_ICR_RR_INVALID 0x00000
67#define APIC_ICR_RR_INPROG 0x10000
68#define APIC_ICR_RR_VALID 0x20000
69#define APIC_INT_LEVELTRIG 0x08000
70#define APIC_INT_ASSERT 0x04000
71#define APIC_ICR_BUSY 0x01000
72#define APIC_DEST_LOGICAL 0x00800
73#define APIC_DEST_PHYSICAL 0x00000
74#define APIC_DM_FIXED 0x00000
75#define APIC_DM_LOWEST 0x00100
76#define APIC_DM_SMI 0x00200
77#define APIC_DM_REMRD 0x00300
78#define APIC_DM_NMI 0x00400
79#define APIC_DM_INIT 0x00500
80#define APIC_DM_STARTUP 0x00600
81#define APIC_DM_EXTINT 0x00700
82#define APIC_VECTOR_MASK 0x000FF
83#define APIC_ICR2 0x310
84#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
85#define SET_APIC_DEST_FIELD(x) ((x) << 24)
86#define APIC_LVTT 0x320
87#define APIC_LVTTHMR 0x330
88#define APIC_LVTPC 0x340
89#define APIC_LVT0 0x350
90#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
91#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
92#define SET_APIC_TIMER_BASE(x) (((x) << 18))
93#define APIC_TIMER_BASE_CLKIN 0x0
94#define APIC_TIMER_BASE_TMBASE 0x1
95#define APIC_TIMER_BASE_DIV 0x2
96#define APIC_LVT_TIMER_PERIODIC (1 << 17)
97#define APIC_LVT_MASKED (1 << 16)
98#define APIC_LVT_LEVEL_TRIGGER (1 << 15)
99#define APIC_LVT_REMOTE_IRR (1 << 14)
100#define APIC_INPUT_POLARITY (1 << 13)
101#define APIC_SEND_PENDING (1 << 12)
102#define APIC_MODE_MASK 0x700
103#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
104#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
105#define APIC_MODE_FIXED 0x0
106#define APIC_MODE_NMI 0x4
107#define APIC_MODE_EXTINT 0x7
108#define APIC_LVT1 0x360
109#define APIC_LVTERR 0x370
110#define APIC_TMICT 0x380
111#define APIC_TMCCT 0x390
112#define APIC_TDCR 0x3E0
113#define APIC_SELF_IPI 0x3F0
114#define APIC_TDR_DIV_TMBASE (1 << 2)
115#define APIC_TDR_DIV_1 0xB
116#define APIC_TDR_DIV_2 0x0
117#define APIC_TDR_DIV_4 0x1
118#define APIC_TDR_DIV_8 0x2
119#define APIC_TDR_DIV_16 0x3
120#define APIC_TDR_DIV_32 0x8
121#define APIC_TDR_DIV_64 0x9
122#define APIC_TDR_DIV_128 0xA
123#define APIC_EFEAT 0x400
124#define APIC_ECTRL 0x410
125#define APIC_EILVTn(n) (0x500 + 0x10 * n)
126#define APIC_EILVT_NR_AMD_K8 1
127#define APIC_EILVT_NR_AMD_10H 4
128#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
129#define APIC_EILVT_MSG_FIX 0x0
130#define APIC_EILVT_MSG_SMI 0x2
131#define APIC_EILVT_MSG_NMI 0x4
132#define APIC_EILVT_MSG_EXT 0x7
133#define APIC_EILVT_MASKED (1 << 16)
134
135#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
136#define APIC_BASE_MSR 0x800
137#define X2APIC_ENABLE (1UL << 10)
138
139#ifdef CONFIG_X86_32
140# define MAX_IO_APICS 64
141#else
142# define MAX_IO_APICS 128
143# define MAX_LOCAL_APIC 32768
144#endif
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149
150#define XAPIC_DEST_CPUS_SHIFT 4
151#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
152#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
153#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
154#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
155#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
156#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
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162
163
164#define u32 unsigned int
165
166struct local_apic {
167
168 struct { u32 __reserved[4]; } __reserved_01;
169
170 struct { u32 __reserved[4]; } __reserved_02;
171
172 struct {
173 u32 __reserved_1 : 24,
174 phys_apic_id : 4,
175 __reserved_2 : 4;
176 u32 __reserved[3];
177 } id;
178
179 const
180 struct {
181 u32 version : 8,
182 __reserved_1 : 8,
183 max_lvt : 8,
184 __reserved_2 : 8;
185 u32 __reserved[3];
186 } version;
187
188 struct { u32 __reserved[4]; } __reserved_03;
189
190 struct { u32 __reserved[4]; } __reserved_04;
191
192 struct { u32 __reserved[4]; } __reserved_05;
193
194 struct { u32 __reserved[4]; } __reserved_06;
195
196 struct {
197 u32 priority : 8,
198 __reserved_1 : 24;
199 u32 __reserved_2[3];
200 } tpr;
201
202 const
203 struct {
204 u32 priority : 8,
205 __reserved_1 : 24;
206 u32 __reserved_2[3];
207 } apr;
208
209 const
210 struct {
211 u32 priority : 8,
212 __reserved_1 : 24;
213 u32 __reserved_2[3];
214 } ppr;
215
216 struct {
217 u32 eoi;
218 u32 __reserved[3];
219 } eoi;
220
221 struct { u32 __reserved[4]; } __reserved_07;
222
223 struct {
224 u32 __reserved_1 : 24,
225 logical_dest : 8;
226 u32 __reserved_2[3];
227 } ldr;
228
229 struct {
230 u32 __reserved_1 : 28,
231 model : 4;
232 u32 __reserved_2[3];
233 } dfr;
234
235 struct {
236 u32 spurious_vector : 8,
237 apic_enabled : 1,
238 focus_cpu : 1,
239 __reserved_2 : 22;
240 u32 __reserved_3[3];
241 } svr;
242
243 struct {
244 u32 bitfield;
245 u32 __reserved[3];
246 } isr [8];
247
248 struct {
249 u32 bitfield;
250 u32 __reserved[3];
251 } tmr [8];
252
253 struct {
254 u32 bitfield;
255 u32 __reserved[3];
256 } irr [8];
257
258 union {
259 struct {
260 u32 send_cs_error : 1,
261 receive_cs_error : 1,
262 send_accept_error : 1,
263 receive_accept_error : 1,
264 __reserved_1 : 1,
265 send_illegal_vector : 1,
266 receive_illegal_vector : 1,
267 illegal_register_address : 1,
268 __reserved_2 : 24;
269 u32 __reserved_3[3];
270 } error_bits;
271 struct {
272 u32 errors;
273 u32 __reserved_3[3];
274 } all_errors;
275 } esr;
276
277 struct { u32 __reserved[4]; } __reserved_08;
278
279 struct { u32 __reserved[4]; } __reserved_09;
280
281 struct { u32 __reserved[4]; } __reserved_10;
282
283 struct { u32 __reserved[4]; } __reserved_11;
284
285 struct { u32 __reserved[4]; } __reserved_12;
286
287 struct { u32 __reserved[4]; } __reserved_13;
288
289 struct { u32 __reserved[4]; } __reserved_14;
290
291 struct {
292 u32 vector : 8,
293 delivery_mode : 3,
294 destination_mode : 1,
295 delivery_status : 1,
296 __reserved_1 : 1,
297 level : 1,
298 trigger : 1,
299 __reserved_2 : 2,
300 shorthand : 2,
301 __reserved_3 : 12;
302 u32 __reserved_4[3];
303 } icr1;
304
305 struct {
306 union {
307 u32 __reserved_1 : 24,
308 phys_dest : 4,
309 __reserved_2 : 4;
310 u32 __reserved_3 : 24,
311 logical_dest : 8;
312 } dest;
313 u32 __reserved_4[3];
314 } icr2;
315
316 struct {
317 u32 vector : 8,
318 __reserved_1 : 4,
319 delivery_status : 1,
320 __reserved_2 : 3,
321 mask : 1,
322 timer_mode : 1,
323 __reserved_3 : 14;
324 u32 __reserved_4[3];
325 } lvt_timer;
326
327 struct {
328 u32 vector : 8,
329 delivery_mode : 3,
330 __reserved_1 : 1,
331 delivery_status : 1,
332 __reserved_2 : 3,
333 mask : 1,
334 __reserved_3 : 15;
335 u32 __reserved_4[3];
336 } lvt_thermal;
337
338 struct {
339 u32 vector : 8,
340 delivery_mode : 3,
341 __reserved_1 : 1,
342 delivery_status : 1,
343 __reserved_2 : 3,
344 mask : 1,
345 __reserved_3 : 15;
346 u32 __reserved_4[3];
347 } lvt_pc;
348
349 struct {
350 u32 vector : 8,
351 delivery_mode : 3,
352 __reserved_1 : 1,
353 delivery_status : 1,
354 polarity : 1,
355 remote_irr : 1,
356 trigger : 1,
357 mask : 1,
358 __reserved_2 : 15;
359 u32 __reserved_3[3];
360 } lvt_lint0;
361
362 struct {
363 u32 vector : 8,
364 delivery_mode : 3,
365 __reserved_1 : 1,
366 delivery_status : 1,
367 polarity : 1,
368 remote_irr : 1,
369 trigger : 1,
370 mask : 1,
371 __reserved_2 : 15;
372 u32 __reserved_3[3];
373 } lvt_lint1;
374
375 struct {
376 u32 vector : 8,
377 __reserved_1 : 4,
378 delivery_status : 1,
379 __reserved_2 : 3,
380 mask : 1,
381 __reserved_3 : 15;
382 u32 __reserved_4[3];
383 } lvt_error;
384
385 struct {
386 u32 initial_count;
387 u32 __reserved_2[3];
388 } timer_icr;
389
390 const
391 struct {
392 u32 curr_count;
393 u32 __reserved_2[3];
394 } timer_ccr;
395
396 struct { u32 __reserved[4]; } __reserved_16;
397
398 struct { u32 __reserved[4]; } __reserved_17;
399
400 struct { u32 __reserved[4]; } __reserved_18;
401
402 struct { u32 __reserved[4]; } __reserved_19;
403
404 struct {
405 u32 divisor : 4,
406 __reserved_1 : 28;
407 u32 __reserved_2[3];
408 } timer_dcr;
409
410 struct { u32 __reserved[4]; } __reserved_20;
411
412} __attribute__ ((packed));
413
414#undef u32
415
416#ifdef CONFIG_X86_32
417 #define BAD_APICID 0xFFu
418#else
419 #define BAD_APICID 0xFFFFu
420#endif
421#endif
422
