LXR linux/arch/x86/include/asm/mce.h

   1#ifndef _ASM_X86_MCE_H
   2#define _ASM_X86_MCE_H
   3
   4#include <linux/types.h>
   5#include <asm/ioctls.h>
   6
   7/*
   8 * Machine Check support for x86
   9 */
  10
  11#define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  12#define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  13#define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  14#define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  15#define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  16#define MCG_EXT_CNT_SHIFT       16
  17#define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  18#define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  19
  20#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  21#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  22#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  23
  24#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  25#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  26#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  27#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  28#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  29#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  30#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  31#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  32#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  33
  34/* MISC register defines */
  35#define MCM_ADDR_SEGOFF  0      /* segment offset */
  36#define MCM_ADDR_LINEAR  1      /* linear address */
  37#define MCM_ADDR_PHYS    2      /* physical address */
  38#define MCM_ADDR_MEM     3      /* memory address */
  39#define MCM_ADDR_GENERIC 7      /* generic */
  40
  41#define MCJ_CTX_MASK            3
  42#define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  43#define MCJ_CTX_RANDOM          0    /* inject context: random */
  44#define MCJ_CTX_PROCESS         1    /* inject context: process */
  45#define MCJ_CTX_IRQ             2    /* inject context: IRQ */
  46#define MCJ_NMI_BROADCAST       4    /* do NMI broadcasting */
  47#define MCJ_EXCEPTION           8    /* raise as exception */
  48
  49/* Fields are zero when not available */
  50struct mce {
  51        __u64 status;
  52        __u64 misc;
  53        __u64 addr;
  54        __u64 mcgstatus;
  55        __u64 ip;
  56        __u64 tsc;      /* cpu time stamp counter */
  57        __u64 time;     /* wall time_t when error was detected */
  58        __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
  59        __u8  inject_flags;     /* software inject flags */
  60        __u16  pad;
  61        __u32 cpuid;    /* CPUID 1 EAX */
  62        __u8  cs;               /* code segment */
  63        __u8  bank;     /* machine check bank */
  64        __u8  cpu;      /* cpu number; obsolete; use extcpu now */
  65        __u8  finished;   /* entry is valid */
  66        __u32 extcpu;   /* linux cpu number that detected the error */
  67        __u32 socketid; /* CPU socket ID */
  68        __u32 apicid;   /* CPU initial apic ID */
  69        __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
  70};
  71
  72/*
  73 * This structure contains all data related to the MCE log.  Also
  74 * carries a signature to make it easier to find from external
  75 * debugging tools.  Each entry is only valid when its finished flag
  76 * is set.
  77 */
  78
  79#define MCE_LOG_LEN 32
  80
  81struct mce_log {
  82        char signature[12]; /* "MACHINECHECK" */
  83        unsigned len;       /* = MCE_LOG_LEN */
  84        unsigned next;
  85        unsigned flags;
  86        unsigned recordlen;     /* length of struct mce */
  87        struct mce entry[MCE_LOG_LEN];
  88};
  89
  90#define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
  91
  92#define MCE_LOG_SIGNATURE       "MACHINECHECK"
  93
  94#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
  95#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
  96#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
  97
  98/* Software defined banks */
  99#define MCE_EXTENDED_BANK       128
 100#define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
 101
 102#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
 103#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
 104#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
 105#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
 106#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
 107#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
 108#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
 109#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
 110
 111#ifdef __KERNEL__
 112
 113#include <linux/percpu.h>
 114#include <linux/init.h>
 115#include <asm/atomic.h>
 116
 117extern int mce_disabled;
 118extern int mce_p5_enabled;
 119
 120#ifdef CONFIG_X86_MCE
 121void mcheck_init(struct cpuinfo_x86 *c);
 122#else
 123static inline void mcheck_init(struct cpuinfo_x86 *c) {}
 124#endif
 125
 126#ifdef CONFIG_X86_ANCIENT_MCE
 127void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 128void winchip_mcheck_init(struct cpuinfo_x86 *c);
 129static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 130#else
 131static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 132static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 133static inline void enable_p5_mce(void) {}
 134#endif
 135
 136extern void (*x86_mce_decode_callback)(struct mce *m);
 137
 138void mce_setup(struct mce *m);
 139void mce_log(struct mce *m);
 140DECLARE_PER_CPU(struct sys_device, mce_dev);
 141
 142/*
 143 * Maximum banks number.
 144 * This is the limit of the current register layout on
 145 * Intel CPUs.
 146 */
 147#define MAX_NR_BANKS 32
 148
 149#ifdef CONFIG_X86_MCE_INTEL
 150extern int mce_cmci_disabled;
 151extern int mce_ignore_ce;
 152void mce_intel_feature_init(struct cpuinfo_x86 *c);
 153void cmci_clear(void);
 154void cmci_reenable(void);
 155void cmci_rediscover(int dying);
 156void cmci_recheck(void);
 157#else
 158static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 159static inline void cmci_clear(void) {}
 160static inline void cmci_reenable(void) {}
 161static inline void cmci_rediscover(int dying) {}
 162static inline void cmci_recheck(void) {}
 163#endif
 164
 165#ifdef CONFIG_X86_MCE_AMD
 166void mce_amd_feature_init(struct cpuinfo_x86 *c);
 167#else
 168static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 169#endif
 170
 171int mce_available(struct cpuinfo_x86 *c);
 172
 173DECLARE_PER_CPU(unsigned, mce_exception_count);
 174DECLARE_PER_CPU(unsigned, mce_poll_count);
 175
 176extern atomic_t mce_entry;
 177
 178typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 179DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 180
 181enum mcp_flags {
 182        MCP_TIMESTAMP = (1 << 0),       /* log time stamp */
 183        MCP_UC = (1 << 1),              /* log uncorrected errors */
 184        MCP_DONTLOG = (1 << 2),         /* only clear, don't log */
 185};
 186void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 187
 188int mce_notify_irq(void);
 189void mce_notify_process(void);
 190
 191DECLARE_PER_CPU(struct mce, injectm);
 192extern struct file_operations mce_chrdev_ops;
 193
 194/*
 195 * Exception handler
 196 */
 197
 198/* Call the installed machine check handler for this CPU setup. */
 199extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 200void do_machine_check(struct pt_regs *, long);
 201
 202/*
 203 * Threshold handler
 204 */
 205
 206extern void (*mce_threshold_vector)(void);
 207extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 208
 209/*
 210 * Thermal handler
 211 */
 212
 213void intel_init_thermal(struct cpuinfo_x86 *c);
 214
 215void mce_log_therm_throt_event(__u64 status);
 216
 217#endif /* __KERNEL__ */
 218#endif /* _ASM_X86_MCE_H */
 219