1#ifndef _ASM_X86_MSR_INDEX_H 2#define _ASM_X86_MSR_INDEX_H 3 4/* CPU model specific register (MSR) numbers */ 5 6/* x86-64 specific MSRs */ 7#define MSR_EFER 0xc0000080 /* extended feature register */ 8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 16/* EFER bits: */ 17#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 18#define _EFER_LME 8 /* Long mode enable */ 19#define _EFER_LMA 10 /* Long mode active (read-only) */ 20#define _EFER_NX 11 /* No execute enable */ 21#define _EFER_SVME 12 /* Enable virtualization */ 22#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 23 24#define EFER_SCE (1<<_EFER_SCE) 25#define EFER_LME (1<<_EFER_LME) 26#define EFER_LMA (1<<_EFER_LMA) 27#define EFER_NX (1<<_EFER_NX) 28#define EFER_SVME (1<<_EFER_SVME) 29#define EFER_FFXSR (1<<_EFER_FFXSR) 30 31/* Intel MSRs. Some also available on other CPUs */ 32#define MSR_IA32_PERFCTR0 0x000000c1 33#define MSR_IA32_PERFCTR1 0x000000c2 34#define MSR_FSB_FREQ 0x000000cd 35 36#define MSR_MTRRcap 0x000000fe 37#define MSR_IA32_BBL_CR_CTL 0x00000119 38 39#define MSR_IA32_SYSENTER_CS 0x00000174 40#define MSR_IA32_SYSENTER_ESP 0x00000175 41#define MSR_IA32_SYSENTER_EIP 0x00000176 42 43#define MSR_IA32_MCG_CAP 0x00000179 44#define MSR_IA32_MCG_STATUS 0x0000017a 45#define MSR_IA32_MCG_CTL 0x0000017b 46 47#define MSR_IA32_PEBS_ENABLE 0x000003f1 48#define MSR_IA32_DS_AREA 0x00000600 49#define MSR_IA32_PERF_CAPABILITIES 0x00000345 50 51#define MSR_MTRRfix64K_00000 0x00000250 52#define MSR_MTRRfix16K_80000 0x00000258 53#define MSR_MTRRfix16K_A0000 0x00000259 54#define MSR_MTRRfix4K_C0000 0x00000268 55#define MSR_MTRRfix4K_C8000 0x00000269 56#define MSR_MTRRfix4K_D0000 0x0000026a 57#define MSR_MTRRfix4K_D8000 0x0000026b 58#define MSR_MTRRfix4K_E0000 0x0000026c 59#define MSR_MTRRfix4K_E8000 0x0000026d 60#define MSR_MTRRfix4K_F0000 0x0000026e 61#define MSR_MTRRfix4K_F8000 0x0000026f 62#define MSR_MTRRdefType 0x000002ff 63 64#define MSR_IA32_CR_PAT 0x00000277 65 66#define MSR_IA32_DEBUGCTLMSR 0x000001d9 67#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 68#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 69#define MSR_IA32_LASTINTFROMIP 0x000001dd 70#define MSR_IA32_LASTINTTOIP 0x000001de 71 72/* DEBUGCTLMSR bits (others vary by model): */ 73#define _DEBUGCTLMSR_LBR 0 /* last branch recording */ 74#define _DEBUGCTLMSR_BTF 1 /* single-step on branches */ 75 76#define DEBUGCTLMSR_LBR (1UL << _DEBUGCTLMSR_LBR) 77#define DEBUGCTLMSR_BTF (1UL << _DEBUGCTLMSR_BTF) 78 79#define MSR_IA32_MC0_CTL 0x00000400 80#define MSR_IA32_MC0_STATUS 0x00000401 81#define MSR_IA32_MC0_ADDR 0x00000402 82#define MSR_IA32_MC0_MISC 0x00000403 83 84#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 85#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 86#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 87#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 88 89/* These are consecutive and not in the normal 4er MCE bank block */ 90#define MSR_IA32_MC0_CTL2 0x00000280 91#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 92 93#define CMCI_EN (1ULL << 30) 94#define CMCI_THRESHOLD_MASK 0xffffULL 95 96#define MSR_P6_PERFCTR0 0x000000c1 97#define MSR_P6_PERFCTR1 0x000000c2 98#define MSR_P6_EVNTSEL0 0x00000186 99#define MSR_P6_EVNTSEL1 0x00000187 100 101/* AMD64 MSRs. Not complete. See the architecture manual for a more 102 complete list. */ 103 104#define MSR_AMD64_PATCH_LEVEL 0x0000008b 105#define MSR_AMD64_NB_CFG 0xc001001f 106#define MSR_AMD64_PATCH_LOADER 0xc0010020 107#define MSR_AMD64_IBSFETCHCTL 0xc0011030 108#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 109#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 110#define MSR_AMD64_IBSOPCTL 0xc0011033 111#define MSR_AMD64_IBSOPRIP 0xc0011034 112#define MSR_AMD64_IBSOPDATA 0xc0011035 113#define MSR_AMD64_IBSOPDATA2 0xc0011036 114#define MSR_AMD64_IBSOPDATA3 0xc0011037 115#define MSR_AMD64_IBSDCLINAD 0xc0011038 116#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 117#define MSR_AMD64_IBSCTL 0xc001103a 118 119/* Fam 10h MSRs */ 120#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 121#define FAM10H_MMIO_CONF_ENABLE (1<<0) 122#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 123#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 124#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 125#define FAM10H_MMIO_CONF_BASE_SHIFT 20 126 127/* K8 MSRs */ 128#define MSR_K8_TOP_MEM1 0xc001001a 129#define MSR_K8_TOP_MEM2 0xc001001d 130#define MSR_K8_SYSCFG 0xc0010010 131#define MSR_K8_INT_PENDING_MSG 0xc0010055 132/* C1E active bits in int pending message */ 133#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 134#define MSR_K8_TSEG_ADDR 0xc0010112 135#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 136#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 137#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 138 139/* K7 MSRs */ 140#define MSR_K7_EVNTSEL0 0xc0010000 141#define MSR_K7_PERFCTR0 0xc0010004 142#define MSR_K7_EVNTSEL1 0xc0010001 143#define MSR_K7_PERFCTR1 0xc0010005 144#define MSR_K7_EVNTSEL2 0xc0010002 145#define MSR_K7_PERFCTR2 0xc0010006 146#define MSR_K7_EVNTSEL3 0xc0010003 147#define MSR_K7_PERFCTR3 0xc0010007 148#define MSR_K7_CLK_CTL 0xc001001b 149#define MSR_K7_HWCR 0xc0010015 150#define MSR_K7_FID_VID_CTL 0xc0010041 151#define MSR_K7_FID_VID_STATUS 0xc0010042 152 153/* K6 MSRs */ 154#define MSR_K6_EFER 0xc0000080 155#define MSR_K6_STAR 0xc0000081 156#define MSR_K6_WHCR 0xc0000082 157#define MSR_K6_UWCCR 0xc0000085 158#define MSR_K6_EPMR 0xc0000086 159#define MSR_K6_PSOR 0xc0000087 160#define MSR_K6_PFIR 0xc0000088 161 162/* Centaur-Hauls/IDT defined MSRs. */ 163#define MSR_IDT_FCR1 0x00000107 164#define MSR_IDT_FCR2 0x00000108 165#define MSR_IDT_FCR3 0x00000109 166#define MSR_IDT_FCR4 0x0000010a 167 168#define MSR_IDT_MCR0 0x00000110 169#define MSR_IDT_MCR1 0x00000111 170#define MSR_IDT_MCR2 0x00000112 171#define MSR_IDT_MCR3 0x00000113 172#define MSR_IDT_MCR4 0x00000114 173#define MSR_IDT_MCR5 0x00000115 174#define MSR_IDT_MCR6 0x00000116 175#define MSR_IDT_MCR7 0x00000117 176#define MSR_IDT_MCR_CTRL 0x00000120 177 178/* VIA Cyrix defined MSRs*/ 179#define MSR_VIA_FCR 0x00001107 180#define MSR_VIA_LONGHAUL 0x0000110a 181#define MSR_VIA_RNG 0x0000110b 182#define MSR_VIA_BCR2 0x00001147 183 184/* Transmeta defined MSRs */ 185#define MSR_TMTA_LONGRUN_CTRL 0x80868010 186#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 187#define MSR_TMTA_LRTI_READOUT 0x80868018 188#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 189 190/* Intel defined MSRs. */ 191#define MSR_IA32_P5_MC_ADDR 0x00000000 192#define MSR_IA32_P5_MC_TYPE 0x00000001 193#define MSR_IA32_TSC 0x00000010 194#define MSR_IA32_PLATFORM_ID 0x00000017 195#define MSR_IA32_EBL_CR_POWERON 0x0000002a 196#define MSR_IA32_FEATURE_CONTROL 0x0000003a 197 198#define FEATURE_CONTROL_LOCKED (1<<0) 199#define FEATURE_CONTROL_VMXON_ENABLED (1<<2) 200 201#define MSR_IA32_APICBASE 0x0000001b 202#define MSR_IA32_APICBASE_BSP (1<<8) 203#define MSR_IA32_APICBASE_ENABLE (1<<11) 204#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 205 206#define MSR_IA32_UCODE_WRITE 0x00000079 207#define MSR_IA32_UCODE_REV 0x0000008b 208 209#define MSR_IA32_PERF_STATUS 0x00000198 210#define MSR_IA32_PERF_CTL 0x00000199 211 212#define MSR_IA32_MPERF 0x000000e7 213#define MSR_IA32_APERF 0x000000e8 214 215#define MSR_IA32_THERM_CONTROL 0x0000019a 216#define MSR_IA32_THERM_INTERRUPT 0x0000019b 217 218#define THERM_INT_LOW_ENABLE (1 << 0) 219#define THERM_INT_HIGH_ENABLE (1 << 1) 220 221#define MSR_IA32_THERM_STATUS 0x0000019c 222 223#define THERM_STATUS_PROCHOT (1 << 0) 224 225#define MSR_THERM2_CTL 0x0000019d 226 227#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 228 229#define MSR_IA32_MISC_ENABLE 0x000001a0 230 231/* MISC_ENABLE bits: architectural */ 232#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 233#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 234#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 235#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 236#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 237#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 238#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 239#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 240#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 241#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 242 243/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 244#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 245#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 246#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 247#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 248#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 249#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 250#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 251#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 252#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 253#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 254#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 255#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 256#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 257#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 258#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 259 260/* P4/Xeon+ specific */ 261#define MSR_IA32_MCG_EAX 0x00000180 262#define MSR_IA32_MCG_EBX 0x00000181 263#define MSR_IA32_MCG_ECX 0x00000182 264#define MSR_IA32_MCG_EDX 0x00000183 265#define MSR_IA32_MCG_ESI 0x00000184 266#define MSR_IA32_MCG_EDI 0x00000185 267#define MSR_IA32_MCG_EBP 0x00000186 268#define MSR_IA32_MCG_ESP 0x00000187 269#define MSR_IA32_MCG_EFLAGS 0x00000188 270#define MSR_IA32_MCG_EIP 0x00000189 271#define MSR_IA32_MCG_RESERVED 0x0000018a 272 273/* Pentium IV performance counter MSRs */ 274#define MSR_P4_BPU_PERFCTR0 0x00000300 275#define MSR_P4_BPU_PERFCTR1 0x00000301 276#define MSR_P4_BPU_PERFCTR2 0x00000302 277#define MSR_P4_BPU_PERFCTR3 0x00000303 278#define MSR_P4_MS_PERFCTR0 0x00000304 279#define MSR_P4_MS_PERFCTR1 0x00000305 280#define MSR_P4_MS_PERFCTR2 0x00000306 281#define MSR_P4_MS_PERFCTR3 0x00000307 282#define MSR_P4_FLAME_PERFCTR0 0x00000308 283#define MSR_P4_FLAME_PERFCTR1 0x00000309 284#define MSR_P4_FLAME_PERFCTR2 0x0000030a 285#define MSR_P4_FLAME_PERFCTR3 0x0000030b 286#define MSR_P4_IQ_PERFCTR0 0x0000030c 287#define MSR_P4_IQ_PERFCTR1 0x0000030d 288#define MSR_P4_IQ_PERFCTR2 0x0000030e 289#define MSR_P4_IQ_PERFCTR3 0x0000030f 290#define MSR_P4_IQ_PERFCTR4 0x00000310 291#define MSR_P4_IQ_PERFCTR5 0x00000311 292#define MSR_P4_BPU_CCCR0 0x00000360 293#define MSR_P4_BPU_CCCR1 0x00000361 294#define MSR_P4_BPU_CCCR2 0x00000362 295#define MSR_P4_BPU_CCCR3 0x00000363 296#define MSR_P4_MS_CCCR0 0x00000364 297#define MSR_P4_MS_CCCR1 0x00000365 298#define MSR_P4_MS_CCCR2 0x00000366 299#define MSR_P4_MS_CCCR3 0x00000367 300#define MSR_P4_FLAME_CCCR0 0x00000368 301#define MSR_P4_FLAME_CCCR1 0x00000369 302#define MSR_P4_FLAME_CCCR2 0x0000036a 303#define MSR_P4_FLAME_CCCR3 0x0000036b 304#define MSR_P4_IQ_CCCR0 0x0000036c 305#define MSR_P4_IQ_CCCR1 0x0000036d 306#define MSR_P4_IQ_CCCR2 0x0000036e 307#define MSR_P4_IQ_CCCR3 0x0000036f 308#define MSR_P4_IQ_CCCR4 0x00000370 309#define MSR_P4_IQ_CCCR5 0x00000371 310#define MSR_P4_ALF_ESCR0 0x000003ca 311#define MSR_P4_ALF_ESCR1 0x000003cb 312#define MSR_P4_BPU_ESCR0 0x000003b2 313#define MSR_P4_BPU_ESCR1 0x000003b3 314#define MSR_P4_BSU_ESCR0 0x000003a0 315#define MSR_P4_BSU_ESCR1 0x000003a1 316#define MSR_P4_CRU_ESCR0 0x000003b8 317#define MSR_P4_CRU_ESCR1 0x000003b9 318#define MSR_P4_CRU_ESCR2 0x000003cc 319#define MSR_P4_CRU_ESCR3 0x000003cd 320#define MSR_P4_CRU_ESCR4 0x000003e0 321#define MSR_P4_CRU_ESCR5 0x000003e1 322#define MSR_P4_DAC_ESCR0 0x000003a8 323#define MSR_P4_DAC_ESCR1 0x000003a9 324#define MSR_P4_FIRM_ESCR0 0x000003a4 325#define MSR_P4_FIRM_ESCR1 0x000003a5 326#define MSR_P4_FLAME_ESCR0 0x000003a6 327#define MSR_P4_FLAME_ESCR1 0x000003a7 328#define MSR_P4_FSB_ESCR0 0x000003a2 329#define MSR_P4_FSB_ESCR1 0x000003a3 330#define MSR_P4_IQ_ESCR0 0x000003ba 331#define MSR_P4_IQ_ESCR1 0x000003bb 332#define MSR_P4_IS_ESCR0 0x000003b4 333#define MSR_P4_IS_ESCR1 0x000003b5 334#define MSR_P4_ITLB_ESCR0 0x000003b6 335#define MSR_P4_ITLB_ESCR1 0x000003b7 336#define MSR_P4_IX_ESCR0 0x000003c8 337#define MSR_P4_IX_ESCR1 0x000003c9 338#define MSR_P4_MOB_ESCR0 0x000003aa 339#define MSR_P4_MOB_ESCR1 0x000003ab 340#define MSR_P4_MS_ESCR0 0x000003c0 341#define MSR_P4_MS_ESCR1 0x000003c1 342#define MSR_P4_PMH_ESCR0 0x000003ac 343#define MSR_P4_PMH_ESCR1 0x000003ad 344#define MSR_P4_RAT_ESCR0 0x000003bc 345#define MSR_P4_RAT_ESCR1 0x000003bd 346#define MSR_P4_SAAT_ESCR0 0x000003ae 347#define MSR_P4_SAAT_ESCR1 0x000003af 348#define MSR_P4_SSU_ESCR0 0x000003be 349#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 350 351#define MSR_P4_TBPU_ESCR0 0x000003c2 352#define MSR_P4_TBPU_ESCR1 0x000003c3 353#define MSR_P4_TC_ESCR0 0x000003c4 354#define MSR_P4_TC_ESCR1 0x000003c5 355#define MSR_P4_U2L_ESCR0 0x000003b0 356#define MSR_P4_U2L_ESCR1 0x000003b1 357 358/* Intel Core-based CPU performance counters */ 359#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 360#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 361#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 362#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 363#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 364#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 365#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 366 367/* Geode defined MSRs */ 368#define MSR_GEODE_BUSCONT_CONF0 0x00001900 369 370/* Intel VT MSRs */ 371#define MSR_IA32_VMX_BASIC 0x00000480 372#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 373#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 374#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 375#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 376#define MSR_IA32_VMX_MISC 0x00000485 377#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 378#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 379#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 380#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 381#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 382#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 383#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 384 385/* AMD-V MSRs */ 386 387#define MSR_VM_CR 0xc0010114 388#define MSR_VM_IGNNE 0xc0010115 389#define MSR_VM_HSAVE_PA 0xc0010117 390 391#endif /* _ASM_X86_MSR_INDEX_H */ 392