LXR linux/arch/x86/include/asm/pci

   1/*
   2 *      Low-Level PCI Access for i386 machines.
   3 *
   4 *      (c) 1999 Martin Mares <mj@ucw.cz>
   5 */
   6
   7#undef DEBUG
   8
   9#ifdef DEBUG
  10#define DBG(x...) printk(x)
  11#else
  12#define DBG(x...)
  13#endif
  14
  15#define PCI_PROBE_BIOS          0x0001
  16#define PCI_PROBE_CONF1         0x0002
  17#define PCI_PROBE_CONF2         0x0004
  18#define PCI_PROBE_MMCONF        0x0008
  19#define PCI_PROBE_MASK          0x000f
  20#define PCI_PROBE_NOEARLY       0x0010
  21
  22#define PCI_NO_CHECKS           0x0400
  23#define PCI_USE_PIRQ_MASK       0x0800
  24#define PCI_ASSIGN_ROMS         0x1000
  25#define PCI_BIOS_IRQ_SCAN       0x2000
  26#define PCI_ASSIGN_ALL_BUSSES   0x4000
  27#define PCI_CAN_SKIP_ISA_ALIGN  0x8000
  28#define PCI_USE__CRS            0x10000
  29#define PCI_CHECK_ENABLE_AMD_MMCONF     0x20000
  30#define PCI_HAS_IO_ECS          0x40000
  31#define PCI_NOASSIGN_ROMS       0x80000
  32
  33extern unsigned int pci_probe;
  34extern unsigned long pirq_table_addr;
  35
  36enum pci_bf_sort_state {
  37        pci_bf_sort_default,
  38        pci_force_nobf,
  39        pci_force_bf,
  40        pci_dmi_bf,
  41};
  42
  43/* pci-i386.c */
  44
  45extern unsigned int pcibios_max_latency;
  46
  47void pcibios_resource_survey(void);
  48
  49/* pci-pc.c */
  50
  51extern int pcibios_last_bus;
  52extern struct pci_bus *pci_root_bus;
  53extern struct pci_ops pci_root_ops;
  54
  55/* pci-irq.c */
  56
  57struct irq_info {
  58        u8 bus, devfn;                  /* Bus, device and function */
  59        struct {
  60                u8 link;                /* IRQ line ID, chipset dependent,
  61                                           0 = not routed */
  62                u16 bitmap;             /* Available IRQs */
  63        } __attribute__((packed)) irq[4];
  64        u8 slot;                        /* Slot number, 0=onboard */
  65        u8 rfu;
  66} __attribute__((packed));
  67
  68struct irq_routing_table {
  69        u32 signature;                  /* PIRQ_SIGNATURE should be here */
  70        u16 version;                    /* PIRQ_VERSION */
  71        u16 size;                       /* Table size in bytes */
  72        u8 rtr_bus, rtr_devfn;          /* Where the interrupt router lies */
  73        u16 exclusive_irqs;             /* IRQs devoted exclusively to
  74                                           PCI usage */
  75        u16 rtr_vendor, rtr_device;     /* Vendor and device ID of
  76                                           interrupt router */
  77        u32 miniport_data;              /* Crap */
  78        u8 rfu[11];
  79        u8 checksum;                    /* Modulo 256 checksum must give 0 */
  80        struct irq_info slots[0];
  81} __attribute__((packed));
  82
  83extern unsigned int pcibios_irq_mask;
  84
  85extern int pcibios_scanned;
  86extern spinlock_t pci_config_lock;
  87
  88extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  89extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  90
  91struct pci_raw_ops {
  92        int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
  93                                                int reg, int len, u32 *val);
  94        int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
  95                                                int reg, int len, u32 val);
  96};
  97
  98extern struct pci_raw_ops *raw_pci_ops;
  99extern struct pci_raw_ops *raw_pci_ext_ops;
 100
 101extern struct pci_raw_ops pci_direct_conf1;
 102extern bool port_cf9_safe;
 103
 104/* arch_initcall level */
 105extern int pci_direct_probe(void);
 106extern void pci_direct_init(int type);
 107extern void pci_pcbios_init(void);
 108extern int pci_olpc_init(void);
 109extern void __init dmi_check_pciprobe(void);
 110extern void __init dmi_check_skip_isa_align(void);
 111
 112/* some common used subsys_initcalls */
 113extern int __init pci_acpi_init(void);
 114extern int __init pcibios_irq_init(void);
 115extern int __init pci_visws_init(void);
 116extern int __init pci_numaq_init(void);
 117extern int __init pcibios_init(void);
 118
 119/* pci-mmconfig.c */
 120
 121extern int __init pci_mmcfg_arch_init(void);
 122extern void __init pci_mmcfg_arch_free(void);
 123
 124extern struct acpi_mcfg_allocation *pci_mmcfg_config;
 125extern int pci_mmcfg_config_num;
 126
 127/*
 128 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 129 * on their northbrige except through the * %eax register. As such, you MUST
 130 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 131 * accessor functions.
 132 * In fact just use pci_config_*, nothing else please.
 133 */
 134static inline unsigned char mmio_config_readb(void __iomem *pos)
 135{
 136        u8 val;
 137        asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
 138        return val;
 139}
 140
 141static inline unsigned short mmio_config_readw(void __iomem *pos)
 142{
 143        u16 val;
 144        asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
 145        return val;
 146}
 147
 148static inline unsigned int mmio_config_readl(void __iomem *pos)
 149{
 150        u32 val;
 151        asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
 152        return val;
 153}
 154
 155static inline void mmio_config_writeb(void __iomem *pos, u8 val)
 156{
 157        asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
 158}
 159
 160static inline void mmio_config_writew(void __iomem *pos, u16 val)
 161{
 162        asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
 163}
 164
 165static inline void mmio_config_writel(void __iomem *pos, u32 val)
 166{
 167        asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
 168}
 169