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17#include <linux/perf_event.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/acpi_pmtmr.h>
21#include <linux/clockchips.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24#include <linux/ftrace.h>
25#include <linux/ioport.h>
26#include <linux/module.h>
27#include <linux/sysdev.h>
28#include <linux/delay.h>
29#include <linux/timex.h>
30#include <linux/dmar.h>
31#include <linux/init.h>
32#include <linux/cpu.h>
33#include <linux/dmi.h>
34#include <linux/nmi.h>
35#include <linux/smp.h>
36#include <linux/mm.h>
37
38#include <asm/perf_event.h>
39#include <asm/x86_init.h>
40#include <asm/pgalloc.h>
41#include <asm/atomic.h>
42#include <asm/mpspec.h>
43#include <asm/i8253.h>
44#include <asm/i8259.h>
45#include <asm/proto.h>
46#include <asm/apic.h>
47#include <asm/desc.h>
48#include <asm/hpet.h>
49#include <asm/idle.h>
50#include <asm/mtrr.h>
51#include <asm/smp.h>
52#include <asm/mce.h>
53#include <asm/kvm_para.h>
54
55unsigned int num_processors;
56
57unsigned disabled_cpus __cpuinitdata;
58
59
60unsigned int boot_cpu_physical_apicid = -1U;
61
62
63
64
65
66
67
68
69
70
71unsigned int max_physical_apicid;
72
73
74
75
76physid_mask_t phys_cpu_present_map;
77
78
79
80
81DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
82DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
83EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
84EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
85
86#ifdef CONFIG_X86_32
87
88
89
90
91
92static int force_enable_local_apic;
93
94
95
96static int __init parse_lapic(char *arg)
97{
98 force_enable_local_apic = 1;
99 return 0;
100}
101early_param("lapic", parse_lapic);
102
103static int enabled_via_apicbase;
104
105
106
107
108
109
110
111
112
113static inline void imcr_pic_to_apic(void)
114{
115
116 outb(0x70, 0x22);
117
118 outb(0x01, 0x23);
119}
120
121static inline void imcr_apic_to_pic(void)
122{
123
124 outb(0x70, 0x22);
125
126 outb(0x00, 0x23);
127}
128#endif
129
130#ifdef CONFIG_X86_64
131static int apic_calibrate_pmtmr __initdata;
132static __init int setup_apicpmtimer(char *s)
133{
134 apic_calibrate_pmtmr = 1;
135 notsc_setup(NULL);
136 return 0;
137}
138__setup("apicpmtimer", setup_apicpmtimer);
139#endif
140
141int x2apic_mode;
142#ifdef CONFIG_X86_X2APIC
143
144static int x2apic_preenabled;
145static __init int setup_nox2apic(char *str)
146{
147 if (x2apic_enabled()) {
148 pr_warning("Bios already enabled x2apic, "
149 "can't enforce nox2apic");
150 return 0;
151 }
152
153 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
154 return 0;
155}
156early_param("nox2apic", setup_nox2apic);
157#endif
158
159unsigned long mp_lapic_addr;
160int disable_apic;
161
162static int disable_apic_timer __cpuinitdata;
163
164int local_apic_timer_c2_ok;
165EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
166
167int first_system_vector = 0xfe;
168
169
170
171
172unsigned int apic_verbosity;
173
174int pic_mode;
175
176
177int smp_found_config;
178
179static struct resource lapic_resource = {
180 .name = "Local APIC",
181 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
182};
183
184static unsigned int calibration_result;
185
186static int lapic_next_event(unsigned long delta,
187 struct clock_event_device *evt);
188static void lapic_timer_setup(enum clock_event_mode mode,
189 struct clock_event_device *evt);
190static void lapic_timer_broadcast(const struct cpumask *mask);
191static void apic_pm_activate(void);
192
193
194
195
196static struct clock_event_device lapic_clockevent = {
197 .name = "lapic",
198 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
199 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
200 .shift = 32,
201 .set_mode = lapic_timer_setup,
202 .set_next_event = lapic_next_event,
203 .broadcast = lapic_timer_broadcast,
204 .rating = 100,
205 .irq = -1,
206};
207static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
208
209static unsigned long apic_phys;
210
211
212
213
214static inline int lapic_get_version(void)
215{
216 return GET_APIC_VERSION(apic_read(APIC_LVR));
217}
218
219
220
221
222static inline int lapic_is_integrated(void)
223{
224#ifdef CONFIG_X86_64
225 return 1;
226#else
227 return APIC_INTEGRATED(lapic_get_version());
228#endif
229}
230
231
232
233
234static int modern_apic(void)
235{
236
237 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
238 boot_cpu_data.x86 >= 0xf)
239 return 1;
240 return lapic_get_version() >= 0x14;
241}
242
243
244
245
246
247static void native_apic_write_dummy(u32 reg, u32 v)
248{
249 WARN_ON_ONCE((cpu_has_apic || !disable_apic));
250}
251
252static u32 native_apic_read_dummy(u32 reg)
253{
254 WARN_ON_ONCE((cpu_has_apic && !disable_apic));
255 return 0;
256}
257
258
259
260
261
262void apic_disable(void)
263{
264 apic->read = native_apic_read_dummy;
265 apic->write = native_apic_write_dummy;
266}
267
268void native_apic_wait_icr_idle(void)
269{
270 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
271 cpu_relax();
272}
273
274u32 native_safe_apic_wait_icr_idle(void)
275{
276 u32 send_status;
277 int timeout;
278
279 timeout = 0;
280 do {
281 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
282 if (!send_status)
283 break;
284 udelay(100);
285 } while (timeout++ < 1000);
286
287 return send_status;
288}
289
290void native_apic_icr_write(u32 low, u32 id)
291{
292 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
293 apic_write(APIC_ICR, low);
294}
295
296u64 native_apic_icr_read(void)
297{
298 u32 icr1, icr2;
299
300 icr2 = apic_read(APIC_ICR2);
301 icr1 = apic_read(APIC_ICR);
302
303 return icr1 | ((u64)icr2 << 32);
304}
305
306
307
308
309void __cpuinit enable_NMI_through_LVT0(void)
310{
311 unsigned int v;
312
313
314 v = APIC_DM_NMI;
315
316
317 if (!lapic_is_integrated())
318 v |= APIC_LVT_LEVEL_TRIGGER;
319
320 apic_write(APIC_LVT0, v);
321}
322
323#ifdef CONFIG_X86_32
324
325
326
327int get_physical_broadcast(void)
328{
329 return modern_apic() ? 0xff : 0xf;
330}
331#endif
332
333
334
335
336int lapic_get_maxlvt(void)
337{
338 unsigned int v;
339
340 v = apic_read(APIC_LVR);
341
342
343
344
345 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
346}
347
348
349
350
351
352
353#define APIC_DIVISOR 16
354
355
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357
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363
364
365static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
366{
367 unsigned int lvtt_value, tmp_value;
368
369 lvtt_value = LOCAL_TIMER_VECTOR;
370 if (!oneshot)
371 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
372 if (!lapic_is_integrated())
373 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
374
375 if (!irqen)
376 lvtt_value |= APIC_LVT_MASKED;
377
378 apic_write(APIC_LVTT, lvtt_value);
379
380
381
382
383 tmp_value = apic_read(APIC_TDCR);
384 apic_write(APIC_TDCR,
385 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
386 APIC_TDR_DIV_16);
387
388 if (!oneshot)
389 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
390}
391
392
393
394
395
396
397
398
399
400
401
402#define APIC_EILVT_LVTOFF_MCE 0
403#define APIC_EILVT_LVTOFF_IBS 1
404
405static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
406{
407 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0);
408 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
409
410 apic_write(reg, v);
411}
412
413u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
414{
415 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
416 return APIC_EILVT_LVTOFF_MCE;
417}
418
419u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
420{
421 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
422 return APIC_EILVT_LVTOFF_IBS;
423}
424EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
425
426
427
428
429static int lapic_next_event(unsigned long delta,
430 struct clock_event_device *evt)
431{
432 apic_write(APIC_TMICT, delta);
433 return 0;
434}
435
436
437
438
439static void lapic_timer_setup(enum clock_event_mode mode,
440 struct clock_event_device *evt)
441{
442 unsigned long flags;
443 unsigned int v;
444
445
446 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
447 return;
448
449 local_irq_save(flags);
450
451 switch (mode) {
452 case CLOCK_EVT_MODE_PERIODIC:
453 case CLOCK_EVT_MODE_ONESHOT:
454 __setup_APIC_LVTT(calibration_result,
455 mode != CLOCK_EVT_MODE_PERIODIC, 1);
456 break;
457 case CLOCK_EVT_MODE_UNUSED:
458 case CLOCK_EVT_MODE_SHUTDOWN:
459 v = apic_read(APIC_LVTT);
460 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
461 apic_write(APIC_LVTT, v);
462 apic_write(APIC_TMICT, 0xffffffff);
463 break;
464 case CLOCK_EVT_MODE_RESUME:
465
466 break;
467 }
468
469 local_irq_restore(flags);
470}
471
472
473
474
475static void lapic_timer_broadcast(const struct cpumask *mask)
476{
477#ifdef CONFIG_SMP
478 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
479#endif
480}
481
482
483
484
485
486static void __cpuinit setup_APIC_timer(void)
487{
488 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
489
490 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) {
491 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
492
493 lapic_clockevent.rating = 150;
494 }
495
496 memcpy(levt, &lapic_clockevent, sizeof(*levt));
497 levt->cpumask = cpumask_of(smp_processor_id());
498
499 clockevents_register_device(levt);
500}
501
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521
522
523#define LAPIC_CAL_LOOPS (HZ/10)
524
525static __initdata int lapic_cal_loops = -1;
526static __initdata long lapic_cal_t1, lapic_cal_t2;
527static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
528static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
529static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
530
531
532
533
534static void __init lapic_cal_handler(struct clock_event_device *dev)
535{
536 unsigned long long tsc = 0;
537 long tapic = apic_read(APIC_TMCCT);
538 unsigned long pm = acpi_pm_read_early();
539
540 if (cpu_has_tsc)
541 rdtscll(tsc);
542
543 switch (lapic_cal_loops++) {
544 case 0:
545 lapic_cal_t1 = tapic;
546 lapic_cal_tsc1 = tsc;
547 lapic_cal_pm1 = pm;
548 lapic_cal_j1 = jiffies;
549 break;
550
551 case LAPIC_CAL_LOOPS:
552 lapic_cal_t2 = tapic;
553 lapic_cal_tsc2 = tsc;
554 if (pm < lapic_cal_pm1)
555 pm += ACPI_PM_OVRRUN;
556 lapic_cal_pm2 = pm;
557 lapic_cal_j2 = jiffies;
558 break;
559 }
560}
561
562static int __init
563calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
564{
565 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
566 const long pm_thresh = pm_100ms / 100;
567 unsigned long mult;
568 u64 res;
569
570#ifndef CONFIG_X86_PM_TIMER
571 return -1;
572#endif
573
574 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
575
576
577 if (!deltapm)
578 return -1;
579
580 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
581
582 if (deltapm > (pm_100ms - pm_thresh) &&
583 deltapm < (pm_100ms + pm_thresh)) {
584 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
585 return 0;
586 }
587
588 res = (((u64)deltapm) * mult) >> 22;
589 do_div(res, 1000000);
590 pr_warning("APIC calibration not consistent "
591 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
592
593
594 res = (((u64)(*delta)) * pm_100ms);
595 do_div(res, deltapm);
596 pr_info("APIC delta adjusted to PM-Timer: "
597 "%lu (%ld)\n", (unsigned long)res, *delta);
598 *delta = (long)res;
599
600
601 if (cpu_has_tsc) {
602 res = (((u64)(*deltatsc)) * pm_100ms);
603 do_div(res, deltapm);
604 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
605 "PM-Timer: %lu (%ld) \n",
606 (unsigned long)res, *deltatsc);
607 *deltatsc = (long)res;
608 }
609
610 return 0;
611}
612
613static int __init calibrate_APIC_clock(void)
614{
615 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
616 void (*real_handler)(struct clock_event_device *dev);
617 unsigned long deltaj;
618 long delta, deltatsc;
619 int pm_referenced = 0;
620
621 local_irq_disable();
622
623
624 real_handler = global_clock_event->event_handler;
625 global_clock_event->event_handler = lapic_cal_handler;
626
627
628
629
630
631 __setup_APIC_LVTT(0xffffffff, 0, 0);
632
633
634 local_irq_enable();
635
636 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
637 cpu_relax();
638
639 local_irq_disable();
640
641
642 global_clock_event->event_handler = real_handler;
643
644
645 delta = lapic_cal_t1 - lapic_cal_t2;
646 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
647
648 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
649
650
651 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
652 &delta, &deltatsc);
653
654
655 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
656 lapic_clockevent.shift);
657 lapic_clockevent.max_delta_ns =
658 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
659 lapic_clockevent.min_delta_ns =
660 clockevent_delta2ns(0xF, &lapic_clockevent);
661
662 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
663
664 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
665 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
666 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
667 calibration_result);
668
669 if (cpu_has_tsc) {
670 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
671 "%ld.%04ld MHz.\n",
672 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
673 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
674 }
675
676 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
677 "%u.%04u MHz.\n",
678 calibration_result / (1000000 / HZ),
679 calibration_result % (1000000 / HZ));
680
681
682
683
684 if (calibration_result < (1000000 / HZ)) {
685 local_irq_enable();
686 pr_warning("APIC frequency too slow, disabling apic timer\n");
687 return -1;
688 }
689
690 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
691
692
693
694
695
696 if (!pm_referenced) {
697 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
698
699
700
701
702 levt->event_handler = lapic_cal_handler;
703 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
704 lapic_cal_loops = -1;
705
706
707 local_irq_enable();
708
709 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
710 cpu_relax();
711
712
713 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
714
715
716 deltaj = lapic_cal_j2 - lapic_cal_j1;
717 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
718
719
720 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
721 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
722 else
723 levt->features |= CLOCK_EVT_FEAT_DUMMY;
724 } else
725 local_irq_enable();
726
727 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
728 pr_warning("APIC timer disabled due to verification failure\n");
729 return -1;
730 }
731
732 return 0;
733}
734
735
736
737
738
739
740void __init setup_boot_APIC_clock(void)
741{
742
743
744
745
746
747
748 if (disable_apic_timer) {
749 pr_info("Disabling APIC timer\n");
750
751 if (num_possible_cpus() > 1) {
752 lapic_clockevent.mult = 1;
753 setup_APIC_timer();
754 }
755 return;
756 }
757
758 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
759 "calibrating APIC timer ...\n");
760
761 if (calibrate_APIC_clock()) {
762
763 if (num_possible_cpus() > 1)
764 setup_APIC_timer();
765 return;
766 }
767
768
769
770
771
772
773 if (nmi_watchdog != NMI_IO_APIC)
774 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
775 else
776 pr_warning("APIC timer registered as dummy,"
777 " due to nmi_watchdog=%d!\n", nmi_watchdog);
778
779
780 setup_APIC_timer();
781}
782
783void __cpuinit setup_secondary_APIC_clock(void)
784{
785 setup_APIC_timer();
786}
787
788
789
790
791static void local_apic_timer_interrupt(void)
792{
793 int cpu = smp_processor_id();
794 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
795
796
797
798
799
800
801
802
803
804
805
806
807 if (!evt->event_handler) {
808 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
809
810 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
811 return;
812 }
813
814
815
816
817 inc_irq_stat(apic_timer_irqs);
818
819 evt->event_handler(evt);
820}
821
822
823
824
825
826
827
828
829
830void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
831{
832 struct pt_regs *old_regs = set_irq_regs(regs);
833
834
835
836
837
838 ack_APIC_irq();
839
840
841
842
843
844 exit_idle();
845 irq_enter();
846 local_apic_timer_interrupt();
847 irq_exit();
848
849 set_irq_regs(old_regs);
850}
851
852int setup_profiling_timer(unsigned int multiplier)
853{
854 return -EINVAL;
855}
856
857
858
859
860
861
862
863
864
865
866
867
868void clear_local_APIC(void)
869{
870 int maxlvt;
871 u32 v;
872
873
874 if (!x2apic_mode && !apic_phys)
875 return;
876
877 maxlvt = lapic_get_maxlvt();
878
879
880
881
882 if (maxlvt >= 3) {
883 v = ERROR_APIC_VECTOR;
884 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
885 }
886
887
888
889
890 v = apic_read(APIC_LVTT);
891 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
892 v = apic_read(APIC_LVT0);
893 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
894 v = apic_read(APIC_LVT1);
895 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
896 if (maxlvt >= 4) {
897 v = apic_read(APIC_LVTPC);
898 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
899 }
900
901
902#ifdef CONFIG_X86_THERMAL_VECTOR
903 if (maxlvt >= 5) {
904 v = apic_read(APIC_LVTTHMR);
905 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
906 }
907#endif
908#ifdef CONFIG_X86_MCE_INTEL
909 if (maxlvt >= 6) {
910 v = apic_read(APIC_LVTCMCI);
911 if (!(v & APIC_LVT_MASKED))
912 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
913 }
914#endif
915
916
917
918
919 apic_write(APIC_LVTT, APIC_LVT_MASKED);
920 apic_write(APIC_LVT0, APIC_LVT_MASKED);
921 apic_write(APIC_LVT1, APIC_LVT_MASKED);
922 if (maxlvt >= 3)
923 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
924 if (maxlvt >= 4)
925 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
926
927
928 if (lapic_is_integrated()) {
929 if (maxlvt > 3)
930
931 apic_write(APIC_ESR, 0);
932 apic_read(APIC_ESR);
933 }
934}
935
936
937
938
939void disable_local_APIC(void)
940{
941 unsigned int value;
942
943
944 if (!apic_phys)
945 return;
946
947 clear_local_APIC();
948
949
950
951
952
953 value = apic_read(APIC_SPIV);
954 value &= ~APIC_SPIV_APIC_ENABLED;
955 apic_write(APIC_SPIV, value);
956
957#ifdef CONFIG_X86_32
958
959
960
961
962 if (enabled_via_apicbase) {
963 unsigned int l, h;
964
965 rdmsr(MSR_IA32_APICBASE, l, h);
966 l &= ~MSR_IA32_APICBASE_ENABLE;
967 wrmsr(MSR_IA32_APICBASE, l, h);
968 }
969#endif
970}
971
972
973
974
975
976
977
978void lapic_shutdown(void)
979{
980 unsigned long flags;
981
982 if (!cpu_has_apic && !apic_from_smp_config())
983 return;
984
985 local_irq_save(flags);
986
987#ifdef CONFIG_X86_32
988 if (!enabled_via_apicbase)
989 clear_local_APIC();
990 else
991#endif
992 disable_local_APIC();
993
994
995 local_irq_restore(flags);
996}
997
998
999
1000
1001
1002
1003int __init verify_local_APIC(void)
1004{
1005 unsigned int reg0, reg1;
1006
1007
1008
1009
1010 reg0 = apic_read(APIC_LVR);
1011 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1012 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1013 reg1 = apic_read(APIC_LVR);
1014 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1015
1016
1017
1018
1019
1020
1021 if (reg1 != reg0)
1022 return 0;
1023
1024
1025
1026
1027 reg1 = GET_APIC_VERSION(reg0);
1028 if (reg1 == 0x00 || reg1 == 0xff)
1029 return 0;
1030 reg1 = lapic_get_maxlvt();
1031 if (reg1 < 0x02 || reg1 == 0xff)
1032 return 0;
1033
1034
1035
1036
1037 reg0 = apic_read(APIC_ID);
1038 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1039 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1040 reg1 = apic_read(APIC_ID);
1041 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1042 apic_write(APIC_ID, reg0);
1043 if (reg1 != (reg0 ^ apic->apic_id_mask))
1044 return 0;
1045
1046
1047
1048
1049
1050
1051 reg0 = apic_read(APIC_LVT0);
1052 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1053 reg1 = apic_read(APIC_LVT1);
1054 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1055
1056 return 1;
1057}
1058
1059
1060
1061
1062void __init sync_Arb_IDs(void)
1063{
1064
1065
1066
1067
1068 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1069 return;
1070
1071
1072
1073
1074 apic_wait_icr_idle();
1075
1076 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1077 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1078 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1079}
1080
1081
1082
1083
1084void __init init_bsp_APIC(void)
1085{
1086 unsigned int value;
1087
1088
1089
1090
1091
1092 if (smp_found_config || !cpu_has_apic)
1093 return;
1094
1095
1096
1097
1098 clear_local_APIC();
1099
1100
1101
1102
1103 value = apic_read(APIC_SPIV);
1104 value &= ~APIC_VECTOR_MASK;
1105 value |= APIC_SPIV_APIC_ENABLED;
1106
1107#ifdef CONFIG_X86_32
1108
1109 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1110 (boot_cpu_data.x86 == 15))
1111 value &= ~APIC_SPIV_FOCUS_DISABLED;
1112 else
1113#endif
1114 value |= APIC_SPIV_FOCUS_DISABLED;
1115 value |= SPURIOUS_APIC_VECTOR;
1116 apic_write(APIC_SPIV, value);
1117
1118
1119
1120
1121 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1122 value = APIC_DM_NMI;
1123 if (!lapic_is_integrated())
1124 value |= APIC_LVT_LEVEL_TRIGGER;
1125 apic_write(APIC_LVT1, value);
1126}
1127
1128static void __cpuinit lapic_setup_esr(void)
1129{
1130 unsigned int oldvalue, value, maxlvt;
1131
1132 if (!lapic_is_integrated()) {
1133 pr_info("No ESR for 82489DX.\n");
1134 return;
1135 }
1136
1137 if (apic->disable_esr) {
1138
1139
1140
1141
1142
1143
1144 pr_info("Leaving ESR disabled.\n");
1145 return;
1146 }
1147
1148 maxlvt = lapic_get_maxlvt();
1149 if (maxlvt > 3)
1150 apic_write(APIC_ESR, 0);
1151 oldvalue = apic_read(APIC_ESR);
1152
1153
1154 value = ERROR_APIC_VECTOR;
1155 apic_write(APIC_LVTERR, value);
1156
1157
1158
1159
1160 if (maxlvt > 3)
1161 apic_write(APIC_ESR, 0);
1162 value = apic_read(APIC_ESR);
1163 if (value != oldvalue)
1164 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1165 "vector: 0x%08x after: 0x%08x\n",
1166 oldvalue, value);
1167}
1168
1169
1170
1171
1172
1173void __cpuinit setup_local_APIC(void)
1174{
1175 unsigned int value;
1176 int i, j;
1177
1178 if (disable_apic) {
1179 arch_disable_smp_support();
1180 return;
1181 }
1182
1183#ifdef CONFIG_X86_32
1184
1185 if (lapic_is_integrated() && apic->disable_esr) {
1186 apic_write(APIC_ESR, 0);
1187 apic_write(APIC_ESR, 0);
1188 apic_write(APIC_ESR, 0);
1189 apic_write(APIC_ESR, 0);
1190 }
1191#endif
1192 perf_events_lapic_init();
1193
1194 preempt_disable();
1195
1196
1197
1198
1199
1200 BUG_ON(!apic->apic_id_registered());
1201
1202
1203
1204
1205
1206
1207 apic->init_apic_ldr();
1208
1209
1210
1211
1212
1213 value = apic_read(APIC_TASKPRI);
1214 value &= ~APIC_TPRI_MASK;
1215 apic_write(APIC_TASKPRI, value);
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1229 value = apic_read(APIC_ISR + i*0x10);
1230 for (j = 31; j >= 0; j--) {
1231 if (value & (1<<j))
1232 ack_APIC_irq();
1233 }
1234 }
1235
1236
1237
1238
1239 value = apic_read(APIC_SPIV);
1240 value &= ~APIC_VECTOR_MASK;
1241
1242
1243
1244 value |= APIC_SPIV_APIC_ENABLED;
1245
1246#ifdef CONFIG_X86_32
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272 value &= ~APIC_SPIV_FOCUS_DISABLED;
1273#endif
1274
1275
1276
1277
1278 value |= SPURIOUS_APIC_VECTOR;
1279 apic_write(APIC_SPIV, value);
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1292 if (!smp_processor_id() && (pic_mode || !value)) {
1293 value = APIC_DM_EXTINT;
1294 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1295 smp_processor_id());
1296 } else {
1297 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1298 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1299 smp_processor_id());
1300 }
1301 apic_write(APIC_LVT0, value);
1302
1303
1304
1305
1306 if (!smp_processor_id())
1307 value = APIC_DM_NMI;
1308 else
1309 value = APIC_DM_NMI | APIC_LVT_MASKED;
1310 if (!lapic_is_integrated())
1311 value |= APIC_LVT_LEVEL_TRIGGER;
1312 apic_write(APIC_LVT1, value);
1313
1314 preempt_enable();
1315
1316#ifdef CONFIG_X86_MCE_INTEL
1317
1318 if (smp_processor_id() == 0)
1319 cmci_recheck();
1320#endif
1321}
1322
1323void __cpuinit end_local_APIC_setup(void)
1324{
1325 lapic_setup_esr();
1326
1327#ifdef CONFIG_X86_32
1328 {
1329 unsigned int value;
1330
1331 value = apic_read(APIC_LVTT);
1332 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1333 apic_write(APIC_LVTT, value);
1334 }
1335#endif
1336
1337 setup_apic_nmi_watchdog(NULL);
1338 apic_pm_activate();
1339}
1340
1341#ifdef CONFIG_X86_X2APIC
1342void check_x2apic(void)
1343{
1344 if (x2apic_enabled()) {
1345 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1346 x2apic_preenabled = x2apic_mode = 1;
1347 }
1348}
1349
1350void enable_x2apic(void)
1351{
1352 int msr, msr2;
1353
1354 if (!x2apic_mode)
1355 return;
1356
1357 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1358 if (!(msr & X2APIC_ENABLE)) {
1359 pr_info("Enabling x2apic\n");
1360 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1361 }
1362}
1363#endif
1364
1365int __init enable_IR(void)
1366{
1367#ifdef CONFIG_INTR_REMAP
1368 if (!intr_remapping_supported()) {
1369 pr_debug("intr-remapping not supported\n");
1370 return 0;
1371 }
1372
1373 if (!x2apic_preenabled && skip_ioapic_setup) {
1374 pr_info("Skipped enabling intr-remap because of skipping "
1375 "io-apic setup\n");
1376 return 0;
1377 }
1378
1379 if (enable_intr_remapping(x2apic_supported()))
1380 return 0;
1381
1382 pr_info("Enabled Interrupt-remapping\n");
1383
1384 return 1;
1385
1386#endif
1387 return 0;
1388}
1389
1390void __init enable_IR_x2apic(void)
1391{
1392 unsigned long flags;
1393 struct IO_APIC_route_entry **ioapic_entries = NULL;
1394 int ret, x2apic_enabled = 0;
1395 int dmar_table_init_ret = 0;
1396
1397#ifdef CONFIG_INTR_REMAP
1398 dmar_table_init_ret = dmar_table_init();
1399 if (dmar_table_init_ret)
1400 pr_debug("dmar_table_init() failed with %d:\n",
1401 dmar_table_init_ret);
1402#endif
1403
1404 ioapic_entries = alloc_ioapic_entries();
1405 if (!ioapic_entries) {
1406 pr_err("Allocate ioapic_entries failed\n");
1407 goto out;
1408 }
1409
1410 ret = save_IO_APIC_setup(ioapic_entries);
1411 if (ret) {
1412 pr_info("Saving IO-APIC state failed: %d\n", ret);
1413 goto out;
1414 }
1415
1416 local_irq_save(flags);
1417 mask_8259A();
1418 mask_IO_APIC_setup(ioapic_entries);
1419
1420 if (dmar_table_init_ret)
1421 ret = 0;
1422 else
1423 ret = enable_IR();
1424
1425 if (!ret) {
1426
1427
1428
1429 if (max_physical_apicid > 255 || !kvm_para_available())
1430 goto nox2apic;
1431
1432
1433
1434
1435 x2apic_force_phys();
1436 }
1437
1438 x2apic_enabled = 1;
1439
1440 if (x2apic_supported() && !x2apic_mode) {
1441 x2apic_mode = 1;
1442 enable_x2apic();
1443 pr_info("Enabled x2apic\n");
1444 }
1445
1446nox2apic:
1447 if (!ret)
1448 restore_IO_APIC_setup(ioapic_entries);
1449 unmask_8259A();
1450 local_irq_restore(flags);
1451
1452out:
1453 if (ioapic_entries)
1454 free_ioapic_entries(ioapic_entries);
1455
1456 if (x2apic_enabled)
1457 return;
1458
1459 if (x2apic_preenabled)
1460 panic("x2apic: enabled by BIOS but kernel init failed.");
1461 else if (cpu_has_x2apic)
1462 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1463}
1464
1465#ifdef CONFIG_X86_64
1466
1467
1468
1469
1470
1471
1472static int __init detect_init_APIC(void)
1473{
1474 if (!cpu_has_apic) {
1475 pr_info("No local APIC present\n");
1476 return -1;
1477 }
1478
1479 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1480 return 0;
1481}
1482#else
1483
1484
1485
1486static int __init detect_init_APIC(void)
1487{
1488 u32 h, l, features;
1489
1490
1491 if (disable_apic)
1492 return -1;
1493
1494 switch (boot_cpu_data.x86_vendor) {
1495 case X86_VENDOR_AMD:
1496 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1497 (boot_cpu_data.x86 >= 15))
1498 break;
1499 goto no_apic;
1500 case X86_VENDOR_INTEL:
1501 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1502 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1503 break;
1504 goto no_apic;
1505 default:
1506 goto no_apic;
1507 }
1508
1509 if (!cpu_has_apic) {
1510
1511
1512
1513
1514 if (!force_enable_local_apic) {
1515 pr_info("Local APIC disabled by BIOS -- "
1516 "you can enable it with \"lapic\"\n");
1517 return -1;
1518 }
1519
1520
1521
1522
1523
1524 rdmsr(MSR_IA32_APICBASE, l, h);
1525 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1526 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1527 l &= ~MSR_IA32_APICBASE_BASE;
1528 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1529 wrmsr(MSR_IA32_APICBASE, l, h);
1530 enabled_via_apicbase = 1;
1531 }
1532 }
1533
1534
1535
1536
1537 features = cpuid_edx(1);
1538 if (!(features & (1 << X86_FEATURE_APIC))) {
1539 pr_warning("Could not enable APIC!\n");
1540 return -1;
1541 }
1542 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1543 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1544
1545
1546 rdmsr(MSR_IA32_APICBASE, l, h);
1547 if (l & MSR_IA32_APICBASE_ENABLE)
1548 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1549
1550 pr_info("Found and enabled local APIC!\n");
1551
1552 apic_pm_activate();
1553
1554 return 0;
1555
1556no_apic:
1557 pr_info("No local APIC present or hardware disabled\n");
1558 return -1;
1559}
1560#endif
1561
1562#ifdef CONFIG_X86_64
1563void __init early_init_lapic_mapping(void)
1564{
1565
1566
1567
1568
1569 if (!smp_found_config)
1570 return;
1571
1572 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
1573 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1574 APIC_BASE, mp_lapic_addr);
1575
1576
1577
1578
1579
1580 boot_cpu_physical_apicid = read_apic_id();
1581}
1582#endif
1583
1584
1585
1586
1587void __init init_apic_mappings(void)
1588{
1589 unsigned int new_apicid;
1590
1591 if (x2apic_mode) {
1592 boot_cpu_physical_apicid = read_apic_id();
1593 return;
1594 }
1595
1596
1597 if (!smp_found_config && detect_init_APIC()) {
1598
1599 pr_info("APIC: disable apic facility\n");
1600 apic_disable();
1601 } else {
1602 apic_phys = mp_lapic_addr;
1603
1604
1605
1606
1607
1608 if (!acpi_lapic)
1609 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1610
1611 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1612 APIC_BASE, apic_phys);
1613 }
1614
1615
1616
1617
1618
1619 new_apicid = read_apic_id();
1620 if (boot_cpu_physical_apicid != new_apicid) {
1621 boot_cpu_physical_apicid = new_apicid;
1622
1623
1624
1625
1626
1627
1628
1629 apic_version[new_apicid] =
1630 GET_APIC_VERSION(apic_read(APIC_LVR));
1631 }
1632}
1633
1634
1635
1636
1637
1638int apic_version[MAX_APICS];
1639
1640int __init APIC_init_uniprocessor(void)
1641{
1642 if (disable_apic) {
1643 pr_info("Apic disabled\n");
1644 return -1;
1645 }
1646#ifdef CONFIG_X86_64
1647 if (!cpu_has_apic) {
1648 disable_apic = 1;
1649 pr_info("Apic disabled by BIOS\n");
1650 return -1;
1651 }
1652#else
1653 if (!smp_found_config && !cpu_has_apic)
1654 return -1;
1655
1656
1657
1658
1659 if (!cpu_has_apic &&
1660 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1661 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1662 boot_cpu_physical_apicid);
1663 return -1;
1664 }
1665#endif
1666
1667 enable_IR_x2apic();
1668#ifdef CONFIG_X86_64
1669 default_setup_apic_routing();
1670#endif
1671
1672 verify_local_APIC();
1673 connect_bsp_APIC();
1674
1675#ifdef CONFIG_X86_64
1676 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1677#else
1678
1679
1680
1681
1682
1683# ifdef CONFIG_CRASH_DUMP
1684 boot_cpu_physical_apicid = read_apic_id();
1685# endif
1686#endif
1687 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1688 setup_local_APIC();
1689
1690#ifdef CONFIG_X86_IO_APIC
1691
1692
1693
1694
1695 if (!skip_ioapic_setup && nr_ioapics)
1696 enable_IO_APIC();
1697#endif
1698
1699 end_local_APIC_setup();
1700
1701#ifdef CONFIG_X86_IO_APIC
1702 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1703 setup_IO_APIC();
1704 else {
1705 nr_ioapics = 0;
1706 localise_nmi_watchdog();
1707 }
1708#else
1709 localise_nmi_watchdog();
1710#endif
1711
1712 x86_init.timers.setup_percpu_clockev();
1713#ifdef CONFIG_X86_64
1714 check_nmi_watchdog();
1715#endif
1716
1717 return 0;
1718}
1719
1720
1721
1722
1723
1724
1725
1726
1727void smp_spurious_interrupt(struct pt_regs *regs)
1728{
1729 u32 v;
1730
1731 exit_idle();
1732 irq_enter();
1733
1734
1735
1736
1737
1738 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1739 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1740 ack_APIC_irq();
1741
1742 inc_irq_stat(irq_spurious_count);
1743
1744
1745 pr_info("spurious APIC interrupt on CPU#%d, "
1746 "should never happen.\n", smp_processor_id());
1747 irq_exit();
1748}
1749
1750
1751
1752
1753void smp_error_interrupt(struct pt_regs *regs)
1754{
1755 u32 v, v1;
1756
1757 exit_idle();
1758 irq_enter();
1759
1760 v = apic_read(APIC_ESR);
1761 apic_write(APIC_ESR, 0);
1762 v1 = apic_read(APIC_ESR);
1763 ack_APIC_irq();
1764 atomic_inc(&irq_err_count);
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1778 smp_processor_id(), v , v1);
1779 irq_exit();
1780}
1781
1782
1783
1784
1785void __init connect_bsp_APIC(void)
1786{
1787#ifdef CONFIG_X86_32
1788 if (pic_mode) {
1789
1790
1791
1792 clear_local_APIC();
1793
1794
1795
1796
1797 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1798 "enabling APIC mode.\n");
1799 imcr_pic_to_apic();
1800 }
1801#endif
1802 if (apic->enable_apic_mode)
1803 apic->enable_apic_mode();
1804}
1805
1806
1807
1808
1809
1810
1811
1812
1813void disconnect_bsp_APIC(int virt_wire_setup)
1814{
1815 unsigned int value;
1816
1817#ifdef CONFIG_X86_32
1818 if (pic_mode) {
1819
1820
1821
1822
1823
1824
1825 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1826 "entering PIC mode.\n");
1827 imcr_apic_to_pic();
1828 return;
1829 }
1830#endif
1831
1832
1833
1834
1835 value = apic_read(APIC_SPIV);
1836 value &= ~APIC_VECTOR_MASK;
1837 value |= APIC_SPIV_APIC_ENABLED;
1838 value |= 0xf;
1839 apic_write(APIC_SPIV, value);
1840
1841 if (!virt_wire_setup) {
1842
1843
1844
1845
1846 value = apic_read(APIC_LVT0);
1847 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1848 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1849 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1850 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1851 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1852 apic_write(APIC_LVT0, value);
1853 } else {
1854
1855 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1856 }
1857
1858
1859
1860
1861
1862 value = apic_read(APIC_LVT1);
1863 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1864 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1865 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1866 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1867 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1868 apic_write(APIC_LVT1, value);
1869}
1870
1871void __cpuinit generic_processor_info(int apicid, int version)
1872{
1873 int cpu;
1874
1875
1876
1877
1878 if (version == 0x0) {
1879 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1880 "fixing up to 0x10. (tell your hw vendor)\n",
1881 version);
1882 version = 0x10;
1883 }
1884 apic_version[apicid] = version;
1885
1886 if (num_processors >= nr_cpu_ids) {
1887 int max = nr_cpu_ids;
1888 int thiscpu = max + disabled_cpus;
1889
1890 pr_warning(
1891 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1892 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1893
1894 disabled_cpus++;
1895 return;
1896 }
1897
1898 num_processors++;
1899 cpu = cpumask_next_zero(-1, cpu_present_mask);
1900
1901 if (version != apic_version[boot_cpu_physical_apicid])
1902 WARN_ONCE(1,
1903 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1904 apic_version[boot_cpu_physical_apicid], cpu, version);
1905
1906 physid_set(apicid, phys_cpu_present_map);
1907 if (apicid == boot_cpu_physical_apicid) {
1908
1909
1910
1911
1912
1913 cpu = 0;
1914 }
1915 if (apicid > max_physical_apicid)
1916 max_physical_apicid = apicid;
1917
1918#ifdef CONFIG_X86_32
1919 switch (boot_cpu_data.x86_vendor) {
1920 case X86_VENDOR_INTEL:
1921 if (num_processors > 8)
1922 def_to_bigsmp = 1;
1923 break;
1924 case X86_VENDOR_AMD:
1925 if (max_physical_apicid >= 8)
1926 def_to_bigsmp = 1;
1927 }
1928#endif
1929
1930#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1931 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1932 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1933#endif
1934
1935 set_cpu_possible(cpu, true);
1936 set_cpu_present(cpu, true);
1937}
1938
1939int hard_smp_processor_id(void)
1940{
1941 return read_apic_id();
1942}
1943
1944void default_init_apic_ldr(void)
1945{
1946 unsigned long val;
1947
1948 apic_write(APIC_DFR, APIC_DFR_VALUE);
1949 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1950 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1951 apic_write(APIC_LDR, val);
1952}
1953
1954#ifdef CONFIG_X86_32
1955int default_apicid_to_node(int logical_apicid)
1956{
1957#ifdef CONFIG_SMP
1958 return apicid_2_node[hard_smp_processor_id()];
1959#else
1960 return 0;
1961#endif
1962}
1963#endif
1964
1965
1966
1967
1968#ifdef CONFIG_PM
1969
1970static struct {
1971
1972
1973
1974
1975
1976 int active;
1977
1978 unsigned int apic_id;
1979 unsigned int apic_taskpri;
1980 unsigned int apic_ldr;
1981 unsigned int apic_dfr;
1982 unsigned int apic_spiv;
1983 unsigned int apic_lvtt;
1984 unsigned int apic_lvtpc;
1985 unsigned int apic_lvt0;
1986 unsigned int apic_lvt1;
1987 unsigned int apic_lvterr;
1988 unsigned int apic_tmict;
1989 unsigned int apic_tdcr;
1990 unsigned int apic_thmr;
1991} apic_pm_state;
1992
1993static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1994{
1995 unsigned long flags;
1996 int maxlvt;
1997
1998 if (!apic_pm_state.active)
1999 return 0;
2000
2001 maxlvt = lapic_get_maxlvt();
2002
2003 apic_pm_state.apic_id = apic_read(APIC_ID);
2004 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2005 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2006 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2007 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2008 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2009 if (maxlvt >= 4)
2010 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2011 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2012 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2013 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2014 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2015 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2016#ifdef CONFIG_X86_THERMAL_VECTOR
2017 if (maxlvt >= 5)
2018 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2019#endif
2020
2021 local_irq_save(flags);
2022 disable_local_APIC();
2023
2024 if (intr_remapping_enabled)
2025 disable_intr_remapping();
2026
2027 local_irq_restore(flags);
2028 return 0;
2029}
2030
2031static int lapic_resume(struct sys_device *dev)
2032{
2033 unsigned int l, h;
2034 unsigned long flags;
2035 int maxlvt;
2036 int ret = 0;
2037 struct IO_APIC_route_entry **ioapic_entries = NULL;
2038
2039 if (!apic_pm_state.active)
2040 return 0;
2041
2042 local_irq_save(flags);
2043 if (intr_remapping_enabled) {
2044 ioapic_entries = alloc_ioapic_entries();
2045 if (!ioapic_entries) {
2046 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2047 ret = -ENOMEM;
2048 goto restore;
2049 }
2050
2051 ret = save_IO_APIC_setup(ioapic_entries);
2052 if (ret) {
2053 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2054 free_ioapic_entries(ioapic_entries);
2055 goto restore;
2056 }
2057
2058 mask_IO_APIC_setup(ioapic_entries);
2059 mask_8259A();
2060 }
2061
2062 if (x2apic_mode)
2063 enable_x2apic();
2064 else {
2065
2066
2067
2068
2069
2070
2071 rdmsr(MSR_IA32_APICBASE, l, h);
2072 l &= ~MSR_IA32_APICBASE_BASE;
2073 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2074 wrmsr(MSR_IA32_APICBASE, l, h);
2075 }
2076
2077 maxlvt = lapic_get_maxlvt();
2078 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2079 apic_write(APIC_ID, apic_pm_state.apic_id);
2080 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2081 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2082 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2083 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2084 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2085 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2086#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2087 if (maxlvt >= 5)
2088 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2089#endif
2090 if (maxlvt >= 4)
2091 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2092 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2093 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2094 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2095 apic_write(APIC_ESR, 0);
2096 apic_read(APIC_ESR);
2097 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2098 apic_write(APIC_ESR, 0);
2099 apic_read(APIC_ESR);
2100
2101 if (intr_remapping_enabled) {
2102 reenable_intr_remapping(x2apic_mode);
2103 unmask_8259A();
2104 restore_IO_APIC_setup(ioapic_entries);
2105 free_ioapic_entries(ioapic_entries);
2106 }
2107restore:
2108 local_irq_restore(flags);
2109
2110 return ret;
2111}
2112
2113
2114
2115
2116
2117
2118static struct sysdev_class lapic_sysclass = {
2119 .name = "lapic",
2120 .resume = lapic_resume,
2121 .suspend = lapic_suspend,
2122};
2123
2124static struct sys_device device_lapic = {
2125 .id = 0,
2126 .cls = &lapic_sysclass,
2127};
2128
2129static void __cpuinit apic_pm_activate(void)
2130{
2131 apic_pm_state.active = 1;
2132}
2133
2134static int __init init_lapic_sysfs(void)
2135{
2136 int error;
2137
2138 if (!cpu_has_apic)
2139 return 0;
2140
2141
2142 error = sysdev_class_register(&lapic_sysclass);
2143 if (!error)
2144 error = sysdev_register(&device_lapic);
2145 return error;
2146}
2147
2148
2149core_initcall(init_lapic_sysfs);
2150
2151#else
2152
2153static void apic_pm_activate(void) { }
2154
2155#endif
2156
2157#ifdef CONFIG_X86_64
2158
2159static int __cpuinit apic_cluster_num(void)
2160{
2161 int i, clusters, zeros;
2162 unsigned id;
2163 u16 *bios_cpu_apicid;
2164 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2165
2166 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2167 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2168
2169 for (i = 0; i < nr_cpu_ids; i++) {
2170
2171 if (bios_cpu_apicid) {
2172 id = bios_cpu_apicid[i];
2173 } else if (i < nr_cpu_ids) {
2174 if (cpu_present(i))
2175 id = per_cpu(x86_bios_cpu_apicid, i);
2176 else
2177 continue;
2178 } else
2179 break;
2180
2181 if (id != BAD_APICID)
2182 __set_bit(APIC_CLUSTERID(id), clustermap);
2183 }
2184
2185
2186
2187
2188
2189
2190
2191 clusters = 0;
2192 zeros = 0;
2193 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2194 if (test_bit(i, clustermap)) {
2195 clusters += 1 + zeros;
2196 zeros = 0;
2197 } else
2198 ++zeros;
2199 }
2200
2201 return clusters;
2202}
2203
2204static int __cpuinitdata multi_checked;
2205static int __cpuinitdata multi;
2206
2207static int __cpuinit set_multi(const struct dmi_system_id *d)
2208{
2209 if (multi)
2210 return 0;
2211 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2212 multi = 1;
2213 return 0;
2214}
2215
2216static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2217 {
2218 .callback = set_multi,
2219 .ident = "IBM System Summit2",
2220 .matches = {
2221 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2222 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2223 },
2224 },
2225 {}
2226};
2227
2228static void __cpuinit dmi_check_multi(void)
2229{
2230 if (multi_checked)
2231 return;
2232
2233 dmi_check_system(multi_dmi_table);
2234 multi_checked = 1;
2235}
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245__cpuinit int apic_is_clustered_box(void)
2246{
2247 dmi_check_multi();
2248 if (multi)
2249 return 1;
2250
2251 if (!is_vsmp_box())
2252 return 0;
2253
2254
2255
2256
2257
2258 if (apic_cluster_num() > 1)
2259 return 1;
2260
2261 return 0;
2262}
2263#endif
2264
2265
2266
2267
2268static int __init setup_disableapic(char *arg)
2269{
2270 disable_apic = 1;
2271 setup_clear_cpu_cap(X86_FEATURE_APIC);
2272 return 0;
2273}
2274early_param("disableapic", setup_disableapic);
2275
2276
2277static int __init setup_nolapic(char *arg)
2278{
2279 return setup_disableapic(arg);
2280}
2281early_param("nolapic", setup_nolapic);
2282
2283static int __init parse_lapic_timer_c2_ok(char *arg)
2284{
2285 local_apic_timer_c2_ok = 1;
2286 return 0;
2287}
2288early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2289
2290static int __init parse_disable_apic_timer(char *arg)
2291{
2292 disable_apic_timer = 1;
2293 return 0;
2294}
2295early_param("noapictimer", parse_disable_apic_timer);
2296
2297static int __init parse_nolapic_timer(char *arg)
2298{
2299 disable_apic_timer = 1;
2300 return 0;
2301}
2302early_param("nolapic_timer", parse_nolapic_timer);
2303
2304static int __init apic_set_verbosity(char *arg)
2305{
2306 if (!arg) {
2307#ifdef CONFIG_X86_64
2308 skip_ioapic_setup = 0;
2309 return 0;
2310#endif
2311 return -EINVAL;
2312 }
2313
2314 if (strcmp("debug", arg) == 0)
2315 apic_verbosity = APIC_DEBUG;
2316 else if (strcmp("verbose", arg) == 0)
2317 apic_verbosity = APIC_VERBOSE;
2318 else {
2319 pr_warning("APIC Verbosity level %s not recognised"
2320 " use apic=verbose or apic=debug\n", arg);
2321 return -EINVAL;
2322 }
2323
2324 return 0;
2325}
2326early_param("apic", apic_set_verbosity);
2327
2328static int __init lapic_insert_resource(void)
2329{
2330 if (!apic_phys)
2331 return -1;
2332
2333
2334 lapic_resource.start = apic_phys;
2335 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2336 insert_resource(&iomem_resource, &lapic_resource);
2337
2338 return 0;
2339}
2340
2341
2342
2343
2344
2345late_initcall(lapic_insert_resource);
2346