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16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/cpufreq.h>
20#include <linux/sched.h>
21#include <linux/delay.h>
22#include <linux/compiler.h>
23
24#include <asm/msr.h>
25#include <asm/processor.h>
26#include <asm/cpufeature.h>
27
28#define PFX "speedstep-centrino: "
29#define MAINTAINER "cpufreq@vger.kernel.org"
30
31#define dprintk(msg...) \
32 cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
33
34#define INTEL_MSR_RANGE (0xffff)
35
36struct cpu_id
37{
38 __u8 x86;
39 __u8 x86_model;
40 __u8 x86_mask;
41};
42
43enum {
44 CPU_BANIAS,
45 CPU_DOTHAN_A1,
46 CPU_DOTHAN_A2,
47 CPU_DOTHAN_B0,
48 CPU_MP4HT_D0,
49 CPU_MP4HT_E0,
50};
51
52static const struct cpu_id cpu_ids[] = {
53 [CPU_BANIAS] = { 6, 9, 5 },
54 [CPU_DOTHAN_A1] = { 6, 13, 1 },
55 [CPU_DOTHAN_A2] = { 6, 13, 2 },
56 [CPU_DOTHAN_B0] = { 6, 13, 6 },
57 [CPU_MP4HT_D0] = {15, 3, 4 },
58 [CPU_MP4HT_E0] = {15, 4, 1 },
59};
60#define N_IDS ARRAY_SIZE(cpu_ids)
61
62struct cpu_model
63{
64 const struct cpu_id *cpu_id;
65 const char *model_name;
66 unsigned max_freq;
67
68 struct cpufreq_frequency_table *op_points;
69};
70static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
71 const struct cpu_id *x);
72
73
74static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
75static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
76
77static struct cpufreq_driver centrino_driver;
78
79#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
80
81
82
83
84#define OP(mhz, mv) \
85 { \
86 .frequency = (mhz) * 1000, \
87 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
88 }
89
90
91
92
93
94
95
96
97
98static struct cpufreq_frequency_table banias_900[] =
99{
100 OP(600, 844),
101 OP(800, 988),
102 OP(900, 1004),
103 { .frequency = CPUFREQ_TABLE_END }
104};
105
106
107static struct cpufreq_frequency_table banias_1000[] =
108{
109 OP(600, 844),
110 OP(800, 972),
111 OP(900, 988),
112 OP(1000, 1004),
113 { .frequency = CPUFREQ_TABLE_END }
114};
115
116
117static struct cpufreq_frequency_table banias_1100[] =
118{
119 OP( 600, 956),
120 OP( 800, 1020),
121 OP( 900, 1100),
122 OP(1000, 1164),
123 OP(1100, 1180),
124 { .frequency = CPUFREQ_TABLE_END }
125};
126
127
128
129static struct cpufreq_frequency_table banias_1200[] =
130{
131 OP( 600, 956),
132 OP( 800, 1004),
133 OP( 900, 1020),
134 OP(1000, 1100),
135 OP(1100, 1164),
136 OP(1200, 1180),
137 { .frequency = CPUFREQ_TABLE_END }
138};
139
140
141static struct cpufreq_frequency_table banias_1300[] =
142{
143 OP( 600, 956),
144 OP( 800, 1260),
145 OP(1000, 1292),
146 OP(1200, 1356),
147 OP(1300, 1388),
148 { .frequency = CPUFREQ_TABLE_END }
149};
150
151
152static struct cpufreq_frequency_table banias_1400[] =
153{
154 OP( 600, 956),
155 OP( 800, 1180),
156 OP(1000, 1308),
157 OP(1200, 1436),
158 OP(1400, 1484),
159 { .frequency = CPUFREQ_TABLE_END }
160};
161
162
163static struct cpufreq_frequency_table banias_1500[] =
164{
165 OP( 600, 956),
166 OP( 800, 1116),
167 OP(1000, 1228),
168 OP(1200, 1356),
169 OP(1400, 1452),
170 OP(1500, 1484),
171 { .frequency = CPUFREQ_TABLE_END }
172};
173
174
175static struct cpufreq_frequency_table banias_1600[] =
176{
177 OP( 600, 956),
178 OP( 800, 1036),
179 OP(1000, 1164),
180 OP(1200, 1276),
181 OP(1400, 1420),
182 OP(1600, 1484),
183 { .frequency = CPUFREQ_TABLE_END }
184};
185
186
187static struct cpufreq_frequency_table banias_1700[] =
188{
189 OP( 600, 956),
190 OP( 800, 1004),
191 OP(1000, 1116),
192 OP(1200, 1228),
193 OP(1400, 1308),
194 OP(1700, 1484),
195 { .frequency = CPUFREQ_TABLE_END }
196};
197#undef OP
198
199#define _BANIAS(cpuid, max, name) \
200{ .cpu_id = cpuid, \
201 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
202 .max_freq = (max)*1000, \
203 .op_points = banias_##max, \
204}
205#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
206
207
208
209static struct cpu_model models[] =
210{
211 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
212 BANIAS(1000),
213 BANIAS(1100),
214 BANIAS(1200),
215 BANIAS(1300),
216 BANIAS(1400),
217 BANIAS(1500),
218 BANIAS(1600),
219 BANIAS(1700),
220
221
222 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
223 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
224 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
225 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
226 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
227
228 { NULL, }
229};
230#undef _BANIAS
231#undef BANIAS
232
233static int centrino_cpu_init_table(struct cpufreq_policy *policy)
234{
235 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
236 struct cpu_model *model;
237
238 for(model = models; model->cpu_id != NULL; model++)
239 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
240 (model->model_name == NULL ||
241 strcmp(cpu->x86_model_id, model->model_name) == 0))
242 break;
243
244 if (model->cpu_id == NULL) {
245
246 dprintk("no support for CPU model \"%s\": "
247 "send /proc/cpuinfo to " MAINTAINER "\n",
248 cpu->x86_model_id);
249 return -ENOENT;
250 }
251
252 if (model->op_points == NULL) {
253
254 dprintk("no table support for CPU model \"%s\"\n",
255 cpu->x86_model_id);
256 dprintk("try using the acpi-cpufreq driver\n");
257 return -ENOENT;
258 }
259
260 per_cpu(centrino_model, policy->cpu) = model;
261
262 dprintk("found \"%s\": max frequency: %dkHz\n",
263 model->model_name, model->max_freq);
264
265 return 0;
266}
267
268#else
269static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
270{
271 return -ENODEV;
272}
273#endif
274
275static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
276 const struct cpu_id *x)
277{
278 if ((c->x86 == x->x86) &&
279 (c->x86_model == x->x86_model) &&
280 (c->x86_mask == x->x86_mask))
281 return 1;
282 return 0;
283}
284
285
286static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
287{
288 int i;
289
290
291
292
293
294
295 if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
296 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
297 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
298 msr = (msr >> 8) & 0xff;
299 return msr * 100000;
300 }
301
302 if ((!per_cpu(centrino_model, cpu)) ||
303 (!per_cpu(centrino_model, cpu)->op_points))
304 return 0;
305
306 msr &= 0xffff;
307 for (i = 0;
308 per_cpu(centrino_model, cpu)->op_points[i].frequency
309 != CPUFREQ_TABLE_END;
310 i++) {
311 if (msr == per_cpu(centrino_model, cpu)->op_points[i].index)
312 return per_cpu(centrino_model, cpu)->
313 op_points[i].frequency;
314 }
315 if (failsafe)
316 return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
317 else
318 return 0;
319}
320
321
322static unsigned int get_cur_freq(unsigned int cpu)
323{
324 unsigned l, h;
325 unsigned clock_freq;
326
327 rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
328 clock_freq = extract_clock(l, cpu, 0);
329
330 if (unlikely(clock_freq == 0)) {
331
332
333
334
335
336
337 rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
338 clock_freq = extract_clock(l, cpu, 1);
339 }
340 return clock_freq;
341}
342
343
344static int centrino_cpu_init(struct cpufreq_policy *policy)
345{
346 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
347 unsigned freq;
348 unsigned l, h;
349 int ret;
350 int i;
351
352
353 if (cpu->x86_vendor != X86_VENDOR_INTEL ||
354 !cpu_has(cpu, X86_FEATURE_EST))
355 return -ENODEV;
356
357 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
358 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
359
360 if (policy->cpu != 0)
361 return -ENODEV;
362
363 for (i = 0; i < N_IDS; i++)
364 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
365 break;
366
367 if (i != N_IDS)
368 per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
369
370 if (!per_cpu(centrino_cpu, policy->cpu)) {
371 dprintk("found unsupported CPU with "
372 "Enhanced SpeedStep: send /proc/cpuinfo to "
373 MAINTAINER "\n");
374 return -ENODEV;
375 }
376
377 if (centrino_cpu_init_table(policy)) {
378 return -ENODEV;
379 }
380
381
382
383 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
384
385 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
386 l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
387 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
388 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
389
390
391 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
392 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
393 printk(KERN_INFO PFX
394 "couldn't enable Enhanced SpeedStep\n");
395 return -ENODEV;
396 }
397 }
398
399 freq = get_cur_freq(policy->cpu);
400 policy->cpuinfo.transition_latency = 10000;
401
402 policy->cur = freq;
403
404 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
405
406 ret = cpufreq_frequency_table_cpuinfo(policy,
407 per_cpu(centrino_model, policy->cpu)->op_points);
408 if (ret)
409 return (ret);
410
411 cpufreq_frequency_table_get_attr(
412 per_cpu(centrino_model, policy->cpu)->op_points, policy->cpu);
413
414 return 0;
415}
416
417static int centrino_cpu_exit(struct cpufreq_policy *policy)
418{
419 unsigned int cpu = policy->cpu;
420
421 if (!per_cpu(centrino_model, cpu))
422 return -ENODEV;
423
424 cpufreq_frequency_table_put_attr(cpu);
425
426 per_cpu(centrino_model, cpu) = NULL;
427
428 return 0;
429}
430
431
432
433
434
435
436
437
438static int centrino_verify (struct cpufreq_policy *policy)
439{
440 return cpufreq_frequency_table_verify(policy,
441 per_cpu(centrino_model, policy->cpu)->op_points);
442}
443
444
445
446
447
448
449
450
451
452
453static int centrino_target (struct cpufreq_policy *policy,
454 unsigned int target_freq,
455 unsigned int relation)
456{
457 unsigned int newstate = 0;
458 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
459 struct cpufreq_freqs freqs;
460 int retval = 0;
461 unsigned int j, k, first_cpu, tmp;
462 cpumask_var_t covered_cpus;
463
464 if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
465 return -ENOMEM;
466
467 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
468 retval = -ENODEV;
469 goto out;
470 }
471
472 if (unlikely(cpufreq_frequency_table_target(policy,
473 per_cpu(centrino_model, cpu)->op_points,
474 target_freq,
475 relation,
476 &newstate))) {
477 retval = -EINVAL;
478 goto out;
479 }
480
481 first_cpu = 1;
482 for_each_cpu(j, policy->cpus) {
483 int good_cpu;
484
485
486 if (!cpu_online(j))
487 continue;
488
489
490
491
492
493 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
494 good_cpu = cpumask_any_and(policy->cpus,
495 cpu_online_mask);
496 else
497 good_cpu = j;
498
499 if (good_cpu >= nr_cpu_ids) {
500 dprintk("couldn't limit to CPUs in this domain\n");
501 retval = -EAGAIN;
502 if (first_cpu) {
503
504 goto out;
505 }
506 break;
507 }
508
509 msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
510
511 if (first_cpu) {
512 rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
513 if (msr == (oldmsr & 0xffff)) {
514 dprintk("no change needed - msr was and needs "
515 "to be %x\n", oldmsr);
516 retval = 0;
517 goto out;
518 }
519
520 freqs.old = extract_clock(oldmsr, cpu, 0);
521 freqs.new = extract_clock(msr, cpu, 0);
522
523 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
524 target_freq, freqs.old, freqs.new, msr);
525
526 for_each_cpu(k, policy->cpus) {
527 if (!cpu_online(k))
528 continue;
529 freqs.cpu = k;
530 cpufreq_notify_transition(&freqs,
531 CPUFREQ_PRECHANGE);
532 }
533
534 first_cpu = 0;
535
536 oldmsr &= ~0xffff;
537 msr &= 0xffff;
538 oldmsr |= msr;
539 }
540
541 wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
542 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
543 break;
544
545 cpumask_set_cpu(j, covered_cpus);
546 }
547
548 for_each_cpu(k, policy->cpus) {
549 if (!cpu_online(k))
550 continue;
551 freqs.cpu = k;
552 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
553 }
554
555 if (unlikely(retval)) {
556
557
558
559
560
561
562
563 for_each_cpu(j, covered_cpus)
564 wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
565
566 tmp = freqs.new;
567 freqs.new = freqs.old;
568 freqs.old = tmp;
569 for_each_cpu(j, policy->cpus) {
570 if (!cpu_online(j))
571 continue;
572 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
573 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
574 }
575 }
576 retval = 0;
577
578out:
579 free_cpumask_var(covered_cpus);
580 return retval;
581}
582
583static struct freq_attr* centrino_attr[] = {
584 &cpufreq_freq_attr_scaling_available_freqs,
585 NULL,
586};
587
588static struct cpufreq_driver centrino_driver = {
589 .name = "centrino",
590
591 .init = centrino_cpu_init,
592 .exit = centrino_cpu_exit,
593 .verify = centrino_verify,
594 .target = centrino_target,
595 .get = get_cur_freq,
596 .attr = centrino_attr,
597 .owner = THIS_MODULE,
598};
599
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613
614
615static int __init centrino_init(void)
616{
617 struct cpuinfo_x86 *cpu = &cpu_data(0);
618
619 if (!cpu_has(cpu, X86_FEATURE_EST))
620 return -ENODEV;
621
622 return cpufreq_register_driver(¢rino_driver);
623}
624
625static void __exit centrino_exit(void)
626{
627 cpufreq_unregister_driver(¢rino_driver);
628}
629
630MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
631MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
632MODULE_LICENSE ("GPL");
633
634late_initcall(centrino_init);
635module_exit(centrino_exit);
636