1#include <linux/init.h>
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/thread_info.h>
9#include <linux/module.h>
10#include <linux/uaccess.h>
11
12#include <asm/processor.h>
13#include <asm/pgtable.h>
14#include <asm/msr.h>
15#include <asm/ds.h>
16#include <asm/bugs.h>
17#include <asm/cpu.h>
18
19#ifdef CONFIG_X86_64
20#include <linux/topology.h>
21#include <asm/numa_64.h>
22#endif
23
24#include "cpu.h"
25
26#ifdef CONFIG_X86_LOCAL_APIC
27#include <asm/mpspec.h>
28#include <asm/apic.h>
29#endif
30
31static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
32{
33
34 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
35 u64 misc_enable;
36
37 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
38
39 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
40 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
41 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
42 c->cpuid_level = cpuid_eax(0);
43 }
44 }
45
46 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
47 (c->x86 == 0x6 && c->x86_model >= 0x0e))
48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
49
50#ifdef CONFIG_X86_64
51 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
52#else
53
54 if (c->x86 == 15 && c->x86_cache_alignment == 64)
55 c->x86_cache_alignment = 128;
56#endif
57
58
59 if (c->x86 == 0xF && c->x86_model == 0x3
60 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
61 c->x86_phys_bits = 36;
62
63
64
65
66
67
68
69
70 if (c->x86_power & (1 << 8)) {
71 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
72 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
73 set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
74 sched_clock_stable = 1;
75 }
76
77
78
79
80
81
82
83
84
85
86
87 if (c->x86 == 6 && c->x86_model < 15)
88 clear_cpu_cap(c, X86_FEATURE_PAT);
89
90#ifdef CONFIG_KMEMCHECK
91
92
93
94
95
96
97
98
99 if (c->x86 == 15) {
100 u64 misc_enable;
101
102 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
103
104 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
105 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
106
107 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
108 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
109 }
110 }
111#endif
112}
113
114#ifdef CONFIG_X86_32
115
116
117
118
119
120
121int __cpuinit ppro_with_ram_bug(void)
122{
123
124 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
125 boot_cpu_data.x86 == 6 &&
126 boot_cpu_data.x86_model == 1 &&
127 boot_cpu_data.x86_mask < 8) {
128 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
129 return 1;
130 }
131 return 0;
132}
133
134#ifdef CONFIG_X86_F00F_BUG
135static void __cpuinit trap_init_f00f_bug(void)
136{
137 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
138
139
140
141
142
143 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
144 load_idt(&idt_descr);
145}
146#endif
147
148static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
149{
150#ifdef CONFIG_SMP
151
152 if (c->cpu_index == boot_cpu_id)
153 return;
154
155
156
157
158 if (c->x86 == 5 &&
159 c->x86_mask >= 1 && c->x86_mask <= 4 &&
160 c->x86_model <= 3) {
161
162
163
164 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
165 "with B stepping processors.\n");
166 }
167#endif
168}
169
170static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
171{
172 unsigned long lo, hi;
173
174#ifdef CONFIG_X86_F00F_BUG
175
176
177
178
179
180
181 c->f00f_bug = 0;
182 if (!paravirt_enabled() && c->x86 == 5) {
183 static int f00f_workaround_enabled;
184
185 c->f00f_bug = 1;
186 if (!f00f_workaround_enabled) {
187 trap_init_f00f_bug();
188 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
189 f00f_workaround_enabled = 1;
190 }
191 }
192#endif
193
194
195
196
197
198 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
199 clear_cpu_cap(c, X86_FEATURE_SEP);
200
201
202
203
204
205 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
206 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
207 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
208 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
209 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
210 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
211 wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
212 }
213 }
214
215
216
217
218
219
220
221 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
222 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
223 set_cpu_cap(c, X86_FEATURE_11AP);
224
225
226#ifdef CONFIG_X86_INTEL_USERCOPY
227
228
229
230 switch (c->x86) {
231 case 4:
232 break;
233 case 5:
234 break;
235 case 6:
236 movsl_mask.mask = 7;
237 break;
238 case 15:
239 movsl_mask.mask = 7;
240 break;
241 }
242#endif
243
244#ifdef CONFIG_X86_NUMAQ
245 numaq_tsc_disable();
246#endif
247
248 intel_smp_check(c);
249}
250#else
251static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
252{
253}
254#endif
255
256static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
257{
258#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
259 unsigned node;
260 int cpu = smp_processor_id();
261 int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
262
263
264
265 node = apicid_to_node[apicid];
266 if (node == NUMA_NO_NODE || !node_online(node))
267 node = first_node(node_online_map);
268 numa_set_node(cpu, node);
269
270 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
271#endif
272}
273
274
275
276
277static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
278{
279 unsigned int eax, ebx, ecx, edx;
280
281 if (c->cpuid_level < 4)
282 return 1;
283
284
285 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
286 if (eax & 0x1f)
287 return (eax >> 26) + 1;
288 else
289 return 1;
290}
291
292static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
293{
294
295#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
296#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
297#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
298#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
299#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
300#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
301
302 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
303
304 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
305 clear_cpu_cap(c, X86_FEATURE_VNMI);
306 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
307 clear_cpu_cap(c, X86_FEATURE_EPT);
308 clear_cpu_cap(c, X86_FEATURE_VPID);
309
310 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
311 msr_ctl = vmx_msr_high | vmx_msr_low;
312 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
313 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
314 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
315 set_cpu_cap(c, X86_FEATURE_VNMI);
316 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
317 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
318 vmx_msr_low, vmx_msr_high);
319 msr_ctl2 = vmx_msr_high | vmx_msr_low;
320 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
321 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
322 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
323 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
324 set_cpu_cap(c, X86_FEATURE_EPT);
325 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
326 set_cpu_cap(c, X86_FEATURE_VPID);
327 }
328}
329
330static void __cpuinit init_intel(struct cpuinfo_x86 *c)
331{
332 unsigned int l2 = 0;
333
334 early_init_intel(c);
335
336 intel_workarounds(c);
337
338
339
340
341
342
343 detect_extended_topology(c);
344
345 l2 = init_intel_cacheinfo(c);
346 if (c->cpuid_level > 9) {
347 unsigned eax = cpuid_eax(10);
348
349 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
350 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
351 }
352
353 if (c->cpuid_level > 6) {
354 unsigned ecx = cpuid_ecx(6);
355 if (ecx & 0x01)
356 set_cpu_cap(c, X86_FEATURE_APERFMPERF);
357 }
358
359 if (cpu_has_xmm2)
360 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
361 if (cpu_has_ds) {
362 unsigned int l1;
363 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
364 if (!(l1 & (1<<11)))
365 set_cpu_cap(c, X86_FEATURE_BTS);
366 if (!(l1 & (1<<12)))
367 set_cpu_cap(c, X86_FEATURE_PEBS);
368 ds_init_intel(c);
369 }
370
371 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
372 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
373
374#ifdef CONFIG_X86_64
375 if (c->x86 == 15)
376 c->x86_cache_alignment = c->x86_clflush_size * 2;
377 if (c->x86 == 6)
378 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
379#else
380
381
382
383
384
385 if (c->x86 == 6) {
386 char *p = NULL;
387
388 switch (c->x86_model) {
389 case 5:
390 if (c->x86_mask == 0) {
391 if (l2 == 0)
392 p = "Celeron (Covington)";
393 else if (l2 == 256)
394 p = "Mobile Pentium II (Dixon)";
395 }
396 break;
397
398 case 6:
399 if (l2 == 128)
400 p = "Celeron (Mendocino)";
401 else if (c->x86_mask == 0 || c->x86_mask == 5)
402 p = "Celeron-A";
403 break;
404
405 case 8:
406 if (l2 == 128)
407 p = "Celeron (Coppermine)";
408 break;
409 }
410
411 if (p)
412 strcpy(c->x86_model_id, p);
413 }
414
415 if (c->x86 == 15)
416 set_cpu_cap(c, X86_FEATURE_P4);
417 if (c->x86 == 6)
418 set_cpu_cap(c, X86_FEATURE_P3);
419#endif
420
421 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
422
423
424
425
426 c->x86_max_cores = intel_num_cpu_cores(c);
427#ifdef CONFIG_X86_32
428 detect_ht(c);
429#endif
430 }
431
432
433 srat_detect_node(c);
434
435 if (cpu_has(c, X86_FEATURE_VMX))
436 detect_vmx_virtcap(c);
437}
438
439#ifdef CONFIG_X86_32
440static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
441{
442
443
444
445
446
447
448 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
449 size = 256;
450 return size;
451}
452#endif
453
454static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
455 .c_vendor = "Intel",
456 .c_ident = { "GenuineIntel" },
457#ifdef CONFIG_X86_32
458 .c_models = {
459 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
460 {
461 [0] = "486 DX-25/33",
462 [1] = "486 DX-50",
463 [2] = "486 SX",
464 [3] = "486 DX/2",
465 [4] = "486 SL",
466 [5] = "486 SX/2",
467 [7] = "486 DX/2-WB",
468 [8] = "486 DX/4",
469 [9] = "486 DX/4-WB"
470 }
471 },
472 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
473 {
474 [0] = "Pentium 60/66 A-step",
475 [1] = "Pentium 60/66",
476 [2] = "Pentium 75 - 200",
477 [3] = "OverDrive PODP5V83",
478 [4] = "Pentium MMX",
479 [7] = "Mobile Pentium 75 - 200",
480 [8] = "Mobile Pentium MMX"
481 }
482 },
483 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
484 {
485 [0] = "Pentium Pro A-step",
486 [1] = "Pentium Pro",
487 [3] = "Pentium II (Klamath)",
488 [4] = "Pentium II (Deschutes)",
489 [5] = "Pentium II (Deschutes)",
490 [6] = "Mobile Pentium II",
491 [7] = "Pentium III (Katmai)",
492 [8] = "Pentium III (Coppermine)",
493 [10] = "Pentium III (Cascades)",
494 [11] = "Pentium III (Tualatin)",
495 }
496 },
497 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
498 {
499 [0] = "Pentium 4 (Unknown)",
500 [1] = "Pentium 4 (Willamette)",
501 [2] = "Pentium 4 (Northwood)",
502 [4] = "Pentium 4 (Foster)",
503 [5] = "Pentium 4 (Foster)",
504 }
505 },
506 },
507 .c_size_cache = intel_size_cache,
508#endif
509 .c_early_init = early_init_intel,
510 .c_init = init_intel,
511 .c_x86_vendor = X86_VENDOR_INTEL,
512};
513
514cpu_dev_register(intel_cpu_dev);
515
516