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9
10#include <linux/thread_info.h>
11#include <linux/capability.h>
12#include <linux/miscdevice.h>
13#include <linux/interrupt.h>
14#include <linux/ratelimit.h>
15#include <linux/kallsyms.h>
16#include <linux/rcupdate.h>
17#include <linux/kobject.h>
18#include <linux/uaccess.h>
19#include <linux/kdebug.h>
20#include <linux/kernel.h>
21#include <linux/percpu.h>
22#include <linux/string.h>
23#include <linux/sysdev.h>
24#include <linux/delay.h>
25#include <linux/ctype.h>
26#include <linux/sched.h>
27#include <linux/sysfs.h>
28#include <linux/types.h>
29#include <linux/init.h>
30#include <linux/kmod.h>
31#include <linux/poll.h>
32#include <linux/nmi.h>
33#include <linux/cpu.h>
34#include <linux/smp.h>
35#include <linux/fs.h>
36#include <linux/mm.h>
37#include <linux/debugfs.h>
38
39#include <asm/processor.h>
40#include <asm/hw_irq.h>
41#include <asm/apic.h>
42#include <asm/idle.h>
43#include <asm/ipi.h>
44#include <asm/mce.h>
45#include <asm/msr.h>
46
47#include "mce-internal.h"
48
49int mce_disabled __read_mostly;
50
51#define MISC_MCELOG_MINOR 227
52
53#define SPINUNIT 100
54
55atomic_t mce_entry;
56
57DEFINE_PER_CPU(unsigned, mce_exception_count);
58
59
60
61
62
63
64
65
66static int tolerant __read_mostly = 1;
67static int banks __read_mostly;
68static int rip_msr __read_mostly;
69static int mce_bootlog __read_mostly = -1;
70static int monarch_timeout __read_mostly = -1;
71static int mce_panic_timeout __read_mostly;
72static int mce_dont_log_ce __read_mostly;
73int mce_cmci_disabled __read_mostly;
74int mce_ignore_ce __read_mostly;
75int mce_ser __read_mostly;
76
77struct mce_bank *mce_banks __read_mostly;
78
79
80static unsigned long mce_need_notify;
81static char mce_helper[128];
82static char *mce_helper_argv[2] = { mce_helper, NULL };
83
84static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
85static DEFINE_PER_CPU(struct mce, mces_seen);
86static int cpu_missing;
87
88static void default_decode_mce(struct mce *m)
89{
90 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
91 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
92}
93
94
95
96
97
98void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce;
99EXPORT_SYMBOL(x86_mce_decode_callback);
100
101
102DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
103 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
104};
105
106static DEFINE_PER_CPU(struct work_struct, mce_work);
107
108
109void mce_setup(struct mce *m)
110{
111 memset(m, 0, sizeof(struct mce));
112 m->cpu = m->extcpu = smp_processor_id();
113 rdtscll(m->tsc);
114
115 m->time = get_seconds();
116 m->cpuvendor = boot_cpu_data.x86_vendor;
117 m->cpuid = cpuid_eax(1);
118#ifdef CONFIG_SMP
119 m->socketid = cpu_data(m->extcpu).phys_proc_id;
120#endif
121 m->apicid = cpu_data(m->extcpu).initial_apicid;
122 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
123}
124
125DEFINE_PER_CPU(struct mce, injectm);
126EXPORT_PER_CPU_SYMBOL_GPL(injectm);
127
128
129
130
131
132
133
134static struct mce_log mcelog = {
135 .signature = MCE_LOG_SIGNATURE,
136 .len = MCE_LOG_LEN,
137 .recordlen = sizeof(struct mce),
138};
139
140void mce_log(struct mce *mce)
141{
142 unsigned next, entry;
143
144 mce->finished = 0;
145 wmb();
146 for (;;) {
147 entry = rcu_dereference(mcelog.next);
148 for (;;) {
149
150
151
152
153
154 if (entry >= MCE_LOG_LEN) {
155 set_bit(MCE_OVERFLOW,
156 (unsigned long *)&mcelog.flags);
157 return;
158 }
159
160 if (mcelog.entry[entry].finished) {
161 entry++;
162 continue;
163 }
164 break;
165 }
166 smp_rmb();
167 next = entry + 1;
168 if (cmpxchg(&mcelog.next, entry, next) == entry)
169 break;
170 }
171 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
172 wmb();
173 mcelog.entry[entry].finished = 1;
174 wmb();
175
176 mce->finished = 1;
177 set_bit(0, &mce_need_notify);
178}
179
180static void print_mce(struct mce *m)
181{
182 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
183 m->extcpu, m->mcgstatus, m->bank, m->status);
184
185 if (m->ip) {
186 pr_emerg("RIP%s %02x:<%016Lx> ",
187 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
188 m->cs, m->ip);
189
190 if (m->cs == __KERNEL_CS)
191 print_symbol("{%s}", m->ip);
192 pr_cont("\n");
193 }
194
195 pr_emerg("TSC %llx ", m->tsc);
196 if (m->addr)
197 pr_cont("ADDR %llx ", m->addr);
198 if (m->misc)
199 pr_cont("MISC %llx ", m->misc);
200
201 pr_cont("\n");
202 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
203 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
204
205
206
207
208
209 x86_mce_decode_callback(m);
210}
211
212static void print_mce_head(void)
213{
214 pr_emerg("\nHARDWARE ERROR\n");
215}
216
217static void print_mce_tail(void)
218{
219 pr_emerg("This is not a software problem!\n");
220}
221
222#define PANIC_TIMEOUT 5
223
224static atomic_t mce_paniced;
225
226static int fake_panic;
227static atomic_t mce_fake_paniced;
228
229
230static void wait_for_panic(void)
231{
232 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
233
234 preempt_disable();
235 local_irq_enable();
236 while (timeout-- > 0)
237 udelay(1);
238 if (panic_timeout == 0)
239 panic_timeout = mce_panic_timeout;
240 panic("Panicing machine check CPU died");
241}
242
243static void mce_panic(char *msg, struct mce *final, char *exp)
244{
245 int i;
246
247 if (!fake_panic) {
248
249
250
251 if (atomic_inc_return(&mce_paniced) > 1)
252 wait_for_panic();
253 barrier();
254
255 bust_spinlocks(1);
256 console_verbose();
257 } else {
258
259 if (atomic_inc_return(&mce_fake_paniced) > 1)
260 return;
261 }
262 print_mce_head();
263
264 for (i = 0; i < MCE_LOG_LEN; i++) {
265 struct mce *m = &mcelog.entry[i];
266 if (!(m->status & MCI_STATUS_VAL))
267 continue;
268 if (!(m->status & MCI_STATUS_UC))
269 print_mce(m);
270 }
271
272 for (i = 0; i < MCE_LOG_LEN; i++) {
273 struct mce *m = &mcelog.entry[i];
274 if (!(m->status & MCI_STATUS_VAL))
275 continue;
276 if (!(m->status & MCI_STATUS_UC))
277 continue;
278 if (!final || memcmp(m, final, sizeof(struct mce)))
279 print_mce(m);
280 }
281 if (final)
282 print_mce(final);
283 if (cpu_missing)
284 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
285 print_mce_tail();
286 if (exp)
287 printk(KERN_EMERG "Machine check: %s\n", exp);
288 if (!fake_panic) {
289 if (panic_timeout == 0)
290 panic_timeout = mce_panic_timeout;
291 panic(msg);
292 } else
293 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
294}
295
296
297
298static int msr_to_offset(u32 msr)
299{
300 unsigned bank = __get_cpu_var(injectm.bank);
301
302 if (msr == rip_msr)
303 return offsetof(struct mce, ip);
304 if (msr == MSR_IA32_MCx_STATUS(bank))
305 return offsetof(struct mce, status);
306 if (msr == MSR_IA32_MCx_ADDR(bank))
307 return offsetof(struct mce, addr);
308 if (msr == MSR_IA32_MCx_MISC(bank))
309 return offsetof(struct mce, misc);
310 if (msr == MSR_IA32_MCG_STATUS)
311 return offsetof(struct mce, mcgstatus);
312 return -1;
313}
314
315
316static u64 mce_rdmsrl(u32 msr)
317{
318 u64 v;
319
320 if (__get_cpu_var(injectm).finished) {
321 int offset = msr_to_offset(msr);
322
323 if (offset < 0)
324 return 0;
325 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
326 }
327
328 if (rdmsrl_safe(msr, &v)) {
329 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
330
331
332
333
334
335 v = 0;
336 }
337
338 return v;
339}
340
341static void mce_wrmsrl(u32 msr, u64 v)
342{
343 if (__get_cpu_var(injectm).finished) {
344 int offset = msr_to_offset(msr);
345
346 if (offset >= 0)
347 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
348 return;
349 }
350 wrmsrl(msr, v);
351}
352
353
354
355
356
357
358#define MCE_RING_SIZE 16
359
360struct mce_ring {
361 unsigned short start;
362 unsigned short end;
363 unsigned long ring[MCE_RING_SIZE];
364};
365static DEFINE_PER_CPU(struct mce_ring, mce_ring);
366
367
368static int mce_ring_empty(void)
369{
370 struct mce_ring *r = &__get_cpu_var(mce_ring);
371
372 return r->start == r->end;
373}
374
375static int mce_ring_get(unsigned long *pfn)
376{
377 struct mce_ring *r;
378 int ret = 0;
379
380 *pfn = 0;
381 get_cpu();
382 r = &__get_cpu_var(mce_ring);
383 if (r->start == r->end)
384 goto out;
385 *pfn = r->ring[r->start];
386 r->start = (r->start + 1) % MCE_RING_SIZE;
387 ret = 1;
388out:
389 put_cpu();
390 return ret;
391}
392
393
394static int mce_ring_add(unsigned long pfn)
395{
396 struct mce_ring *r = &__get_cpu_var(mce_ring);
397 unsigned next;
398
399 next = (r->end + 1) % MCE_RING_SIZE;
400 if (next == r->start)
401 return -1;
402 r->ring[r->end] = pfn;
403 wmb();
404 r->end = next;
405 return 0;
406}
407
408int mce_available(struct cpuinfo_x86 *c)
409{
410 if (mce_disabled)
411 return 0;
412 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
413}
414
415static void mce_schedule_work(void)
416{
417 if (!mce_ring_empty()) {
418 struct work_struct *work = &__get_cpu_var(mce_work);
419 if (!work_pending(work))
420 schedule_work(work);
421 }
422}
423
424
425
426
427
428static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
429{
430
431 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
432 m->ip = regs->ip;
433 m->cs = regs->cs;
434 } else {
435 m->ip = 0;
436 m->cs = 0;
437 }
438 if (rip_msr)
439 m->ip = mce_rdmsrl(rip_msr);
440}
441
442#ifdef CONFIG_X86_LOCAL_APIC
443
444
445
446
447
448asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
449{
450 ack_APIC_irq();
451 exit_idle();
452 irq_enter();
453 mce_notify_irq();
454 mce_schedule_work();
455 irq_exit();
456}
457#endif
458
459static void mce_report_event(struct pt_regs *regs)
460{
461 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
462 mce_notify_irq();
463
464
465
466
467
468
469 mce_schedule_work();
470 return;
471 }
472
473#ifdef CONFIG_X86_LOCAL_APIC
474
475
476
477
478 if (!cpu_has_apic)
479 return;
480
481
482
483
484
485
486
487 apic->send_IPI_self(MCE_SELF_VECTOR);
488
489
490
491
492
493
494 apic_wait_icr_idle();
495#endif
496}
497
498DEFINE_PER_CPU(unsigned, mce_poll_count);
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
516{
517 struct mce m;
518 int i;
519
520 __get_cpu_var(mce_poll_count)++;
521
522 mce_setup(&m);
523
524 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
525 for (i = 0; i < banks; i++) {
526 if (!mce_banks[i].ctl || !test_bit(i, *b))
527 continue;
528
529 m.misc = 0;
530 m.addr = 0;
531 m.bank = i;
532 m.tsc = 0;
533
534 barrier();
535 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
536 if (!(m.status & MCI_STATUS_VAL))
537 continue;
538
539
540
541
542
543
544
545 if (!(flags & MCP_UC) &&
546 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
547 continue;
548
549 if (m.status & MCI_STATUS_MISCV)
550 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
551 if (m.status & MCI_STATUS_ADDRV)
552 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
553
554 if (!(flags & MCP_TIMESTAMP))
555 m.tsc = 0;
556
557
558
559
560 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
561 mce_log(&m);
562 add_taint(TAINT_MACHINE_CHECK);
563 }
564
565
566
567
568 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
569 }
570
571
572
573
574
575
576 sync_core();
577}
578EXPORT_SYMBOL_GPL(machine_check_poll);
579
580
581
582
583
584static int mce_no_way_out(struct mce *m, char **msg)
585{
586 int i;
587
588 for (i = 0; i < banks; i++) {
589 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
590 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
591 return 1;
592 }
593 return 0;
594}
595
596
597
598
599
600static atomic_t mce_executing;
601
602
603
604
605static atomic_t mce_callin;
606
607
608
609
610static int mce_timed_out(u64 *t)
611{
612
613
614
615
616
617
618 rmb();
619 if (atomic_read(&mce_paniced))
620 wait_for_panic();
621 if (!monarch_timeout)
622 goto out;
623 if ((s64)*t < SPINUNIT) {
624
625 if (tolerant < 1)
626 mce_panic("Timeout synchronizing machine check over CPUs",
627 NULL, NULL);
628 cpu_missing = 1;
629 return 1;
630 }
631 *t -= SPINUNIT;
632out:
633 touch_nmi_watchdog();
634 return 0;
635}
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661static void mce_reign(void)
662{
663 int cpu;
664 struct mce *m = NULL;
665 int global_worst = 0;
666 char *msg = NULL;
667 char *nmsg = NULL;
668
669
670
671
672
673
674 for_each_possible_cpu(cpu) {
675 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
676 &nmsg);
677 if (severity > global_worst) {
678 msg = nmsg;
679 global_worst = severity;
680 m = &per_cpu(mces_seen, cpu);
681 }
682 }
683
684
685
686
687
688
689 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
690 mce_panic("Fatal Machine check", m, msg);
691
692
693
694
695
696
697
698
699
700
701
702 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
703 mce_panic("Machine check from unknown source", NULL, NULL);
704
705
706
707
708
709 for_each_possible_cpu(cpu)
710 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
711}
712
713static atomic_t global_nwo;
714
715
716
717
718
719
720
721
722static int mce_start(int *no_way_out)
723{
724 int order;
725 int cpus = num_online_cpus();
726 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
727
728 if (!timeout)
729 return -1;
730
731 atomic_add(*no_way_out, &global_nwo);
732
733
734
735 smp_wmb();
736 order = atomic_inc_return(&mce_callin);
737
738
739
740
741 while (atomic_read(&mce_callin) != cpus) {
742 if (mce_timed_out(&timeout)) {
743 atomic_set(&global_nwo, 0);
744 return -1;
745 }
746 ndelay(SPINUNIT);
747 }
748
749
750
751
752 smp_rmb();
753
754 if (order == 1) {
755
756
757
758 atomic_set(&mce_executing, 1);
759 } else {
760
761
762
763
764
765
766 while (atomic_read(&mce_executing) < order) {
767 if (mce_timed_out(&timeout)) {
768 atomic_set(&global_nwo, 0);
769 return -1;
770 }
771 ndelay(SPINUNIT);
772 }
773 }
774
775
776
777
778 *no_way_out = atomic_read(&global_nwo);
779
780 return order;
781}
782
783
784
785
786
787static int mce_end(int order)
788{
789 int ret = -1;
790 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
791
792 if (!timeout)
793 goto reset;
794 if (order < 0)
795 goto reset;
796
797
798
799
800 atomic_inc(&mce_executing);
801
802 if (order == 1) {
803
804 int cpus = num_online_cpus();
805
806
807
808
809
810 while (atomic_read(&mce_executing) <= cpus) {
811 if (mce_timed_out(&timeout))
812 goto reset;
813 ndelay(SPINUNIT);
814 }
815
816 mce_reign();
817 barrier();
818 ret = 0;
819 } else {
820
821
822
823 while (atomic_read(&mce_executing) != 0) {
824 if (mce_timed_out(&timeout))
825 goto reset;
826 ndelay(SPINUNIT);
827 }
828
829
830
831
832 return 0;
833 }
834
835
836
837
838reset:
839 atomic_set(&global_nwo, 0);
840 atomic_set(&mce_callin, 0);
841 barrier();
842
843
844
845
846 atomic_set(&mce_executing, 0);
847 return ret;
848}
849
850
851
852
853
854
855
856static int mce_usable_address(struct mce *m)
857{
858 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
859 return 0;
860 if ((m->misc & 0x3f) > PAGE_SHIFT)
861 return 0;
862 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
863 return 0;
864 return 1;
865}
866
867static void mce_clear_state(unsigned long *toclear)
868{
869 int i;
870
871 for (i = 0; i < banks; i++) {
872 if (test_bit(i, toclear))
873 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
874 }
875}
876
877
878
879
880
881
882
883
884
885
886
887
888
889void do_machine_check(struct pt_regs *regs, long error_code)
890{
891 struct mce m, *final;
892 int i;
893 int worst = 0;
894 int severity;
895
896
897
898
899 int order;
900
901
902
903
904 int no_way_out = 0;
905
906
907
908
909 int kill_it = 0;
910 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
911 char *msg = "Unknown";
912
913 atomic_inc(&mce_entry);
914
915 __get_cpu_var(mce_exception_count)++;
916
917 if (notify_die(DIE_NMI, "machine check", regs, error_code,
918 18, SIGKILL) == NOTIFY_STOP)
919 goto out;
920 if (!banks)
921 goto out;
922
923 mce_setup(&m);
924
925 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
926 final = &__get_cpu_var(mces_seen);
927 *final = m;
928
929 no_way_out = mce_no_way_out(&m, &msg);
930
931 barrier();
932
933
934
935
936 if (!(m.mcgstatus & MCG_STATUS_RIPV))
937 kill_it = 1;
938
939
940
941
942
943
944 order = mce_start(&no_way_out);
945 for (i = 0; i < banks; i++) {
946 __clear_bit(i, toclear);
947 if (!mce_banks[i].ctl)
948 continue;
949
950 m.misc = 0;
951 m.addr = 0;
952 m.bank = i;
953
954 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
955 if ((m.status & MCI_STATUS_VAL) == 0)
956 continue;
957
958
959
960
961
962 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
963 !no_way_out)
964 continue;
965
966
967
968
969 add_taint(TAINT_MACHINE_CHECK);
970
971 severity = mce_severity(&m, tolerant, NULL);
972
973
974
975
976
977 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
978 continue;
979 __set_bit(i, toclear);
980 if (severity == MCE_NO_SEVERITY) {
981
982
983
984
985 continue;
986 }
987
988
989
990
991 if (severity == MCE_AR_SEVERITY)
992 kill_it = 1;
993
994 if (m.status & MCI_STATUS_MISCV)
995 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
996 if (m.status & MCI_STATUS_ADDRV)
997 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
998
999
1000
1001
1002
1003
1004
1005
1006 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1007 mce_ring_add(m.addr >> PAGE_SHIFT);
1008
1009 mce_get_rip(&m, regs);
1010 mce_log(&m);
1011
1012 if (severity > worst) {
1013 *final = m;
1014 worst = severity;
1015 }
1016 }
1017
1018 if (!no_way_out)
1019 mce_clear_state(toclear);
1020
1021
1022
1023
1024
1025 if (mce_end(order) < 0)
1026 no_way_out = worst >= MCE_PANIC_SEVERITY;
1027
1028
1029
1030
1031
1032
1033
1034
1035 if (no_way_out && tolerant < 3)
1036 mce_panic("Fatal machine check on current CPU", final, msg);
1037
1038
1039
1040
1041
1042
1043
1044
1045 if (kill_it && tolerant < 3)
1046 force_sig(SIGBUS, current);
1047
1048
1049 set_thread_flag(TIF_MCE_NOTIFY);
1050
1051 if (worst > 0)
1052 mce_report_event(regs);
1053 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1054out:
1055 atomic_dec(&mce_entry);
1056 sync_core();
1057}
1058EXPORT_SYMBOL_GPL(do_machine_check);
1059
1060
1061void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1062{
1063 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1064}
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077void mce_notify_process(void)
1078{
1079 unsigned long pfn;
1080 mce_notify_irq();
1081 while (mce_ring_get(&pfn))
1082 memory_failure(pfn, MCE_VECTOR);
1083}
1084
1085static void mce_process_work(struct work_struct *dummy)
1086{
1087 mce_notify_process();
1088}
1089
1090#ifdef CONFIG_X86_MCE_INTEL
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104void mce_log_therm_throt_event(__u64 status)
1105{
1106 struct mce m;
1107
1108 mce_setup(&m);
1109 m.bank = MCE_THERMAL_BANK;
1110 m.status = status;
1111 mce_log(&m);
1112}
1113#endif
1114
1115
1116
1117
1118
1119
1120static int check_interval = 5 * 60;
1121
1122static DEFINE_PER_CPU(int, mce_next_interval);
1123static DEFINE_PER_CPU(struct timer_list, mce_timer);
1124
1125static void mcheck_timer(unsigned long data)
1126{
1127 struct timer_list *t = &per_cpu(mce_timer, data);
1128 int *n;
1129
1130 WARN_ON(smp_processor_id() != data);
1131
1132 if (mce_available(¤t_cpu_data)) {
1133 machine_check_poll(MCP_TIMESTAMP,
1134 &__get_cpu_var(mce_poll_banks));
1135 }
1136
1137
1138
1139
1140
1141 n = &__get_cpu_var(mce_next_interval);
1142 if (mce_notify_irq())
1143 *n = max(*n/2, HZ/100);
1144 else
1145 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1146
1147 t->expires = jiffies + *n;
1148 add_timer_on(t, smp_processor_id());
1149}
1150
1151static void mce_do_trigger(struct work_struct *work)
1152{
1153 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1154}
1155
1156static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1157
1158
1159
1160
1161
1162
1163int mce_notify_irq(void)
1164{
1165
1166 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1167
1168 clear_thread_flag(TIF_MCE_NOTIFY);
1169
1170 if (test_and_clear_bit(0, &mce_need_notify)) {
1171 wake_up_interruptible(&mce_wait);
1172
1173
1174
1175
1176
1177
1178 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1179 schedule_work(&mce_trigger_work);
1180
1181 if (__ratelimit(&ratelimit))
1182 printk(KERN_INFO "Machine check events logged\n");
1183
1184 return 1;
1185 }
1186 return 0;
1187}
1188EXPORT_SYMBOL_GPL(mce_notify_irq);
1189
1190static int mce_banks_init(void)
1191{
1192 int i;
1193
1194 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1195 if (!mce_banks)
1196 return -ENOMEM;
1197 for (i = 0; i < banks; i++) {
1198 struct mce_bank *b = &mce_banks[i];
1199
1200 b->ctl = -1ULL;
1201 b->init = 1;
1202 }
1203 return 0;
1204}
1205
1206
1207
1208
1209static int __cpuinit mce_cap_init(void)
1210{
1211 unsigned b;
1212 u64 cap;
1213
1214 rdmsrl(MSR_IA32_MCG_CAP, cap);
1215
1216 b = cap & MCG_BANKCNT_MASK;
1217 if (!banks)
1218 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1219
1220 if (b > MAX_NR_BANKS) {
1221 printk(KERN_WARNING
1222 "MCE: Using only %u machine check banks out of %u\n",
1223 MAX_NR_BANKS, b);
1224 b = MAX_NR_BANKS;
1225 }
1226
1227
1228 WARN_ON(banks != 0 && b != banks);
1229 banks = b;
1230 if (!mce_banks) {
1231 int err = mce_banks_init();
1232
1233 if (err)
1234 return err;
1235 }
1236
1237
1238 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1239 rip_msr = MSR_IA32_MCG_EIP;
1240
1241 if (cap & MCG_SER_P)
1242 mce_ser = 1;
1243
1244 return 0;
1245}
1246
1247static void mce_init(void)
1248{
1249 mce_banks_t all_banks;
1250 u64 cap;
1251 int i;
1252
1253
1254
1255
1256 bitmap_fill(all_banks, MAX_NR_BANKS);
1257 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1258
1259 set_in_cr4(X86_CR4_MCE);
1260
1261 rdmsrl(MSR_IA32_MCG_CAP, cap);
1262 if (cap & MCG_CTL_P)
1263 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1264
1265 for (i = 0; i < banks; i++) {
1266 struct mce_bank *b = &mce_banks[i];
1267
1268 if (!b->init)
1269 continue;
1270 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1271 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1272 }
1273}
1274
1275
1276static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
1277{
1278 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1279 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1280 return -EOPNOTSUPP;
1281 }
1282
1283
1284 if (c->x86_vendor == X86_VENDOR_AMD) {
1285 if (c->x86 == 15 && banks > 4) {
1286
1287
1288
1289
1290
1291 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1292 }
1293 if (c->x86 <= 17 && mce_bootlog < 0) {
1294
1295
1296
1297
1298 mce_bootlog = 0;
1299 }
1300
1301
1302
1303
1304 if (c->x86 == 6 && banks > 0)
1305 mce_banks[0].ctl = 0;
1306 }
1307
1308 if (c->x86_vendor == X86_VENDOR_INTEL) {
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1319 mce_banks[0].init = 0;
1320
1321
1322
1323
1324
1325 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1326 monarch_timeout < 0)
1327 monarch_timeout = USEC_PER_SEC;
1328
1329
1330
1331
1332
1333 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1334 mce_bootlog = 0;
1335 }
1336 if (monarch_timeout < 0)
1337 monarch_timeout = 0;
1338 if (mce_bootlog != 0)
1339 mce_panic_timeout = 30;
1340
1341 return 0;
1342}
1343
1344static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1345{
1346 if (c->x86 != 5)
1347 return;
1348 switch (c->x86_vendor) {
1349 case X86_VENDOR_INTEL:
1350 intel_p5_mcheck_init(c);
1351 break;
1352 case X86_VENDOR_CENTAUR:
1353 winchip_mcheck_init(c);
1354 break;
1355 }
1356}
1357
1358static void mce_cpu_features(struct cpuinfo_x86 *c)
1359{
1360 switch (c->x86_vendor) {
1361 case X86_VENDOR_INTEL:
1362 mce_intel_feature_init(c);
1363 break;
1364 case X86_VENDOR_AMD:
1365 mce_amd_feature_init(c);
1366 break;
1367 default:
1368 break;
1369 }
1370}
1371
1372static void mce_init_timer(void)
1373{
1374 struct timer_list *t = &__get_cpu_var(mce_timer);
1375 int *n = &__get_cpu_var(mce_next_interval);
1376
1377 if (mce_ignore_ce)
1378 return;
1379
1380 *n = check_interval * HZ;
1381 if (!*n)
1382 return;
1383 setup_timer(t, mcheck_timer, smp_processor_id());
1384 t->expires = round_jiffies(jiffies + *n);
1385 add_timer_on(t, smp_processor_id());
1386}
1387
1388
1389static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1390{
1391 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1392 smp_processor_id());
1393}
1394
1395
1396void (*machine_check_vector)(struct pt_regs *, long error_code) =
1397 unexpected_machine_check;
1398
1399
1400
1401
1402
1403void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1404{
1405 if (mce_disabled)
1406 return;
1407
1408 mce_ancient_init(c);
1409
1410 if (!mce_available(c))
1411 return;
1412
1413 if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
1414 mce_disabled = 1;
1415 return;
1416 }
1417
1418 machine_check_vector = do_machine_check;
1419
1420 mce_init();
1421 mce_cpu_features(c);
1422 mce_init_timer();
1423 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1424}
1425
1426
1427
1428
1429
1430static DEFINE_SPINLOCK(mce_state_lock);
1431static int open_count;
1432static int open_exclu;
1433
1434static int mce_open(struct inode *inode, struct file *file)
1435{
1436 spin_lock(&mce_state_lock);
1437
1438 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1439 spin_unlock(&mce_state_lock);
1440
1441 return -EBUSY;
1442 }
1443
1444 if (file->f_flags & O_EXCL)
1445 open_exclu = 1;
1446 open_count++;
1447
1448 spin_unlock(&mce_state_lock);
1449
1450 return nonseekable_open(inode, file);
1451}
1452
1453static int mce_release(struct inode *inode, struct file *file)
1454{
1455 spin_lock(&mce_state_lock);
1456
1457 open_count--;
1458 open_exclu = 0;
1459
1460 spin_unlock(&mce_state_lock);
1461
1462 return 0;
1463}
1464
1465static void collect_tscs(void *data)
1466{
1467 unsigned long *cpu_tsc = (unsigned long *)data;
1468
1469 rdtscll(cpu_tsc[smp_processor_id()]);
1470}
1471
1472static DEFINE_MUTEX(mce_read_mutex);
1473
1474static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1475 loff_t *off)
1476{
1477 char __user *buf = ubuf;
1478 unsigned long *cpu_tsc;
1479 unsigned prev, next;
1480 int i, err;
1481
1482 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1483 if (!cpu_tsc)
1484 return -ENOMEM;
1485
1486 mutex_lock(&mce_read_mutex);
1487 next = rcu_dereference(mcelog.next);
1488
1489
1490 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1491 mutex_unlock(&mce_read_mutex);
1492 kfree(cpu_tsc);
1493
1494 return -EINVAL;
1495 }
1496
1497 err = 0;
1498 prev = 0;
1499 do {
1500 for (i = prev; i < next; i++) {
1501 unsigned long start = jiffies;
1502
1503 while (!mcelog.entry[i].finished) {
1504 if (time_after_eq(jiffies, start + 2)) {
1505 memset(mcelog.entry + i, 0,
1506 sizeof(struct mce));
1507 goto timeout;
1508 }
1509 cpu_relax();
1510 }
1511 smp_rmb();
1512 err |= copy_to_user(buf, mcelog.entry + i,
1513 sizeof(struct mce));
1514 buf += sizeof(struct mce);
1515timeout:
1516 ;
1517 }
1518
1519 memset(mcelog.entry + prev, 0,
1520 (next - prev) * sizeof(struct mce));
1521 prev = next;
1522 next = cmpxchg(&mcelog.next, prev, 0);
1523 } while (next != prev);
1524
1525 synchronize_sched();
1526
1527
1528
1529
1530
1531 on_each_cpu(collect_tscs, cpu_tsc, 1);
1532
1533 for (i = next; i < MCE_LOG_LEN; i++) {
1534 if (mcelog.entry[i].finished &&
1535 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1536 err |= copy_to_user(buf, mcelog.entry+i,
1537 sizeof(struct mce));
1538 smp_rmb();
1539 buf += sizeof(struct mce);
1540 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1541 }
1542 }
1543 mutex_unlock(&mce_read_mutex);
1544 kfree(cpu_tsc);
1545
1546 return err ? -EFAULT : buf - ubuf;
1547}
1548
1549static unsigned int mce_poll(struct file *file, poll_table *wait)
1550{
1551 poll_wait(file, &mce_wait, wait);
1552 if (rcu_dereference(mcelog.next))
1553 return POLLIN | POLLRDNORM;
1554 return 0;
1555}
1556
1557static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1558{
1559 int __user *p = (int __user *)arg;
1560
1561 if (!capable(CAP_SYS_ADMIN))
1562 return -EPERM;
1563
1564 switch (cmd) {
1565 case MCE_GET_RECORD_LEN:
1566 return put_user(sizeof(struct mce), p);
1567 case MCE_GET_LOG_LEN:
1568 return put_user(MCE_LOG_LEN, p);
1569 case MCE_GETCLEAR_FLAGS: {
1570 unsigned flags;
1571
1572 do {
1573 flags = mcelog.flags;
1574 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1575
1576 return put_user(flags, p);
1577 }
1578 default:
1579 return -ENOTTY;
1580 }
1581}
1582
1583
1584struct file_operations mce_chrdev_ops = {
1585 .open = mce_open,
1586 .release = mce_release,
1587 .read = mce_read,
1588 .poll = mce_poll,
1589 .unlocked_ioctl = mce_ioctl,
1590};
1591EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1592
1593static struct miscdevice mce_log_device = {
1594 MISC_MCELOG_MINOR,
1595 "mcelog",
1596 &mce_chrdev_ops,
1597};
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610static int __init mcheck_enable(char *str)
1611{
1612 if (*str == 0) {
1613 enable_p5_mce();
1614 return 1;
1615 }
1616 if (*str == '=')
1617 str++;
1618 if (!strcmp(str, "off"))
1619 mce_disabled = 1;
1620 else if (!strcmp(str, "no_cmci"))
1621 mce_cmci_disabled = 1;
1622 else if (!strcmp(str, "dont_log_ce"))
1623 mce_dont_log_ce = 1;
1624 else if (!strcmp(str, "ignore_ce"))
1625 mce_ignore_ce = 1;
1626 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1627 mce_bootlog = (str[0] == 'b');
1628 else if (isdigit(str[0])) {
1629 get_option(&str, &tolerant);
1630 if (*str == ',') {
1631 ++str;
1632 get_option(&str, &monarch_timeout);
1633 }
1634 } else {
1635 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1636 str);
1637 return 0;
1638 }
1639 return 1;
1640}
1641__setup("mce", mcheck_enable);
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651static int mce_disable(void)
1652{
1653 int i;
1654
1655 for (i = 0; i < banks; i++) {
1656 struct mce_bank *b = &mce_banks[i];
1657
1658 if (b->init)
1659 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1660 }
1661 return 0;
1662}
1663
1664static int mce_suspend(struct sys_device *dev, pm_message_t state)
1665{
1666 return mce_disable();
1667}
1668
1669static int mce_shutdown(struct sys_device *dev)
1670{
1671 return mce_disable();
1672}
1673
1674
1675
1676
1677
1678
1679static int mce_resume(struct sys_device *dev)
1680{
1681 mce_init();
1682 mce_cpu_features(¤t_cpu_data);
1683
1684 return 0;
1685}
1686
1687static void mce_cpu_restart(void *data)
1688{
1689 del_timer_sync(&__get_cpu_var(mce_timer));
1690 if (!mce_available(¤t_cpu_data))
1691 return;
1692 mce_init();
1693 mce_init_timer();
1694}
1695
1696
1697static void mce_restart(void)
1698{
1699 on_each_cpu(mce_cpu_restart, NULL, 1);
1700}
1701
1702
1703static void mce_disable_ce(void *all)
1704{
1705 if (!mce_available(¤t_cpu_data))
1706 return;
1707 if (all)
1708 del_timer_sync(&__get_cpu_var(mce_timer));
1709 cmci_clear();
1710}
1711
1712static void mce_enable_ce(void *all)
1713{
1714 if (!mce_available(¤t_cpu_data))
1715 return;
1716 cmci_reenable();
1717 cmci_recheck();
1718 if (all)
1719 mce_init_timer();
1720}
1721
1722static struct sysdev_class mce_sysclass = {
1723 .suspend = mce_suspend,
1724 .shutdown = mce_shutdown,
1725 .resume = mce_resume,
1726 .name = "machinecheck",
1727};
1728
1729DEFINE_PER_CPU(struct sys_device, mce_dev);
1730
1731__cpuinitdata
1732void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1733
1734static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1735{
1736 return container_of(attr, struct mce_bank, attr);
1737}
1738
1739static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1740 char *buf)
1741{
1742 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1743}
1744
1745static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1746 const char *buf, size_t size)
1747{
1748 u64 new;
1749
1750 if (strict_strtoull(buf, 0, &new) < 0)
1751 return -EINVAL;
1752
1753 attr_to_bank(attr)->ctl = new;
1754 mce_restart();
1755
1756 return size;
1757}
1758
1759static ssize_t
1760show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1761{
1762 strcpy(buf, mce_helper);
1763 strcat(buf, "\n");
1764 return strlen(mce_helper) + 1;
1765}
1766
1767static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1768 const char *buf, size_t siz)
1769{
1770 char *p;
1771
1772 strncpy(mce_helper, buf, sizeof(mce_helper));
1773 mce_helper[sizeof(mce_helper)-1] = 0;
1774 p = strchr(mce_helper, '\n');
1775
1776 if (p)
1777 *p = 0;
1778
1779 return strlen(mce_helper) + !!p;
1780}
1781
1782static ssize_t set_ignore_ce(struct sys_device *s,
1783 struct sysdev_attribute *attr,
1784 const char *buf, size_t size)
1785{
1786 u64 new;
1787
1788 if (strict_strtoull(buf, 0, &new) < 0)
1789 return -EINVAL;
1790
1791 if (mce_ignore_ce ^ !!new) {
1792 if (new) {
1793
1794 on_each_cpu(mce_disable_ce, (void *)1, 1);
1795 mce_ignore_ce = 1;
1796 } else {
1797
1798 mce_ignore_ce = 0;
1799 on_each_cpu(mce_enable_ce, (void *)1, 1);
1800 }
1801 }
1802 return size;
1803}
1804
1805static ssize_t set_cmci_disabled(struct sys_device *s,
1806 struct sysdev_attribute *attr,
1807 const char *buf, size_t size)
1808{
1809 u64 new;
1810
1811 if (strict_strtoull(buf, 0, &new) < 0)
1812 return -EINVAL;
1813
1814 if (mce_cmci_disabled ^ !!new) {
1815 if (new) {
1816
1817 on_each_cpu(mce_disable_ce, NULL, 1);
1818 mce_cmci_disabled = 1;
1819 } else {
1820
1821 mce_cmci_disabled = 0;
1822 on_each_cpu(mce_enable_ce, NULL, 1);
1823 }
1824 }
1825 return size;
1826}
1827
1828static ssize_t store_int_with_restart(struct sys_device *s,
1829 struct sysdev_attribute *attr,
1830 const char *buf, size_t size)
1831{
1832 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1833 mce_restart();
1834 return ret;
1835}
1836
1837static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1838static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1839static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1840static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1841
1842static struct sysdev_ext_attribute attr_check_interval = {
1843 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1844 store_int_with_restart),
1845 &check_interval
1846};
1847
1848static struct sysdev_ext_attribute attr_ignore_ce = {
1849 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1850 &mce_ignore_ce
1851};
1852
1853static struct sysdev_ext_attribute attr_cmci_disabled = {
1854 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1855 &mce_cmci_disabled
1856};
1857
1858static struct sysdev_attribute *mce_attrs[] = {
1859 &attr_tolerant.attr,
1860 &attr_check_interval.attr,
1861 &attr_trigger,
1862 &attr_monarch_timeout.attr,
1863 &attr_dont_log_ce.attr,
1864 &attr_ignore_ce.attr,
1865 &attr_cmci_disabled.attr,
1866 NULL
1867};
1868
1869static cpumask_var_t mce_dev_initialized;
1870
1871
1872static __cpuinit int mce_create_device(unsigned int cpu)
1873{
1874 int err;
1875 int i, j;
1876
1877 if (!mce_available(&boot_cpu_data))
1878 return -EIO;
1879
1880 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1881 per_cpu(mce_dev, cpu).id = cpu;
1882 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1883
1884 err = sysdev_register(&per_cpu(mce_dev, cpu));
1885 if (err)
1886 return err;
1887
1888 for (i = 0; mce_attrs[i]; i++) {
1889 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1890 if (err)
1891 goto error;
1892 }
1893 for (j = 0; j < banks; j++) {
1894 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1895 &mce_banks[j].attr);
1896 if (err)
1897 goto error2;
1898 }
1899 cpumask_set_cpu(cpu, mce_dev_initialized);
1900
1901 return 0;
1902error2:
1903 while (--j >= 0)
1904 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1905error:
1906 while (--i >= 0)
1907 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1908
1909 sysdev_unregister(&per_cpu(mce_dev, cpu));
1910
1911 return err;
1912}
1913
1914static __cpuinit void mce_remove_device(unsigned int cpu)
1915{
1916 int i;
1917
1918 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1919 return;
1920
1921 for (i = 0; mce_attrs[i]; i++)
1922 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1923
1924 for (i = 0; i < banks; i++)
1925 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
1926
1927 sysdev_unregister(&per_cpu(mce_dev, cpu));
1928 cpumask_clear_cpu(cpu, mce_dev_initialized);
1929}
1930
1931
1932static void mce_disable_cpu(void *h)
1933{
1934 unsigned long action = *(unsigned long *)h;
1935 int i;
1936
1937 if (!mce_available(¤t_cpu_data))
1938 return;
1939 if (!(action & CPU_TASKS_FROZEN))
1940 cmci_clear();
1941 for (i = 0; i < banks; i++) {
1942 struct mce_bank *b = &mce_banks[i];
1943
1944 if (b->init)
1945 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1946 }
1947}
1948
1949static void mce_reenable_cpu(void *h)
1950{
1951 unsigned long action = *(unsigned long *)h;
1952 int i;
1953
1954 if (!mce_available(¤t_cpu_data))
1955 return;
1956
1957 if (!(action & CPU_TASKS_FROZEN))
1958 cmci_reenable();
1959 for (i = 0; i < banks; i++) {
1960 struct mce_bank *b = &mce_banks[i];
1961
1962 if (b->init)
1963 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1964 }
1965}
1966
1967
1968static int __cpuinit
1969mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1970{
1971 unsigned int cpu = (unsigned long)hcpu;
1972 struct timer_list *t = &per_cpu(mce_timer, cpu);
1973
1974 switch (action) {
1975 case CPU_ONLINE:
1976 case CPU_ONLINE_FROZEN:
1977 mce_create_device(cpu);
1978 if (threshold_cpu_callback)
1979 threshold_cpu_callback(action, cpu);
1980 break;
1981 case CPU_DEAD:
1982 case CPU_DEAD_FROZEN:
1983 if (threshold_cpu_callback)
1984 threshold_cpu_callback(action, cpu);
1985 mce_remove_device(cpu);
1986 break;
1987 case CPU_DOWN_PREPARE:
1988 case CPU_DOWN_PREPARE_FROZEN:
1989 del_timer_sync(t);
1990 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1991 break;
1992 case CPU_DOWN_FAILED:
1993 case CPU_DOWN_FAILED_FROZEN:
1994 t->expires = round_jiffies(jiffies +
1995 __get_cpu_var(mce_next_interval));
1996 add_timer_on(t, cpu);
1997 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1998 break;
1999 case CPU_POST_DEAD:
2000
2001 cmci_rediscover(cpu);
2002 break;
2003 }
2004 return NOTIFY_OK;
2005}
2006
2007static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2008 .notifier_call = mce_cpu_callback,
2009};
2010
2011static __init void mce_init_banks(void)
2012{
2013 int i;
2014
2015 for (i = 0; i < banks; i++) {
2016 struct mce_bank *b = &mce_banks[i];
2017 struct sysdev_attribute *a = &b->attr;
2018
2019 a->attr.name = b->attrname;
2020 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2021
2022 a->attr.mode = 0644;
2023 a->show = show_bank;
2024 a->store = set_bank;
2025 }
2026}
2027
2028static __init int mce_init_device(void)
2029{
2030 int err;
2031 int i = 0;
2032
2033 if (!mce_available(&boot_cpu_data))
2034 return -EIO;
2035
2036 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2037
2038 mce_init_banks();
2039
2040 err = sysdev_class_register(&mce_sysclass);
2041 if (err)
2042 return err;
2043
2044 for_each_online_cpu(i) {
2045 err = mce_create_device(i);
2046 if (err)
2047 return err;
2048 }
2049
2050 register_hotcpu_notifier(&mce_cpu_notifier);
2051 misc_register(&mce_log_device);
2052
2053 return err;
2054}
2055
2056device_initcall(mce_init_device);
2057
2058
2059
2060
2061static int __init mcheck_disable(char *str)
2062{
2063 mce_disabled = 1;
2064 return 1;
2065}
2066__setup("nomce", mcheck_disable);
2067
2068#ifdef CONFIG_DEBUG_FS
2069struct dentry *mce_get_debugfs_dir(void)
2070{
2071 static struct dentry *dmce;
2072
2073 if (!dmce)
2074 dmce = debugfs_create_dir("mce", NULL);
2075
2076 return dmce;
2077}
2078
2079static void mce_reset(void)
2080{
2081 cpu_missing = 0;
2082 atomic_set(&mce_fake_paniced, 0);
2083 atomic_set(&mce_executing, 0);
2084 atomic_set(&mce_callin, 0);
2085 atomic_set(&global_nwo, 0);
2086}
2087
2088static int fake_panic_get(void *data, u64 *val)
2089{
2090 *val = fake_panic;
2091 return 0;
2092}
2093
2094static int fake_panic_set(void *data, u64 val)
2095{
2096 mce_reset();
2097 fake_panic = val;
2098 return 0;
2099}
2100
2101DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2102 fake_panic_set, "%llu\n");
2103
2104static int __init mce_debugfs_init(void)
2105{
2106 struct dentry *dmce, *ffake_panic;
2107
2108 dmce = mce_get_debugfs_dir();
2109 if (!dmce)
2110 return -ENOMEM;
2111 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2112 &fake_panic_fops);
2113 if (!ffake_panic)
2114 return -ENOMEM;
2115
2116 return 0;
2117}
2118late_initcall(mce_debugfs_init);
2119#endif
2120