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25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30#include <linux/spinlock.h>
31#include <linux/string.h>
32#include <linux/crash_dump.h>
33#include <linux/dma-mapping.h>
34#include <linux/bitops.h>
35#include <linux/pci_ids.h>
36#include <linux/pci.h>
37#include <linux/delay.h>
38#include <linux/scatterlist.h>
39#include <linux/iommu-helper.h>
40
41#include <asm/iommu.h>
42#include <asm/calgary.h>
43#include <asm/tce.h>
44#include <asm/pci-direct.h>
45#include <asm/system.h>
46#include <asm/dma.h>
47#include <asm/rio.h>
48#include <asm/bios_ebda.h>
49
50#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
51int use_calgary __read_mostly = 1;
52#else
53int use_calgary __read_mostly = 0;
54#endif
55
56#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
57#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
58
59
60#define CALGARY_CONFIG_REG 0x0108
61#define PHB_CSR_OFFSET 0x0110
62#define PHB_PLSSR_OFFSET 0x0120
63#define PHB_CONFIG_RW_OFFSET 0x0160
64#define PHB_IOBASE_BAR_LOW 0x0170
65#define PHB_IOBASE_BAR_HIGH 0x0180
66#define PHB_MEM_1_LOW 0x0190
67#define PHB_MEM_1_HIGH 0x01A0
68#define PHB_IO_ADDR_SIZE 0x01B0
69#define PHB_MEM_1_SIZE 0x01C0
70#define PHB_MEM_ST_OFFSET 0x01D0
71#define PHB_AER_OFFSET 0x0200
72#define PHB_CONFIG_0_HIGH 0x0220
73#define PHB_CONFIG_0_LOW 0x0230
74#define PHB_CONFIG_0_END 0x0240
75#define PHB_MEM_2_LOW 0x02B0
76#define PHB_MEM_2_HIGH 0x02C0
77#define PHB_MEM_2_SIZE_HIGH 0x02D0
78#define PHB_MEM_2_SIZE_LOW 0x02E0
79#define PHB_DOSHOLE_OFFSET 0x08E0
80
81
82#define PHB_SAVIOR_L2 0x0DB0
83#define PHB_PAGE_MIG_CTRL 0x0DA8
84#define PHB_PAGE_MIG_DEBUG 0x0DA0
85#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
86
87
88#define PHB_TCE_ENABLE 0x20000000
89#define PHB_SLOT_DISABLE 0x1C000000
90#define PHB_DAC_DISABLE 0x01000000
91#define PHB_MEM2_ENABLE 0x00400000
92#define PHB_MCSR_ENABLE 0x00100000
93
94#define TAR_SW_BITS 0x0000ffffffff800fUL
95#define TAR_VALID 0x0000000000000008UL
96
97#define CSR_AGENT_MASK 0xffe0ffff
98
99#define CCR_2SEC_TIMEOUT 0x000000000000000EUL
100
101#define PMR_SOFTSTOP 0x80000000
102#define PMR_SOFTSTOPFAULT 0x40000000
103#define PMR_HARDSTOP 0x20000000
104
105#define MAX_NUM_OF_PHBS 8
106#define MAX_NUM_CHASSIS 8
107
108#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
109#define PHBS_PER_CALGARY 4
110
111
112static const unsigned long tar_offsets[] = {
113 0x0580 ,
114 0x0588 ,
115 0x0590 ,
116 0x0598
117};
118
119static const unsigned long split_queue_offsets[] = {
120 0x4870 ,
121 0x5870 ,
122 0x6870 ,
123 0x7870
124};
125
126static const unsigned long phb_offsets[] = {
127 0x8000 ,
128 0x9000 ,
129 0xA000 ,
130 0xB000
131};
132
133
134
135static const unsigned long phb_debug_offsets[] = {
136 0x4000 ,
137 0x5000 ,
138 0x6000 ,
139 0x7000
140};
141
142
143
144
145
146
147#define PHB_DEBUG_STUFF_OFFSET 0x0020
148
149#define EMERGENCY_PAGES 32
150
151unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
152static int translate_empty_slots __read_mostly = 0;
153static int calgary_detected __read_mostly = 0;
154
155static struct rio_table_hdr *rio_table_hdr __initdata;
156static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
157static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
158
159struct calgary_bus_info {
160 void *tce_space;
161 unsigned char translation_disabled;
162 signed char phbid;
163 void __iomem *bbar;
164};
165
166static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
167static void calgary_tce_cache_blast(struct iommu_table *tbl);
168static void calgary_dump_error_regs(struct iommu_table *tbl);
169static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
170static void calioc2_tce_cache_blast(struct iommu_table *tbl);
171static void calioc2_dump_error_regs(struct iommu_table *tbl);
172static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
173static void get_tce_space_from_tar(void);
174
175static struct cal_chipset_ops calgary_chip_ops = {
176 .handle_quirks = calgary_handle_quirks,
177 .tce_cache_blast = calgary_tce_cache_blast,
178 .dump_error_regs = calgary_dump_error_regs
179};
180
181static struct cal_chipset_ops calioc2_chip_ops = {
182 .handle_quirks = calioc2_handle_quirks,
183 .tce_cache_blast = calioc2_tce_cache_blast,
184 .dump_error_regs = calioc2_dump_error_regs
185};
186
187static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
188
189static inline int translation_enabled(struct iommu_table *tbl)
190{
191
192 return (tbl != NULL);
193}
194
195static void iommu_range_reserve(struct iommu_table *tbl,
196 unsigned long start_addr, unsigned int npages)
197{
198 unsigned long index;
199 unsigned long end;
200 unsigned long flags;
201
202 index = start_addr >> PAGE_SHIFT;
203
204
205 if (index >= tbl->it_size)
206 return;
207
208 end = index + npages;
209 if (end > tbl->it_size)
210 end = tbl->it_size;
211
212 spin_lock_irqsave(&tbl->it_lock, flags);
213
214 iommu_area_reserve(tbl->it_map, index, npages);
215
216 spin_unlock_irqrestore(&tbl->it_lock, flags);
217}
218
219static unsigned long iommu_range_alloc(struct device *dev,
220 struct iommu_table *tbl,
221 unsigned int npages)
222{
223 unsigned long flags;
224 unsigned long offset;
225 unsigned long boundary_size;
226
227 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
228 PAGE_SIZE) >> PAGE_SHIFT;
229
230 BUG_ON(npages == 0);
231
232 spin_lock_irqsave(&tbl->it_lock, flags);
233
234 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
235 npages, 0, boundary_size, 0);
236 if (offset == ~0UL) {
237 tbl->chip_ops->tce_cache_blast(tbl);
238
239 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
240 npages, 0, boundary_size, 0);
241 if (offset == ~0UL) {
242 printk(KERN_WARNING "Calgary: IOMMU full.\n");
243 spin_unlock_irqrestore(&tbl->it_lock, flags);
244 if (panic_on_overflow)
245 panic("Calgary: fix the allocator.\n");
246 else
247 return bad_dma_address;
248 }
249 }
250
251 tbl->it_hint = offset + npages;
252 BUG_ON(tbl->it_hint > tbl->it_size);
253
254 spin_unlock_irqrestore(&tbl->it_lock, flags);
255
256 return offset;
257}
258
259static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
260 void *vaddr, unsigned int npages, int direction)
261{
262 unsigned long entry;
263 dma_addr_t ret = bad_dma_address;
264
265 entry = iommu_range_alloc(dev, tbl, npages);
266
267 if (unlikely(entry == bad_dma_address))
268 goto error;
269
270
271 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
272
273
274 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
275 direction);
276
277 return ret;
278
279error:
280 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
281 "iommu %p\n", npages, tbl);
282 return bad_dma_address;
283}
284
285static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
286 unsigned int npages)
287{
288 unsigned long entry;
289 unsigned long badend;
290 unsigned long flags;
291
292
293 badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
294 if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
295 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
296 "address 0x%Lx\n", dma_addr);
297 return;
298 }
299
300 entry = dma_addr >> PAGE_SHIFT;
301
302 BUG_ON(entry + npages > tbl->it_size);
303
304 tce_free(tbl, entry, npages);
305
306 spin_lock_irqsave(&tbl->it_lock, flags);
307
308 iommu_area_free(tbl->it_map, entry, npages);
309
310 spin_unlock_irqrestore(&tbl->it_lock, flags);
311}
312
313static inline struct iommu_table *find_iommu_table(struct device *dev)
314{
315 struct pci_dev *pdev;
316 struct pci_bus *pbus;
317 struct iommu_table *tbl;
318
319 pdev = to_pci_dev(dev);
320
321 pbus = pdev->bus;
322
323
324 while (pbus->parent)
325 pbus = pbus->parent;
326
327 tbl = pci_iommu(pbus);
328
329 BUG_ON(tbl && (tbl->it_busno != pbus->number));
330
331 return tbl;
332}
333
334static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
335 int nelems,enum dma_data_direction dir,
336 struct dma_attrs *attrs)
337{
338 struct iommu_table *tbl = find_iommu_table(dev);
339 struct scatterlist *s;
340 int i;
341
342 if (!translation_enabled(tbl))
343 return;
344
345 for_each_sg(sglist, s, nelems, i) {
346 unsigned int npages;
347 dma_addr_t dma = s->dma_address;
348 unsigned int dmalen = s->dma_length;
349
350 if (dmalen == 0)
351 break;
352
353 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
354 iommu_free(tbl, dma, npages);
355 }
356}
357
358static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
359 int nelems, enum dma_data_direction dir,
360 struct dma_attrs *attrs)
361{
362 struct iommu_table *tbl = find_iommu_table(dev);
363 struct scatterlist *s;
364 unsigned long vaddr;
365 unsigned int npages;
366 unsigned long entry;
367 int i;
368
369 for_each_sg(sg, s, nelems, i) {
370 BUG_ON(!sg_page(s));
371
372 vaddr = (unsigned long) sg_virt(s);
373 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
374
375 entry = iommu_range_alloc(dev, tbl, npages);
376 if (entry == bad_dma_address) {
377
378 s->dma_length = 0;
379 goto error;
380 }
381
382 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
383
384
385 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
386
387 s->dma_length = s->length;
388 }
389
390 return nelems;
391error:
392 calgary_unmap_sg(dev, sg, nelems, dir, NULL);
393 for_each_sg(sg, s, nelems, i) {
394 sg->dma_address = bad_dma_address;
395 sg->dma_length = 0;
396 }
397 return 0;
398}
399
400static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
401 unsigned long offset, size_t size,
402 enum dma_data_direction dir,
403 struct dma_attrs *attrs)
404{
405 void *vaddr = page_address(page) + offset;
406 unsigned long uaddr;
407 unsigned int npages;
408 struct iommu_table *tbl = find_iommu_table(dev);
409
410 uaddr = (unsigned long)vaddr;
411 npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
412
413 return iommu_alloc(dev, tbl, vaddr, npages, dir);
414}
415
416static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
417 size_t size, enum dma_data_direction dir,
418 struct dma_attrs *attrs)
419{
420 struct iommu_table *tbl = find_iommu_table(dev);
421 unsigned int npages;
422
423 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
424 iommu_free(tbl, dma_addr, npages);
425}
426
427static void* calgary_alloc_coherent(struct device *dev, size_t size,
428 dma_addr_t *dma_handle, gfp_t flag)
429{
430 void *ret = NULL;
431 dma_addr_t mapping;
432 unsigned int npages, order;
433 struct iommu_table *tbl = find_iommu_table(dev);
434
435 size = PAGE_ALIGN(size);
436 npages = size >> PAGE_SHIFT;
437 order = get_order(size);
438
439 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
440
441
442 ret = (void *)__get_free_pages(flag, order);
443 if (!ret)
444 goto error;
445 memset(ret, 0, size);
446
447
448 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
449 if (mapping == bad_dma_address)
450 goto free;
451 *dma_handle = mapping;
452 return ret;
453free:
454 free_pages((unsigned long)ret, get_order(size));
455 ret = NULL;
456error:
457 return ret;
458}
459
460static void calgary_free_coherent(struct device *dev, size_t size,
461 void *vaddr, dma_addr_t dma_handle)
462{
463 unsigned int npages;
464 struct iommu_table *tbl = find_iommu_table(dev);
465
466 size = PAGE_ALIGN(size);
467 npages = size >> PAGE_SHIFT;
468
469 iommu_free(tbl, dma_handle, npages);
470 free_pages((unsigned long)vaddr, get_order(size));
471}
472
473static struct dma_map_ops calgary_dma_ops = {
474 .alloc_coherent = calgary_alloc_coherent,
475 .free_coherent = calgary_free_coherent,
476 .map_sg = calgary_map_sg,
477 .unmap_sg = calgary_unmap_sg,
478 .map_page = calgary_map_page,
479 .unmap_page = calgary_unmap_page,
480};
481
482static inline void __iomem * busno_to_bbar(unsigned char num)
483{
484 return bus_info[num].bbar;
485}
486
487static inline int busno_to_phbid(unsigned char num)
488{
489 return bus_info[num].phbid;
490}
491
492static inline unsigned long split_queue_offset(unsigned char num)
493{
494 size_t idx = busno_to_phbid(num);
495
496 return split_queue_offsets[idx];
497}
498
499static inline unsigned long tar_offset(unsigned char num)
500{
501 size_t idx = busno_to_phbid(num);
502
503 return tar_offsets[idx];
504}
505
506static inline unsigned long phb_offset(unsigned char num)
507{
508 size_t idx = busno_to_phbid(num);
509
510 return phb_offsets[idx];
511}
512
513static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
514{
515 unsigned long target = ((unsigned long)bar) | offset;
516 return (void __iomem*)target;
517}
518
519static inline int is_calioc2(unsigned short device)
520{
521 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
522}
523
524static inline int is_calgary(unsigned short device)
525{
526 return (device == PCI_DEVICE_ID_IBM_CALGARY);
527}
528
529static inline int is_cal_pci_dev(unsigned short device)
530{
531 return (is_calgary(device) || is_calioc2(device));
532}
533
534static void calgary_tce_cache_blast(struct iommu_table *tbl)
535{
536 u64 val;
537 u32 aer;
538 int i = 0;
539 void __iomem *bbar = tbl->bbar;
540 void __iomem *target;
541
542
543 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
544 aer = readl(target);
545 writel(0, target);
546
547
548 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
549 val = readl(target);
550
551
552 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
553 do {
554 val = readq(target);
555 i++;
556 } while ((val & 0xff) != 0xff && i < 100);
557 if (i == 100)
558 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
559 "continuing anyway\n");
560
561
562 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
563 writeq(tbl->tar_val, target);
564
565
566 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
567 writel(aer, target);
568 (void)readl(target);
569}
570
571static void calioc2_tce_cache_blast(struct iommu_table *tbl)
572{
573 void __iomem *bbar = tbl->bbar;
574 void __iomem *target;
575 u64 val64;
576 u32 val;
577 int i = 0;
578 int count = 1;
579 unsigned char bus = tbl->it_busno;
580
581begin:
582 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
583 "sequence - count %d\n", bus, count);
584
585
586 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
587 val = be32_to_cpu(readl(target));
588 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
589 val |= PMR_SOFTSTOP;
590 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
591 writel(cpu_to_be32(val), target);
592
593
594 printk(KERN_DEBUG "2a. starting to poll split queues\n");
595 target = calgary_reg(bbar, split_queue_offset(bus));
596 do {
597 val64 = readq(target);
598 i++;
599 } while ((val64 & 0xff) != 0xff && i < 100);
600 if (i == 100)
601 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
602 "continuing anyway\n");
603
604
605 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
606 val = be32_to_cpu(readl(target));
607 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
608
609
610 if (val & PMR_SOFTSTOPFAULT) {
611 if (++count < 100)
612 goto begin;
613 else {
614 printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
615 "aborting TCE cache flush sequence!\n");
616 return;
617 }
618 }
619
620
621 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
622 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
623 val = be32_to_cpu(readl(target));
624 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
625 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
626 val = be32_to_cpu(readl(target));
627 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
628
629
630 printk(KERN_DEBUG "6. invalidating TCE cache\n");
631 target = calgary_reg(bbar, tar_offset(bus));
632 writeq(tbl->tar_val, target);
633
634
635 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
636 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
637 val = be32_to_cpu(readl(target));
638 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
639
640
641 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
642 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
643 val = 0;
644 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
645 writel(cpu_to_be32(val), target);
646 val = be32_to_cpu(readl(target));
647 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
648}
649
650static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
651 u64 limit)
652{
653 unsigned int numpages;
654
655 limit = limit | 0xfffff;
656 limit++;
657
658 numpages = ((limit - start) >> PAGE_SHIFT);
659 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
660}
661
662static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
663{
664 void __iomem *target;
665 u64 low, high, sizelow;
666 u64 start, limit;
667 struct iommu_table *tbl = pci_iommu(dev->bus);
668 unsigned char busnum = dev->bus->number;
669 void __iomem *bbar = tbl->bbar;
670
671
672 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
673 low = be32_to_cpu(readl(target));
674 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
675 high = be32_to_cpu(readl(target));
676 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
677 sizelow = be32_to_cpu(readl(target));
678
679 start = (high << 32) | low;
680 limit = sizelow;
681
682 calgary_reserve_mem_region(dev, start, limit);
683}
684
685static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
686{
687 void __iomem *target;
688 u32 val32;
689 u64 low, high, sizelow, sizehigh;
690 u64 start, limit;
691 struct iommu_table *tbl = pci_iommu(dev->bus);
692 unsigned char busnum = dev->bus->number;
693 void __iomem *bbar = tbl->bbar;
694
695
696 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
697 val32 = be32_to_cpu(readl(target));
698 if (!(val32 & PHB_MEM2_ENABLE))
699 return;
700
701 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
702 low = be32_to_cpu(readl(target));
703 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
704 high = be32_to_cpu(readl(target));
705 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
706 sizelow = be32_to_cpu(readl(target));
707 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
708 sizehigh = be32_to_cpu(readl(target));
709
710 start = (high << 32) | low;
711 limit = (sizehigh << 32) | sizelow;
712
713 calgary_reserve_mem_region(dev, start, limit);
714}
715
716
717
718
719
720
721
722
723static void __init calgary_reserve_regions(struct pci_dev *dev)
724{
725 unsigned int npages;
726 u64 start;
727 struct iommu_table *tbl = pci_iommu(dev->bus);
728
729
730 iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
731
732
733
734 if (is_calgary(dev->device)) {
735 start = (640 * 1024);
736 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
737 } else {
738 start = 0;
739 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
740 }
741 iommu_range_reserve(tbl, start, npages);
742
743
744 calgary_reserve_peripheral_mem_1(dev);
745 calgary_reserve_peripheral_mem_2(dev);
746}
747
748static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
749{
750 u64 val64;
751 u64 table_phys;
752 void __iomem *target;
753 int ret;
754 struct iommu_table *tbl;
755
756
757 ret = build_tce_table(dev, bbar);
758 if (ret)
759 return ret;
760
761 tbl = pci_iommu(dev->bus);
762 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
763
764 if (is_kdump_kernel())
765 calgary_init_bitmap_from_tce_table(tbl);
766 else
767 tce_free(tbl, 0, tbl->it_size);
768
769 if (is_calgary(dev->device))
770 tbl->chip_ops = &calgary_chip_ops;
771 else if (is_calioc2(dev->device))
772 tbl->chip_ops = &calioc2_chip_ops;
773 else
774 BUG();
775
776 calgary_reserve_regions(dev);
777
778
779 target = calgary_reg(bbar, tar_offset(dev->bus->number));
780 val64 = be64_to_cpu(readq(target));
781
782
783 val64 &= ~TAR_SW_BITS;
784 table_phys = (u64)__pa(tbl->it_base);
785
786 val64 |= table_phys;
787
788 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
789 val64 |= (u64) specified_table_size;
790
791 tbl->tar_val = cpu_to_be64(val64);
792
793 writeq(tbl->tar_val, target);
794 readq(target);
795
796 return 0;
797}
798
799static void __init calgary_free_bus(struct pci_dev *dev)
800{
801 u64 val64;
802 struct iommu_table *tbl = pci_iommu(dev->bus);
803 void __iomem *target;
804 unsigned int bitmapsz;
805
806 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
807 val64 = be64_to_cpu(readq(target));
808 val64 &= ~TAR_SW_BITS;
809 writeq(cpu_to_be64(val64), target);
810 readq(target);
811
812 bitmapsz = tbl->it_size / BITS_PER_BYTE;
813 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
814 tbl->it_map = NULL;
815
816 kfree(tbl);
817
818 set_pci_iommu(dev->bus, NULL);
819
820
821 bus_info[dev->bus->number].tce_space = NULL;
822}
823
824static void calgary_dump_error_regs(struct iommu_table *tbl)
825{
826 void __iomem *bbar = tbl->bbar;
827 void __iomem *target;
828 u32 csr, plssr;
829
830 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
831 csr = be32_to_cpu(readl(target));
832
833 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
834 plssr = be32_to_cpu(readl(target));
835
836
837 printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
838 "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
839}
840
841static void calioc2_dump_error_regs(struct iommu_table *tbl)
842{
843 void __iomem *bbar = tbl->bbar;
844 u32 csr, csmr, plssr, mck, rcstat;
845 void __iomem *target;
846 unsigned long phboff = phb_offset(tbl->it_busno);
847 unsigned long erroff;
848 u32 errregs[7];
849 int i;
850
851
852 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
853 csr = be32_to_cpu(readl(target));
854
855 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
856 plssr = be32_to_cpu(readl(target));
857
858 target = calgary_reg(bbar, phboff | 0x290);
859 csmr = be32_to_cpu(readl(target));
860
861 target = calgary_reg(bbar, phboff | 0x800);
862 mck = be32_to_cpu(readl(target));
863
864 printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
865 tbl->it_busno);
866
867 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
868 csr, plssr, csmr, mck);
869
870
871 printk(KERN_EMERG "Calgary: ");
872 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
873
874 erroff = (0x810 + (i * 0x10));
875 target = calgary_reg(bbar, phboff | erroff);
876 errregs[i] = be32_to_cpu(readl(target));
877 printk("0x%08x@0x%lx ", errregs[i], erroff);
878 }
879 printk("\n");
880
881
882 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
883 rcstat = be32_to_cpu(readl(target));
884 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
885 PHB_ROOT_COMPLEX_STATUS);
886}
887
888static void calgary_watchdog(unsigned long data)
889{
890 struct pci_dev *dev = (struct pci_dev *)data;
891 struct iommu_table *tbl = pci_iommu(dev->bus);
892 void __iomem *bbar = tbl->bbar;
893 u32 val32;
894 void __iomem *target;
895
896 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
897 val32 = be32_to_cpu(readl(target));
898
899
900 if (val32 & CSR_AGENT_MASK) {
901 tbl->chip_ops->dump_error_regs(tbl);
902
903
904 writel(0, target);
905
906
907 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
908 PHB_CONFIG_RW_OFFSET);
909 val32 = be32_to_cpu(readl(target));
910 val32 |= PHB_SLOT_DISABLE;
911 writel(cpu_to_be32(val32), target);
912 readl(target);
913 } else {
914
915 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
916 }
917}
918
919static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
920 unsigned char busnum, unsigned long timeout)
921{
922 u64 val64;
923 void __iomem *target;
924 unsigned int phb_shift = ~0;
925 u64 mask;
926
927 switch (busno_to_phbid(busnum)) {
928 case 0: phb_shift = (63 - 19);
929 break;
930 case 1: phb_shift = (63 - 23);
931 break;
932 case 2: phb_shift = (63 - 27);
933 break;
934 case 3: phb_shift = (63 - 35);
935 break;
936 default:
937 BUG_ON(busno_to_phbid(busnum));
938 }
939
940 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
941 val64 = be64_to_cpu(readq(target));
942
943
944 mask = ~(0xFUL << phb_shift);
945 val64 &= mask;
946 val64 |= (timeout << phb_shift);
947 writeq(cpu_to_be64(val64), target);
948 readq(target);
949}
950
951static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
952{
953 unsigned char busnum = dev->bus->number;
954 void __iomem *bbar = tbl->bbar;
955 void __iomem *target;
956 u32 val;
957
958
959
960
961 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
962 val = cpu_to_be32(readl(target));
963 val |= 0x00800000;
964 writel(cpu_to_be32(val), target);
965}
966
967static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
968{
969 unsigned char busnum = dev->bus->number;
970
971
972
973
974
975 if (is_calgary(dev->device) && (busnum == 1))
976 calgary_set_split_completion_timeout(tbl->bbar, busnum,
977 CCR_2SEC_TIMEOUT);
978}
979
980static void __init calgary_enable_translation(struct pci_dev *dev)
981{
982 u32 val32;
983 unsigned char busnum;
984 void __iomem *target;
985 void __iomem *bbar;
986 struct iommu_table *tbl;
987
988 busnum = dev->bus->number;
989 tbl = pci_iommu(dev->bus);
990 bbar = tbl->bbar;
991
992
993 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
994 val32 = be32_to_cpu(readl(target));
995 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
996
997 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
998 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
999 "Calgary" : "CalIOC2", busnum);
1000 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1001 "bus.\n");
1002
1003 writel(cpu_to_be32(val32), target);
1004 readl(target);
1005
1006 init_timer(&tbl->watchdog_timer);
1007 tbl->watchdog_timer.function = &calgary_watchdog;
1008 tbl->watchdog_timer.data = (unsigned long)dev;
1009 mod_timer(&tbl->watchdog_timer, jiffies);
1010}
1011
1012static void __init calgary_disable_translation(struct pci_dev *dev)
1013{
1014 u32 val32;
1015 unsigned char busnum;
1016 void __iomem *target;
1017 void __iomem *bbar;
1018 struct iommu_table *tbl;
1019
1020 busnum = dev->bus->number;
1021 tbl = pci_iommu(dev->bus);
1022 bbar = tbl->bbar;
1023
1024
1025 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1026 val32 = be32_to_cpu(readl(target));
1027 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1028
1029 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1030 writel(cpu_to_be32(val32), target);
1031 readl(target);
1032
1033 del_timer_sync(&tbl->watchdog_timer);
1034}
1035
1036static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1037{
1038 pci_dev_get(dev);
1039 set_pci_iommu(dev->bus, NULL);
1040
1041
1042 if (dev->bus->parent)
1043 dev->bus->parent->self = dev;
1044 else
1045 dev->bus->self = dev;
1046}
1047
1048static int __init calgary_init_one(struct pci_dev *dev)
1049{
1050 void __iomem *bbar;
1051 struct iommu_table *tbl;
1052 int ret;
1053
1054 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1055
1056 bbar = busno_to_bbar(dev->bus->number);
1057 ret = calgary_setup_tar(dev, bbar);
1058 if (ret)
1059 goto done;
1060
1061 pci_dev_get(dev);
1062
1063 if (dev->bus->parent) {
1064 if (dev->bus->parent->self)
1065 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1066 "bus->parent->self!\n", dev);
1067 dev->bus->parent->self = dev;
1068 } else
1069 dev->bus->self = dev;
1070
1071 tbl = pci_iommu(dev->bus);
1072 tbl->chip_ops->handle_quirks(tbl, dev);
1073
1074 calgary_enable_translation(dev);
1075
1076 return 0;
1077
1078done:
1079 return ret;
1080}
1081
1082static int __init calgary_locate_bbars(void)
1083{
1084 int ret;
1085 int rioidx, phb, bus;
1086 void __iomem *bbar;
1087 void __iomem *target;
1088 unsigned long offset;
1089 u8 start_bus, end_bus;
1090 u32 val;
1091
1092 ret = -ENODATA;
1093 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1094 struct rio_detail *rio = rio_devs[rioidx];
1095
1096 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1097 continue;
1098
1099
1100 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1101 if (!bbar)
1102 goto error;
1103
1104 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1105 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1106 target = calgary_reg(bbar, offset);
1107
1108 val = be32_to_cpu(readl(target));
1109
1110 start_bus = (u8)((val & 0x00FF0000) >> 16);
1111 end_bus = (u8)((val & 0x0000FF00) >> 8);
1112
1113 if (end_bus) {
1114 for (bus = start_bus; bus <= end_bus; bus++) {
1115 bus_info[bus].bbar = bbar;
1116 bus_info[bus].phbid = phb;
1117 }
1118 } else {
1119 bus_info[start_bus].bbar = bbar;
1120 bus_info[start_bus].phbid = phb;
1121 }
1122 }
1123 }
1124
1125 return 0;
1126
1127error:
1128
1129 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1130 if (bus_info[bus].bbar)
1131 iounmap(bus_info[bus].bbar);
1132
1133 return ret;
1134}
1135
1136static int __init calgary_init(void)
1137{
1138 int ret;
1139 struct pci_dev *dev = NULL;
1140 struct calgary_bus_info *info;
1141
1142 ret = calgary_locate_bbars();
1143 if (ret)
1144 return ret;
1145
1146
1147 if (is_kdump_kernel())
1148 get_tce_space_from_tar();
1149
1150 do {
1151 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1152 if (!dev)
1153 break;
1154 if (!is_cal_pci_dev(dev->device))
1155 continue;
1156
1157 info = &bus_info[dev->bus->number];
1158 if (info->translation_disabled) {
1159 calgary_init_one_nontraslated(dev);
1160 continue;
1161 }
1162
1163 if (!info->tce_space && !translate_empty_slots)
1164 continue;
1165
1166 ret = calgary_init_one(dev);
1167 if (ret)
1168 goto error;
1169 } while (1);
1170
1171 dev = NULL;
1172 for_each_pci_dev(dev) {
1173 struct iommu_table *tbl;
1174
1175 tbl = find_iommu_table(&dev->dev);
1176
1177 if (translation_enabled(tbl))
1178 dev->dev.archdata.dma_ops = &calgary_dma_ops;
1179 }
1180
1181 return ret;
1182
1183error:
1184 do {
1185 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1186 if (!dev)
1187 break;
1188 if (!is_cal_pci_dev(dev->device))
1189 continue;
1190
1191 info = &bus_info[dev->bus->number];
1192 if (info->translation_disabled) {
1193 pci_dev_put(dev);
1194 continue;
1195 }
1196 if (!info->tce_space && !translate_empty_slots)
1197 continue;
1198
1199 calgary_disable_translation(dev);
1200 calgary_free_bus(dev);
1201 pci_dev_put(dev);
1202 dev->dev.archdata.dma_ops = NULL;
1203 } while (1);
1204
1205 return ret;
1206}
1207
1208static inline int __init determine_tce_table_size(u64 ram)
1209{
1210 int ret;
1211
1212 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1213 return specified_table_size;
1214
1215
1216
1217
1218
1219
1220
1221
1222 ret = get_order(ram >> 13);
1223 if (ret > TCE_TABLE_SIZE_8M)
1224 ret = TCE_TABLE_SIZE_8M;
1225
1226 return ret;
1227}
1228
1229static int __init build_detail_arrays(void)
1230{
1231 unsigned long ptr;
1232 unsigned numnodes, i;
1233 int scal_detail_size, rio_detail_size;
1234
1235 numnodes = rio_table_hdr->num_scal_dev;
1236 if (numnodes > MAX_NUMNODES){
1237 printk(KERN_WARNING
1238 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1239 "but system has %d nodes.\n",
1240 MAX_NUMNODES, numnodes);
1241 return -ENODEV;
1242 }
1243
1244 switch (rio_table_hdr->version){
1245 case 2:
1246 scal_detail_size = 11;
1247 rio_detail_size = 13;
1248 break;
1249 case 3:
1250 scal_detail_size = 12;
1251 rio_detail_size = 15;
1252 break;
1253 default:
1254 printk(KERN_WARNING
1255 "Calgary: Invalid Rio Grande Table Version: %d\n",
1256 rio_table_hdr->version);
1257 return -EPROTO;
1258 }
1259
1260 ptr = ((unsigned long)rio_table_hdr) + 3;
1261 for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1262 scal_devs[i] = (struct scal_detail *)ptr;
1263
1264 for (i = 0; i < rio_table_hdr->num_rio_dev;
1265 i++, ptr += rio_detail_size)
1266 rio_devs[i] = (struct rio_detail *)ptr;
1267
1268 return 0;
1269}
1270
1271static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1272{
1273 int dev;
1274 u32 val;
1275
1276 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1277
1278
1279
1280
1281 return 1;
1282 }
1283
1284 for (dev = 1; dev < 8; dev++) {
1285 val = read_pci_config(bus, dev, 0, 0);
1286 if (val != 0xffffffff)
1287 break;
1288 }
1289 return (val != 0xffffffff);
1290}
1291
1292
1293
1294
1295
1296
1297static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1298{
1299 u64 *tp;
1300 unsigned int index;
1301 tp = ((u64 *)tbl->it_base);
1302 for (index = 0 ; index < tbl->it_size; index++) {
1303 if (*tp != 0x0)
1304 set_bit(index, tbl->it_map);
1305 tp++;
1306 }
1307}
1308
1309
1310
1311
1312
1313
1314static void __init get_tce_space_from_tar(void)
1315{
1316 int bus;
1317 void __iomem *target;
1318 unsigned long tce_space;
1319
1320 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1321 struct calgary_bus_info *info = &bus_info[bus];
1322 unsigned short pci_device;
1323 u32 val;
1324
1325 val = read_pci_config(bus, 0, 0, 0);
1326 pci_device = (val & 0xFFFF0000) >> 16;
1327
1328 if (!is_cal_pci_dev(pci_device))
1329 continue;
1330 if (info->translation_disabled)
1331 continue;
1332
1333 if (calgary_bus_has_devices(bus, pci_device) ||
1334 translate_empty_slots) {
1335 target = calgary_reg(bus_info[bus].bbar,
1336 tar_offset(bus));
1337 tce_space = be64_to_cpu(readq(target));
1338 tce_space = tce_space & TAR_SW_BITS;
1339
1340 tce_space = tce_space & (~specified_table_size);
1341 info->tce_space = (u64 *)__va(tce_space);
1342 }
1343 }
1344 return;
1345}
1346
1347void __init detect_calgary(void)
1348{
1349 int bus;
1350 void *tbl;
1351 int calgary_found = 0;
1352 unsigned long ptr;
1353 unsigned int offset, prev_offset;
1354 int ret;
1355
1356
1357
1358
1359
1360 if (swiotlb || no_iommu || iommu_detected)
1361 return;
1362
1363 if (!use_calgary)
1364 return;
1365
1366 if (!early_pci_allowed())
1367 return;
1368
1369 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1370
1371 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1372
1373 rio_table_hdr = NULL;
1374 prev_offset = 0;
1375 offset = 0x180;
1376
1377
1378
1379
1380 while (offset > prev_offset) {
1381
1382 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1383
1384 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1385 break;
1386 }
1387 prev_offset = offset;
1388 offset = *((unsigned short *)(ptr + offset));
1389 }
1390 if (!rio_table_hdr) {
1391 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1392 "in EBDA - bailing!\n");
1393 return;
1394 }
1395
1396 ret = build_detail_arrays();
1397 if (ret) {
1398 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1399 return;
1400 }
1401
1402 specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1403 saved_max_pfn : max_pfn) * PAGE_SIZE);
1404
1405 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1406 struct calgary_bus_info *info = &bus_info[bus];
1407 unsigned short pci_device;
1408 u32 val;
1409
1410 val = read_pci_config(bus, 0, 0, 0);
1411 pci_device = (val & 0xFFFF0000) >> 16;
1412
1413 if (!is_cal_pci_dev(pci_device))
1414 continue;
1415
1416 if (info->translation_disabled)
1417 continue;
1418
1419 if (calgary_bus_has_devices(bus, pci_device) ||
1420 translate_empty_slots) {
1421
1422
1423
1424
1425 if (!is_kdump_kernel()) {
1426 tbl = alloc_tce_table();
1427 if (!tbl)
1428 goto cleanup;
1429 info->tce_space = tbl;
1430 }
1431 calgary_found = 1;
1432 }
1433 }
1434
1435 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1436 calgary_found ? "found" : "not found");
1437
1438 if (calgary_found) {
1439 iommu_detected = 1;
1440 calgary_detected = 1;
1441 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1442 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1443 specified_table_size);
1444
1445
1446 if (max_pfn > MAX_DMA32_PFN)
1447 swiotlb = 1;
1448 }
1449 return;
1450
1451cleanup:
1452 for (--bus; bus >= 0; --bus) {
1453 struct calgary_bus_info *info = &bus_info[bus];
1454
1455 if (info->tce_space)
1456 free_tce_table(info->tce_space);
1457 }
1458}
1459
1460int __init calgary_iommu_init(void)
1461{
1462 int ret;
1463
1464 if (no_iommu || (swiotlb && !calgary_detected))
1465 return -ENODEV;
1466
1467 if (!calgary_detected)
1468 return -ENODEV;
1469
1470
1471 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1472
1473 ret = calgary_init();
1474 if (ret) {
1475 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1476 "falling back to no_iommu\n", ret);
1477 return ret;
1478 }
1479
1480 force_iommu = 1;
1481 bad_dma_address = 0x0;
1482
1483 if (!dma_ops)
1484 dma_ops = &nommu_dma_ops;
1485
1486 return 0;
1487}
1488
1489static int __init calgary_parse_options(char *p)
1490{
1491 unsigned int bridge;
1492 size_t len;
1493 char* endp;
1494
1495 while (*p) {
1496 if (!strncmp(p, "64k", 3))
1497 specified_table_size = TCE_TABLE_SIZE_64K;
1498 else if (!strncmp(p, "128k", 4))
1499 specified_table_size = TCE_TABLE_SIZE_128K;
1500 else if (!strncmp(p, "256k", 4))
1501 specified_table_size = TCE_TABLE_SIZE_256K;
1502 else if (!strncmp(p, "512k", 4))
1503 specified_table_size = TCE_TABLE_SIZE_512K;
1504 else if (!strncmp(p, "1M", 2))
1505 specified_table_size = TCE_TABLE_SIZE_1M;
1506 else if (!strncmp(p, "2M", 2))
1507 specified_table_size = TCE_TABLE_SIZE_2M;
1508 else if (!strncmp(p, "4M", 2))
1509 specified_table_size = TCE_TABLE_SIZE_4M;
1510 else if (!strncmp(p, "8M", 2))
1511 specified_table_size = TCE_TABLE_SIZE_8M;
1512
1513 len = strlen("translate_empty_slots");
1514 if (!strncmp(p, "translate_empty_slots", len))
1515 translate_empty_slots = 1;
1516
1517 len = strlen("disable");
1518 if (!strncmp(p, "disable", len)) {
1519 p += len;
1520 if (*p == '=')
1521 ++p;
1522 if (*p == '\0')
1523 break;
1524 bridge = simple_strtoul(p, &endp, 0);
1525 if (p == endp)
1526 break;
1527
1528 if (bridge < MAX_PHB_BUS_NUM) {
1529 printk(KERN_INFO "Calgary: disabling "
1530 "translation for PHB %#x\n", bridge);
1531 bus_info[bridge].translation_disabled = 1;
1532 }
1533 }
1534
1535 p = strpbrk(p, ",");
1536 if (!p)
1537 break;
1538
1539 p++;
1540 }
1541 return 1;
1542}
1543__setup("calgary=", calgary_parse_options);
1544
1545static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1546{
1547 struct iommu_table *tbl;
1548 unsigned int npages;
1549 int i;
1550
1551 tbl = pci_iommu(dev->bus);
1552
1553 for (i = 0; i < 4; i++) {
1554 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1555
1556
1557 if (!(r->flags & IORESOURCE_MEM))
1558 continue;
1559
1560
1561 if (!r->start)
1562 continue;
1563
1564
1565 npages = (r->end - r->start) >> PAGE_SHIFT;
1566 npages++;
1567
1568 iommu_range_reserve(tbl, r->start, npages);
1569 }
1570}
1571
1572static int __init calgary_fixup_tce_spaces(void)
1573{
1574 struct pci_dev *dev = NULL;
1575 struct calgary_bus_info *info;
1576
1577 if (no_iommu || swiotlb || !calgary_detected)
1578 return -ENODEV;
1579
1580 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1581
1582 do {
1583 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1584 if (!dev)
1585 break;
1586 if (!is_cal_pci_dev(dev->device))
1587 continue;
1588
1589 info = &bus_info[dev->bus->number];
1590 if (info->translation_disabled)
1591 continue;
1592
1593 if (!info->tce_space)
1594 continue;
1595
1596 calgary_fixup_one_tce_space(dev);
1597
1598 } while (1);
1599
1600 return 0;
1601}
1602
1603
1604
1605
1606
1607rootfs_initcall(calgary_fixup_tce_spaces);
1608