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14#include <linux/types.h>
15#include <linux/ctype.h>
16#include <linux/agp_backend.h>
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/spinlock.h>
22#include <linux/pci.h>
23#include <linux/module.h>
24#include <linux/topology.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27#include <linux/kdebug.h>
28#include <linux/scatterlist.h>
29#include <linux/iommu-helper.h>
30#include <linux/sysdev.h>
31#include <linux/io.h>
32#include <asm/atomic.h>
33#include <asm/mtrr.h>
34#include <asm/pgtable.h>
35#include <asm/proto.h>
36#include <asm/iommu.h>
37#include <asm/gart.h>
38#include <asm/cacheflush.h>
39#include <asm/swiotlb.h>
40#include <asm/dma.h>
41#include <asm/k8.h>
42
43static unsigned long iommu_bus_base;
44static unsigned long iommu_size;
45static unsigned long iommu_pages;
46
47static u32 *iommu_gatt_base;
48
49
50
51
52
53
54
55
56static int iommu_fullflush = 1;
57
58
59static DEFINE_SPINLOCK(iommu_bitmap_lock);
60
61static unsigned long *iommu_gart_bitmap;
62
63static u32 gart_unmapped_entry;
64
65#define GPTE_VALID 1
66#define GPTE_COHERENT 2
67#define GPTE_ENCODE(x) \
68 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
69#define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
70
71#define EMERGENCY_PAGES 32
72
73#ifdef CONFIG_AGP
74#define AGPEXTERN extern
75#else
76#define AGPEXTERN
77#endif
78
79
80AGPEXTERN int agp_memory_reserved;
81AGPEXTERN __u32 *agp_gatt_table;
82
83static unsigned long next_bit;
84static bool need_flush;
85
86static unsigned long alloc_iommu(struct device *dev, int size,
87 unsigned long align_mask)
88{
89 unsigned long offset, flags;
90 unsigned long boundary_size;
91 unsigned long base_index;
92
93 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
94 PAGE_SIZE) >> PAGE_SHIFT;
95 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
96 PAGE_SIZE) >> PAGE_SHIFT;
97
98 spin_lock_irqsave(&iommu_bitmap_lock, flags);
99 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
100 size, base_index, boundary_size, align_mask);
101 if (offset == -1) {
102 need_flush = true;
103 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
104 size, base_index, boundary_size,
105 align_mask);
106 }
107 if (offset != -1) {
108 next_bit = offset+size;
109 if (next_bit >= iommu_pages) {
110 next_bit = 0;
111 need_flush = true;
112 }
113 }
114 if (iommu_fullflush)
115 need_flush = true;
116 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
117
118 return offset;
119}
120
121static void free_iommu(unsigned long offset, int size)
122{
123 unsigned long flags;
124
125 spin_lock_irqsave(&iommu_bitmap_lock, flags);
126 iommu_area_free(iommu_gart_bitmap, offset, size);
127 if (offset >= next_bit)
128 next_bit = offset + size;
129 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
130}
131
132
133
134
135static void flush_gart(void)
136{
137 unsigned long flags;
138
139 spin_lock_irqsave(&iommu_bitmap_lock, flags);
140 if (need_flush) {
141 k8_flush_garts();
142 need_flush = false;
143 }
144 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
145}
146
147#ifdef CONFIG_IOMMU_LEAK
148
149static int leak_trace;
150static int iommu_leak_pages = 20;
151
152static void dump_leak(void)
153{
154 static int dump;
155
156 if (dump)
157 return;
158 dump = 1;
159
160 show_stack(NULL, NULL);
161 debug_dma_dump_mappings(NULL);
162}
163#endif
164
165static void iommu_full(struct device *dev, size_t size, int dir)
166{
167
168
169
170
171
172
173
174
175
176
177 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
178
179 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
180 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
181 panic("PCI-DMA: Memory would be corrupted\n");
182 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
183 panic(KERN_ERR
184 "PCI-DMA: Random memory would be DMAed\n");
185 }
186#ifdef CONFIG_IOMMU_LEAK
187 dump_leak();
188#endif
189}
190
191static inline int
192need_iommu(struct device *dev, unsigned long addr, size_t size)
193{
194 return force_iommu || !dma_capable(dev, addr, size);
195}
196
197static inline int
198nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
199{
200 return !dma_capable(dev, addr, size);
201}
202
203
204
205
206static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
207 size_t size, int dir, unsigned long align_mask)
208{
209 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
210 unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
211 int i;
212
213 if (iommu_page == -1) {
214 if (!nonforced_iommu(dev, phys_mem, size))
215 return phys_mem;
216 if (panic_on_overflow)
217 panic("dma_map_area overflow %lu bytes\n", size);
218 iommu_full(dev, size, dir);
219 return bad_dma_address;
220 }
221
222 for (i = 0; i < npages; i++) {
223 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
224 phys_mem += PAGE_SIZE;
225 }
226 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
227}
228
229
230static dma_addr_t gart_map_page(struct device *dev, struct page *page,
231 unsigned long offset, size_t size,
232 enum dma_data_direction dir,
233 struct dma_attrs *attrs)
234{
235 unsigned long bus;
236 phys_addr_t paddr = page_to_phys(page) + offset;
237
238 if (!dev)
239 dev = &x86_dma_fallback_dev;
240
241 if (!need_iommu(dev, paddr, size))
242 return paddr;
243
244 bus = dma_map_area(dev, paddr, size, dir, 0);
245 flush_gart();
246
247 return bus;
248}
249
250
251
252
253static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
254 size_t size, enum dma_data_direction dir,
255 struct dma_attrs *attrs)
256{
257 unsigned long iommu_page;
258 int npages;
259 int i;
260
261 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
262 dma_addr >= iommu_bus_base + iommu_size)
263 return;
264
265 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
266 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
267 for (i = 0; i < npages; i++) {
268 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
269 }
270 free_iommu(iommu_page, npages);
271}
272
273
274
275
276static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
277 enum dma_data_direction dir, struct dma_attrs *attrs)
278{
279 struct scatterlist *s;
280 int i;
281
282 for_each_sg(sg, s, nents, i) {
283 if (!s->dma_length || !s->length)
284 break;
285 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL);
286 }
287}
288
289
290static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
291 int nents, int dir)
292{
293 struct scatterlist *s;
294 int i;
295
296#ifdef CONFIG_IOMMU_DEBUG
297 printk(KERN_DEBUG "dma_map_sg overflow\n");
298#endif
299
300 for_each_sg(sg, s, nents, i) {
301 unsigned long addr = sg_phys(s);
302
303 if (nonforced_iommu(dev, addr, s->length)) {
304 addr = dma_map_area(dev, addr, s->length, dir, 0);
305 if (addr == bad_dma_address) {
306 if (i > 0)
307 gart_unmap_sg(dev, sg, i, dir, NULL);
308 nents = 0;
309 sg[0].dma_length = 0;
310 break;
311 }
312 }
313 s->dma_address = addr;
314 s->dma_length = s->length;
315 }
316 flush_gart();
317
318 return nents;
319}
320
321
322static int __dma_map_cont(struct device *dev, struct scatterlist *start,
323 int nelems, struct scatterlist *sout,
324 unsigned long pages)
325{
326 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
327 unsigned long iommu_page = iommu_start;
328 struct scatterlist *s;
329 int i;
330
331 if (iommu_start == -1)
332 return -1;
333
334 for_each_sg(start, s, nelems, i) {
335 unsigned long pages, addr;
336 unsigned long phys_addr = s->dma_address;
337
338 BUG_ON(s != start && s->offset);
339 if (s == start) {
340 sout->dma_address = iommu_bus_base;
341 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
342 sout->dma_length = s->length;
343 } else {
344 sout->dma_length += s->length;
345 }
346
347 addr = phys_addr;
348 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
349 while (pages--) {
350 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
351 addr += PAGE_SIZE;
352 iommu_page++;
353 }
354 }
355 BUG_ON(iommu_page - iommu_start != pages);
356
357 return 0;
358}
359
360static inline int
361dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
362 struct scatterlist *sout, unsigned long pages, int need)
363{
364 if (!need) {
365 BUG_ON(nelems != 1);
366 sout->dma_address = start->dma_address;
367 sout->dma_length = start->length;
368 return 0;
369 }
370 return __dma_map_cont(dev, start, nelems, sout, pages);
371}
372
373
374
375
376
377static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
378 enum dma_data_direction dir, struct dma_attrs *attrs)
379{
380 struct scatterlist *s, *ps, *start_sg, *sgmap;
381 int need = 0, nextneed, i, out, start;
382 unsigned long pages = 0;
383 unsigned int seg_size;
384 unsigned int max_seg_size;
385
386 if (nents == 0)
387 return 0;
388
389 if (!dev)
390 dev = &x86_dma_fallback_dev;
391
392 out = 0;
393 start = 0;
394 start_sg = sgmap = sg;
395 seg_size = 0;
396 max_seg_size = dma_get_max_seg_size(dev);
397 ps = NULL;
398 for_each_sg(sg, s, nents, i) {
399 dma_addr_t addr = sg_phys(s);
400
401 s->dma_address = addr;
402 BUG_ON(s->length == 0);
403
404 nextneed = need_iommu(dev, addr, s->length);
405
406
407 if (i > start) {
408
409
410
411
412
413 if (!iommu_merge || !nextneed || !need || s->offset ||
414 (s->length + seg_size > max_seg_size) ||
415 (ps->offset + ps->length) % PAGE_SIZE) {
416 if (dma_map_cont(dev, start_sg, i - start,
417 sgmap, pages, need) < 0)
418 goto error;
419 out++;
420 seg_size = 0;
421 sgmap = sg_next(sgmap);
422 pages = 0;
423 start = i;
424 start_sg = s;
425 }
426 }
427
428 seg_size += s->length;
429 need = nextneed;
430 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
431 ps = s;
432 }
433 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
434 goto error;
435 out++;
436 flush_gart();
437 if (out < nents) {
438 sgmap = sg_next(sgmap);
439 sgmap->dma_length = 0;
440 }
441 return out;
442
443error:
444 flush_gart();
445 gart_unmap_sg(dev, sg, out, dir, NULL);
446
447
448 if (force_iommu || iommu_merge) {
449 out = dma_map_sg_nonforce(dev, sg, nents, dir);
450 if (out > 0)
451 return out;
452 }
453 if (panic_on_overflow)
454 panic("dma_map_sg: overflow on %lu pages\n", pages);
455
456 iommu_full(dev, pages << PAGE_SHIFT, dir);
457 for_each_sg(sg, s, nents, i)
458 s->dma_address = bad_dma_address;
459 return 0;
460}
461
462
463static void *
464gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
465 gfp_t flag)
466{
467 dma_addr_t paddr;
468 unsigned long align_mask;
469 struct page *page;
470
471 if (force_iommu && !(flag & GFP_DMA)) {
472 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
473 page = alloc_pages(flag | __GFP_ZERO, get_order(size));
474 if (!page)
475 return NULL;
476
477 align_mask = (1UL << get_order(size)) - 1;
478 paddr = dma_map_area(dev, page_to_phys(page), size,
479 DMA_BIDIRECTIONAL, align_mask);
480
481 flush_gart();
482 if (paddr != bad_dma_address) {
483 *dma_addr = paddr;
484 return page_address(page);
485 }
486 __free_pages(page, get_order(size));
487 } else
488 return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
489
490 return NULL;
491}
492
493
494static void
495gart_free_coherent(struct device *dev, size_t size, void *vaddr,
496 dma_addr_t dma_addr)
497{
498 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL);
499 free_pages((unsigned long)vaddr, get_order(size));
500}
501
502static int no_agp;
503
504static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
505{
506 unsigned long a;
507
508 if (!iommu_size) {
509 iommu_size = aper_size;
510 if (!no_agp)
511 iommu_size /= 2;
512 }
513
514 a = aper + iommu_size;
515 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
516
517 if (iommu_size < 64*1024*1024) {
518 printk(KERN_WARNING
519 "PCI-DMA: Warning: Small IOMMU %luMB."
520 " Consider increasing the AGP aperture in BIOS\n",
521 iommu_size >> 20);
522 }
523
524 return iommu_size;
525}
526
527static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
528{
529 unsigned aper_size = 0, aper_base_32, aper_order;
530 u64 aper_base;
531
532 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
533 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
534 aper_order = (aper_order >> 1) & 7;
535
536 aper_base = aper_base_32 & 0x7fff;
537 aper_base <<= 25;
538
539 aper_size = (32 * 1024 * 1024) << aper_order;
540 if (aper_base + aper_size > 0x100000000UL || !aper_size)
541 aper_base = 0;
542
543 *size = aper_size;
544 return aper_base;
545}
546
547static void enable_gart_translations(void)
548{
549 int i;
550
551 for (i = 0; i < num_k8_northbridges; i++) {
552 struct pci_dev *dev = k8_northbridges[i];
553
554 enable_gart_translation(dev, __pa(agp_gatt_table));
555 }
556}
557
558
559
560
561
562static bool fix_up_north_bridges;
563static u32 aperture_order;
564static u32 aperture_alloc;
565
566void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
567{
568 fix_up_north_bridges = true;
569 aperture_order = aper_order;
570 aperture_alloc = aper_alloc;
571}
572
573static int gart_resume(struct sys_device *dev)
574{
575 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
576
577 if (fix_up_north_bridges) {
578 int i;
579
580 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
581
582 for (i = 0; i < num_k8_northbridges; i++) {
583 struct pci_dev *dev = k8_northbridges[i];
584
585
586
587
588
589 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
590 aperture_order << 1);
591 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
592 aperture_alloc >> 25);
593 }
594 }
595
596 enable_gart_translations();
597
598 return 0;
599}
600
601static int gart_suspend(struct sys_device *dev, pm_message_t state)
602{
603 return 0;
604}
605
606static struct sysdev_class gart_sysdev_class = {
607 .name = "gart",
608 .suspend = gart_suspend,
609 .resume = gart_resume,
610
611};
612
613static struct sys_device device_gart = {
614 .id = 0,
615 .cls = &gart_sysdev_class,
616};
617
618
619
620
621
622static __init int init_k8_gatt(struct agp_kern_info *info)
623{
624 unsigned aper_size, gatt_size, new_aper_size;
625 unsigned aper_base, new_aper_base;
626 struct pci_dev *dev;
627 void *gatt;
628 int i, error;
629
630 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
631 aper_size = aper_base = info->aper_size = 0;
632 dev = NULL;
633 for (i = 0; i < num_k8_northbridges; i++) {
634 dev = k8_northbridges[i];
635 new_aper_base = read_aperture(dev, &new_aper_size);
636 if (!new_aper_base)
637 goto nommu;
638
639 if (!aper_base) {
640 aper_size = new_aper_size;
641 aper_base = new_aper_base;
642 }
643 if (aper_size != new_aper_size || aper_base != new_aper_base)
644 goto nommu;
645 }
646 if (!aper_base)
647 goto nommu;
648 info->aper_base = aper_base;
649 info->aper_size = aper_size >> 20;
650
651 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
652 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
653 get_order(gatt_size));
654 if (!gatt)
655 panic("Cannot allocate GATT table");
656 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
657 panic("Could not set GART PTEs to uncacheable pages");
658
659 agp_gatt_table = gatt;
660
661 error = sysdev_class_register(&gart_sysdev_class);
662 if (!error)
663 error = sysdev_register(&device_gart);
664 if (error)
665 panic("Could not register gart_sysdev -- "
666 "would corrupt data on next suspend");
667
668 flush_gart();
669
670 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
671 aper_base, aper_size>>10);
672
673 return 0;
674
675 nommu:
676
677 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
678 "falling back to iommu=soft.\n");
679 return -1;
680}
681
682static struct dma_map_ops gart_dma_ops = {
683 .map_sg = gart_map_sg,
684 .unmap_sg = gart_unmap_sg,
685 .map_page = gart_map_page,
686 .unmap_page = gart_unmap_page,
687 .alloc_coherent = gart_alloc_coherent,
688 .free_coherent = gart_free_coherent,
689};
690
691void gart_iommu_shutdown(void)
692{
693 struct pci_dev *dev;
694 int i;
695
696 if (no_agp && (dma_ops != &gart_dma_ops))
697 return;
698
699 for (i = 0; i < num_k8_northbridges; i++) {
700 u32 ctl;
701
702 dev = k8_northbridges[i];
703 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
704
705 ctl &= ~GARTEN;
706
707 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
708 }
709}
710
711void __init gart_iommu_init(void)
712{
713 struct agp_kern_info info;
714 unsigned long iommu_start;
715 unsigned long aper_base, aper_size;
716 unsigned long start_pfn, end_pfn;
717 unsigned long scratch;
718 long i;
719
720 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0)
721 return;
722
723#ifndef CONFIG_AGP_AMD64
724 no_agp = 1;
725#else
726
727
728 no_agp = no_agp ||
729 (agp_amd64_init() < 0) ||
730 (agp_copy_info(agp_bridge, &info) < 0);
731#endif
732
733 if (swiotlb)
734 return;
735
736
737 if (iommu_detected && !gart_iommu_aperture)
738 return;
739
740 if (no_iommu ||
741 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
742 !gart_iommu_aperture ||
743 (no_agp && init_k8_gatt(&info) < 0)) {
744 if (max_pfn > MAX_DMA32_PFN) {
745 printk(KERN_WARNING "More than 4GB of memory "
746 "but GART IOMMU not available.\n");
747 printk(KERN_WARNING "falling back to iommu=soft.\n");
748 }
749 return;
750 }
751
752
753 aper_size = info.aper_size << 20;
754 aper_base = info.aper_base;
755 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
756 if (end_pfn > max_low_pfn_mapped) {
757 start_pfn = (aper_base>>PAGE_SHIFT);
758 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
759 }
760
761 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
762 iommu_size = check_iommu_size(info.aper_base, aper_size);
763 iommu_pages = iommu_size >> PAGE_SHIFT;
764
765 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
766 get_order(iommu_pages/8));
767 if (!iommu_gart_bitmap)
768 panic("Cannot allocate iommu bitmap\n");
769
770#ifdef CONFIG_IOMMU_LEAK
771 if (leak_trace) {
772 int ret;
773
774 ret = dma_debug_resize_entries(iommu_pages);
775 if (ret)
776 printk(KERN_DEBUG
777 "PCI-DMA: Cannot trace all the entries\n");
778 }
779#endif
780
781
782
783
784
785 iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
786
787 agp_memory_reserved = iommu_size;
788 printk(KERN_INFO
789 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
790 iommu_size >> 20);
791
792 iommu_start = aper_size - iommu_size;
793 iommu_bus_base = info.aper_base + iommu_start;
794 bad_dma_address = iommu_bus_base;
795 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
796
797
798
799
800
801
802
803
804
805
806 set_memory_np((unsigned long)__va(iommu_bus_base),
807 iommu_size >> PAGE_SHIFT);
808
809
810
811
812
813
814
815
816 wbinvd();
817
818
819
820
821
822
823
824 enable_gart_translations();
825
826
827
828
829
830
831
832 scratch = get_zeroed_page(GFP_KERNEL);
833 if (!scratch)
834 panic("Cannot allocate iommu scratch page");
835 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
836 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
837 iommu_gatt_base[i] = gart_unmapped_entry;
838
839 flush_gart();
840 dma_ops = &gart_dma_ops;
841}
842
843void __init gart_parse_options(char *p)
844{
845 int arg;
846
847#ifdef CONFIG_IOMMU_LEAK
848 if (!strncmp(p, "leak", 4)) {
849 leak_trace = 1;
850 p += 4;
851 if (*p == '=')
852 ++p;
853 if (isdigit(*p) && get_option(&p, &arg))
854 iommu_leak_pages = arg;
855 }
856#endif
857 if (isdigit(*p) && get_option(&p, &arg))
858 iommu_size = arg;
859 if (!strncmp(p, "fullflush", 8))
860 iommu_fullflush = 1;
861 if (!strncmp(p, "nofullflush", 11))
862 iommu_fullflush = 0;
863 if (!strncmp(p, "noagp", 5))
864 no_agp = 1;
865 if (!strncmp(p, "noaperture", 10))
866 fix_aperture = 0;
867
868 if (!strncmp(p, "force", 5))
869 gart_iommu_aperture_allowed = 1;
870 if (!strncmp(p, "allowed", 7))
871 gart_iommu_aperture_allowed = 1;
872 if (!strncmp(p, "memaper", 7)) {
873 fallback_aper_force = 1;
874 p += 7;
875 if (*p == '=') {
876 ++p;
877 if (get_option(&p, &arg))
878 fallback_aper_order = arg;
879 }
880 }
881}
882