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13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/acpi.h>
16#include <linux/sfi_acpi.h>
17#include <linux/bitmap.h>
18#include <linux/sort.h>
19#include <asm/e820.h>
20#include <asm/pci_x86.h>
21#include <asm/acpi.h>
22
23#define PREFIX "PCI: "
24
25
26#define MMCONFIG_APER_MIN (2 * 1024*1024)
27#define MMCONFIG_APER_MAX (256 * 1024*1024)
28
29
30static int __initdata pci_mmcfg_resources_inserted;
31
32static __init int extend_mmcfg(int num)
33{
34 struct acpi_mcfg_allocation *new;
35 int new_num = pci_mmcfg_config_num + num;
36
37 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
38 if (!new)
39 return -1;
40
41 if (pci_mmcfg_config) {
42 memcpy(new, pci_mmcfg_config,
43 sizeof(pci_mmcfg_config[0]) * new_num);
44 kfree(pci_mmcfg_config);
45 }
46 pci_mmcfg_config = new;
47
48 return 0;
49}
50
51static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
52{
53 int i = pci_mmcfg_config_num;
54
55 pci_mmcfg_config_num++;
56 pci_mmcfg_config[i].address = addr;
57 pci_mmcfg_config[i].pci_segment = segment;
58 pci_mmcfg_config[i].start_bus_number = start;
59 pci_mmcfg_config[i].end_bus_number = end;
60}
61
62static const char __init *pci_mmcfg_e7520(void)
63{
64 u32 win;
65 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
66
67 win = win & 0xf000;
68 if (win == 0x0000 || win == 0xf000)
69 return NULL;
70
71 if (extend_mmcfg(1) == -1)
72 return NULL;
73
74 fill_one_mmcfg(win << 16, 0, 0, 255);
75
76 return "Intel Corporation E7520 Memory Controller Hub";
77}
78
79static const char __init *pci_mmcfg_intel_945(void)
80{
81 u32 pciexbar, mask = 0, len = 0;
82
83 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
84
85
86 if (!(pciexbar & 1))
87 return NULL;
88
89
90 switch ((pciexbar >> 1) & 3) {
91 case 0:
92 mask = 0xf0000000U;
93 len = 0x10000000U;
94 break;
95 case 1:
96 mask = 0xf8000000U;
97 len = 0x08000000U;
98 break;
99 case 2:
100 mask = 0xfc000000U;
101 len = 0x04000000U;
102 break;
103 default:
104 return NULL;
105 }
106
107
108
109
110 if ((pciexbar & mask) & 0x0fffffffU)
111 return NULL;
112
113
114 if ((pciexbar & mask) >= 0xf0000000U)
115 return NULL;
116
117 if (extend_mmcfg(1) == -1)
118 return NULL;
119
120 fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
121
122 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
123}
124
125static const char __init *pci_mmcfg_amd_fam10h(void)
126{
127 u32 low, high, address;
128 u64 base, msr;
129 int i;
130 unsigned segnbits = 0, busnbits;
131
132 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
133 return NULL;
134
135 address = MSR_FAM10H_MMIO_CONF_BASE;
136 if (rdmsr_safe(address, &low, &high))
137 return NULL;
138
139 msr = high;
140 msr <<= 32;
141 msr |= low;
142
143
144 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
145 return NULL;
146
147 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
148
149 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
150 FAM10H_MMIO_CONF_BUSRANGE_MASK;
151
152
153
154
155
156 if (!busnbits)
157 return NULL;
158
159 if (busnbits > 8) {
160 segnbits = busnbits - 8;
161 busnbits = 8;
162 }
163
164 if (extend_mmcfg(1 << segnbits) == -1)
165 return NULL;
166
167 for (i = 0; i < (1 << segnbits); i++)
168 fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
169
170 return "AMD Family 10h NB";
171}
172
173static bool __initdata mcp55_checked;
174static const char __init *pci_mmcfg_nvidia_mcp55(void)
175{
176 int bus;
177 int mcp55_mmconf_found = 0;
178
179 static const u32 extcfg_regnum = 0x90;
180 static const u32 extcfg_regsize = 4;
181 static const u32 extcfg_enable_mask = 1<<31;
182 static const u32 extcfg_start_mask = 0xff<<16;
183 static const int extcfg_start_shift = 16;
184 static const u32 extcfg_size_mask = 0x3<<28;
185 static const int extcfg_size_shift = 28;
186 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
187 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
188 static const int extcfg_base_lshift = 25;
189
190
191
192
193 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
194 return NULL;
195
196 mcp55_checked = true;
197 for (bus = 0; bus < 256; bus++) {
198 u64 base;
199 u32 l, extcfg;
200 u16 vendor, device;
201 int start, size_index, end;
202
203 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
204 vendor = l & 0xffff;
205 device = (l >> 16) & 0xffff;
206
207 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
208 continue;
209
210 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
211 extcfg_regsize, &extcfg);
212
213 if (!(extcfg & extcfg_enable_mask))
214 continue;
215
216 if (extend_mmcfg(1) == -1)
217 continue;
218
219 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
220 base = extcfg & extcfg_base_mask[size_index];
221
222 base <<= extcfg_base_lshift;
223 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
224 end = start + extcfg_sizebus[size_index] - 1;
225 fill_one_mmcfg(base, 0, start, end);
226 mcp55_mmconf_found++;
227 }
228
229 if (!mcp55_mmconf_found)
230 return NULL;
231
232 return "nVidia MCP55";
233}
234
235struct pci_mmcfg_hostbridge_probe {
236 u32 bus;
237 u32 devfn;
238 u32 vendor;
239 u32 device;
240 const char *(*probe)(void);
241};
242
243static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
244 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
245 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
246 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
247 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
248 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
249 0x1200, pci_mmcfg_amd_fam10h },
250 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
251 0x1200, pci_mmcfg_amd_fam10h },
252 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
253 0x0369, pci_mmcfg_nvidia_mcp55 },
254};
255
256static int __init cmp_mmcfg(const void *x1, const void *x2)
257{
258 const typeof(pci_mmcfg_config[0]) *m1 = x1;
259 const typeof(pci_mmcfg_config[0]) *m2 = x2;
260 int start1, start2;
261
262 start1 = m1->start_bus_number;
263 start2 = m2->start_bus_number;
264
265 return start1 - start2;
266}
267
268static void __init pci_mmcfg_check_end_bus_number(void)
269{
270 int i;
271 typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
272
273
274 sort(pci_mmcfg_config, pci_mmcfg_config_num,
275 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
276
277
278 if (pci_mmcfg_config_num > 0) {
279 i = pci_mmcfg_config_num - 1;
280 cfg = &pci_mmcfg_config[i];
281 if (cfg->end_bus_number < cfg->start_bus_number)
282 cfg->end_bus_number = 255;
283 }
284
285
286 for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
287 cfg = &pci_mmcfg_config[i];
288 cfgx = &pci_mmcfg_config[i+1];
289
290 if (cfg->end_bus_number < cfg->start_bus_number)
291 cfg->end_bus_number = 255;
292
293 if (cfg->end_bus_number >= cfgx->start_bus_number)
294 cfg->end_bus_number = cfgx->start_bus_number - 1;
295 }
296}
297
298static int __init pci_mmcfg_check_hostbridge(void)
299{
300 u32 l;
301 u32 bus, devfn;
302 u16 vendor, device;
303 int i;
304 const char *name;
305
306 if (!raw_pci_ops)
307 return 0;
308
309 pci_mmcfg_config_num = 0;
310 pci_mmcfg_config = NULL;
311
312 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
313 bus = pci_mmcfg_probes[i].bus;
314 devfn = pci_mmcfg_probes[i].devfn;
315 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
316 vendor = l & 0xffff;
317 device = (l >> 16) & 0xffff;
318
319 name = NULL;
320 if (pci_mmcfg_probes[i].vendor == vendor &&
321 pci_mmcfg_probes[i].device == device)
322 name = pci_mmcfg_probes[i].probe();
323
324 if (name)
325 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
326 name);
327 }
328
329
330 pci_mmcfg_check_end_bus_number();
331
332 return pci_mmcfg_config_num != 0;
333}
334
335static void __init pci_mmcfg_insert_resources(void)
336{
337#define PCI_MMCFG_RESOURCE_NAME_LEN 24
338 int i;
339 struct resource *res;
340 char *names;
341 unsigned num_buses;
342
343 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
344 pci_mmcfg_config_num, GFP_KERNEL);
345 if (!res) {
346 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
347 return;
348 }
349
350 names = (void *)&res[pci_mmcfg_config_num];
351 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
352 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
353 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
354 res->name = names;
355 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
356 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
357 cfg->start_bus_number, cfg->end_bus_number);
358 res->start = cfg->address + (cfg->start_bus_number << 20);
359 res->end = res->start + (num_buses << 20) - 1;
360 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
361 insert_resource(&iomem_resource, res);
362 names += PCI_MMCFG_RESOURCE_NAME_LEN;
363 }
364
365
366 pci_mmcfg_resources_inserted = 1;
367}
368
369static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
370 void *data)
371{
372 struct resource *mcfg_res = data;
373 struct acpi_resource_address64 address;
374 acpi_status status;
375
376 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
377 struct acpi_resource_fixed_memory32 *fixmem32 =
378 &res->data.fixed_memory32;
379 if (!fixmem32)
380 return AE_OK;
381 if ((mcfg_res->start >= fixmem32->address) &&
382 (mcfg_res->end < (fixmem32->address +
383 fixmem32->address_length))) {
384 mcfg_res->flags = 1;
385 return AE_CTRL_TERMINATE;
386 }
387 }
388 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
389 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
390 return AE_OK;
391
392 status = acpi_resource_to_address64(res, &address);
393 if (ACPI_FAILURE(status) ||
394 (address.address_length <= 0) ||
395 (address.resource_type != ACPI_MEMORY_RANGE))
396 return AE_OK;
397
398 if ((mcfg_res->start >= address.minimum) &&
399 (mcfg_res->end < (address.minimum + address.address_length))) {
400 mcfg_res->flags = 1;
401 return AE_CTRL_TERMINATE;
402 }
403 return AE_OK;
404}
405
406static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
407 void *context, void **rv)
408{
409 struct resource *mcfg_res = context;
410
411 acpi_walk_resources(handle, METHOD_NAME__CRS,
412 check_mcfg_resource, context);
413
414 if (mcfg_res->flags)
415 return AE_CTRL_TERMINATE;
416
417 return AE_OK;
418}
419
420static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
421{
422 struct resource mcfg_res;
423
424 mcfg_res.start = start;
425 mcfg_res.end = end - 1;
426 mcfg_res.flags = 0;
427
428 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
429
430 if (!mcfg_res.flags)
431 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
432 NULL);
433
434 return mcfg_res.flags;
435}
436
437typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
438
439static int __init is_mmconf_reserved(check_reserved_t is_reserved,
440 u64 addr, u64 size, int i,
441 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
442{
443 u64 old_size = size;
444 int valid = 0;
445
446 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
447 size >>= 1;
448 if (size < (16UL<<20))
449 break;
450 }
451
452 if (size >= (16UL<<20) || size == old_size) {
453 printk(KERN_NOTICE
454 "PCI: MCFG area at %Lx reserved in %s\n",
455 addr, with_e820?"E820":"ACPI motherboard resources");
456 valid = 1;
457
458 if (old_size != size) {
459
460 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
461 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
462 "segment %hu buses %u - %u\n",
463 i, (unsigned long)cfg->address, cfg->pci_segment,
464 (unsigned int)cfg->start_bus_number,
465 (unsigned int)cfg->end_bus_number);
466 }
467 }
468
469 return valid;
470}
471
472static void __init pci_mmcfg_reject_broken(int early)
473{
474 typeof(pci_mmcfg_config[0]) *cfg;
475 int i;
476
477 if ((pci_mmcfg_config_num == 0) ||
478 (pci_mmcfg_config == NULL) ||
479 (pci_mmcfg_config[0].address == 0))
480 return;
481
482 for (i = 0; i < pci_mmcfg_config_num; i++) {
483 int valid = 0;
484 u64 addr, size;
485
486 cfg = &pci_mmcfg_config[i];
487 addr = cfg->start_bus_number;
488 addr <<= 20;
489 addr += cfg->address;
490 size = cfg->end_bus_number + 1 - cfg->start_bus_number;
491 size <<= 20;
492 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
493 "segment %hu buses %u - %u\n",
494 i, (unsigned long)cfg->address, cfg->pci_segment,
495 (unsigned int)cfg->start_bus_number,
496 (unsigned int)cfg->end_bus_number);
497
498 if (!early && !acpi_disabled)
499 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
500
501 if (valid)
502 continue;
503
504 if (!early)
505 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
506 " reserved in ACPI motherboard resources\n",
507 cfg->address);
508
509
510
511 if (raw_pci_ops)
512 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
513
514 if (!valid)
515 goto reject;
516 }
517
518 return;
519
520reject:
521 printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
522 pci_mmcfg_arch_free();
523 kfree(pci_mmcfg_config);
524 pci_mmcfg_config = NULL;
525 pci_mmcfg_config_num = 0;
526}
527
528static int __initdata known_bridge;
529
530static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
531
532
533struct acpi_mcfg_allocation *pci_mmcfg_config;
534int pci_mmcfg_config_num;
535
536static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
537{
538 if (!strcmp(mcfg->header.oem_id, "SGI"))
539 acpi_mcfg_64bit_base_addr = TRUE;
540
541 return 0;
542}
543
544static int __init pci_parse_mcfg(struct acpi_table_header *header)
545{
546 struct acpi_table_mcfg *mcfg;
547 unsigned long i;
548 int config_size;
549
550 if (!header)
551 return -EINVAL;
552
553 mcfg = (struct acpi_table_mcfg *)header;
554
555
556 pci_mmcfg_config_num = 0;
557 i = header->length - sizeof(struct acpi_table_mcfg);
558 while (i >= sizeof(struct acpi_mcfg_allocation)) {
559 ++pci_mmcfg_config_num;
560 i -= sizeof(struct acpi_mcfg_allocation);
561 };
562 if (pci_mmcfg_config_num == 0) {
563 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
564 return -ENODEV;
565 }
566
567 config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
568 pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
569 if (!pci_mmcfg_config) {
570 printk(KERN_WARNING PREFIX
571 "No memory for MCFG config tables\n");
572 return -ENOMEM;
573 }
574
575 memcpy(pci_mmcfg_config, &mcfg[1], config_size);
576
577 acpi_mcfg_oem_check(mcfg);
578
579 for (i = 0; i < pci_mmcfg_config_num; ++i) {
580 if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) &&
581 !acpi_mcfg_64bit_base_addr) {
582 printk(KERN_ERR PREFIX
583 "MMCONFIG not in low 4GB of memory\n");
584 kfree(pci_mmcfg_config);
585 pci_mmcfg_config_num = 0;
586 return -ENODEV;
587 }
588 }
589
590 return 0;
591}
592
593static void __init __pci_mmcfg_init(int early)
594{
595
596 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
597 return;
598
599
600 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
601 return;
602
603
604 if (known_bridge)
605 return;
606
607 if (early) {
608 if (pci_mmcfg_check_hostbridge())
609 known_bridge = 1;
610 }
611
612 if (!known_bridge)
613 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
614
615 pci_mmcfg_reject_broken(early);
616
617 if ((pci_mmcfg_config_num == 0) ||
618 (pci_mmcfg_config == NULL) ||
619 (pci_mmcfg_config[0].address == 0))
620 return;
621
622 if (pci_mmcfg_arch_init())
623 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
624 else {
625
626
627
628
629 pci_mmcfg_resources_inserted = 1;
630 }
631}
632
633void __init pci_mmcfg_early_init(void)
634{
635 __pci_mmcfg_init(1);
636}
637
638void __init pci_mmcfg_late_init(void)
639{
640 __pci_mmcfg_init(0);
641}
642
643static int __init pci_mmcfg_late_insert_resources(void)
644{
645
646
647
648
649 if ((pci_mmcfg_resources_inserted == 1) ||
650 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
651 (pci_mmcfg_config_num == 0) ||
652 (pci_mmcfg_config == NULL) ||
653 (pci_mmcfg_config[0].address == 0))
654 return 1;
655
656
657
658
659
660
661 pci_mmcfg_insert_resources();
662
663 return 0;
664}
665
666
667
668
669
670
671late_initcall(pci_mmcfg_late_insert_resources);
672
