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13#ifndef _XTENSA_ATOMIC_H
14#define _XTENSA_ATOMIC_H
15
16#include <linux/stringify.h>
17#include <linux/types.h>
18
19#ifdef __KERNEL__
20#include <asm/processor.h>
21#include <asm/system.h>
22
23#define ATOMIC_INIT(i) { (i) }
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49#define atomic_read(v) ((v)->counter)
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58#define atomic_set(v,i) ((v)->counter = (i))
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67static inline void atomic_add(int i, atomic_t * v)
68{
69 unsigned int vval;
70
71 __asm__ __volatile__(
72 "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
73 "l32i %0, %2, 0 \n\t"
74 "add %0, %0, %1 \n\t"
75 "s32i %0, %2, 0 \n\t"
76 "wsr a15, "__stringify(PS)" \n\t"
77 "rsync \n"
78 : "=&a" (vval)
79 : "a" (i), "a" (v)
80 : "a15", "memory"
81 );
82}
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90
91static inline void atomic_sub(int i, atomic_t *v)
92{
93 unsigned int vval;
94
95 __asm__ __volatile__(
96 "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
97 "l32i %0, %2, 0 \n\t"
98 "sub %0, %0, %1 \n\t"
99 "s32i %0, %2, 0 \n\t"
100 "wsr a15, "__stringify(PS)" \n\t"
101 "rsync \n"
102 : "=&a" (vval)
103 : "a" (i), "a" (v)
104 : "a15", "memory"
105 );
106}
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111
112static inline int atomic_add_return(int i, atomic_t * v)
113{
114 unsigned int vval;
115
116 __asm__ __volatile__(
117 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
118 "l32i %0, %2, 0 \n\t"
119 "add %0, %0, %1 \n\t"
120 "s32i %0, %2, 0 \n\t"
121 "wsr a15, "__stringify(PS)" \n\t"
122 "rsync \n"
123 : "=&a" (vval)
124 : "a" (i), "a" (v)
125 : "a15", "memory"
126 );
127
128 return vval;
129}
130
131static inline int atomic_sub_return(int i, atomic_t * v)
132{
133 unsigned int vval;
134
135 __asm__ __volatile__(
136 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
137 "l32i %0, %2, 0 \n\t"
138 "sub %0, %0, %1 \n\t"
139 "s32i %0, %2, 0 \n\t"
140 "wsr a15, "__stringify(PS)" \n\t"
141 "rsync \n"
142 : "=&a" (vval)
143 : "a" (i), "a" (v)
144 : "a15", "memory"
145 );
146
147 return vval;
148}
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159#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
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167#define atomic_inc(v) atomic_add(1,(v))
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175#define atomic_inc_return(v) atomic_add_return(1,(v))
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183#define atomic_dec(v) atomic_sub(1,(v))
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191#define atomic_dec_return(v) atomic_sub_return(1,(v))
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201#define atomic_dec_and_test(v) (atomic_sub_return(1,(v)) == 0)
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211#define atomic_inc_and_test(v) (atomic_add_return(1,(v)) == 0)
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222#define atomic_add_negative(i,v) (atomic_add_return((i),(v)) < 0)
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224#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
225#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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236static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
237{
238 int c, old;
239 c = atomic_read(v);
240 for (;;) {
241 if (unlikely(c == (u)))
242 break;
243 old = atomic_cmpxchg((v), c, c + (a));
244 if (likely(old == c))
245 break;
246 c = old;
247 }
248 return c != (u);
249}
250
251#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
252
253static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
254{
255 unsigned int all_f = -1;
256 unsigned int vval;
257
258 __asm__ __volatile__(
259 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
260 "l32i %0, %2, 0 \n\t"
261 "xor %1, %4, %3 \n\t"
262 "and %0, %0, %4 \n\t"
263 "s32i %0, %2, 0 \n\t"
264 "wsr a15, "__stringify(PS)" \n\t"
265 "rsync \n"
266 : "=&a" (vval), "=a" (mask)
267 : "a" (v), "a" (all_f), "1" (mask)
268 : "a15", "memory"
269 );
270}
271
272static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
273{
274 unsigned int vval;
275
276 __asm__ __volatile__(
277 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
278 "l32i %0, %2, 0 \n\t"
279 "or %0, %0, %1 \n\t"
280 "s32i %0, %2, 0 \n\t"
281 "wsr a15, "__stringify(PS)" \n\t"
282 "rsync \n"
283 : "=&a" (vval)
284 : "a" (mask), "a" (v)
285 : "a15", "memory"
286 );
287}
288
289
290#define smp_mb__before_atomic_dec() barrier()
291#define smp_mb__after_atomic_dec() barrier()
292#define smp_mb__before_atomic_inc() barrier()
293#define smp_mb__after_atomic_inc() barrier()
294
295#include <asm-generic/atomic-long.h>
296#endif
297
298#endif
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