1/* 2 * arch/xtensa/kernel/head.S 3 * 4 * Xtensa Processor startup code. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 2001 - 2005 Tensilica Inc. 11 * 12 * Chris Zankel <chris@zankel.net> 13 * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca> 14 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 15 * Kevin Chea 16 */ 17 18#include <asm/processor.h> 19#include <asm/page.h> 20#include <asm/cacheasm.h> 21 22#include <linux/init.h> 23#include <linux/linkage.h> 24 25/* 26 * This module contains the entry code for kernel images. It performs the 27 * minimal setup needed to call the generic C routines. 28 * 29 * Prerequisites: 30 * 31 * - The kernel image has been loaded to the actual address where it was 32 * compiled to. 33 * - a2 contains either 0 or a pointer to a list of boot parameters. 34 * (see setup.c for more details) 35 * 36 */ 37 38/* 39 * _start 40 * 41 * The bootloader passes a pointer to a list of boot parameters in a2. 42 */ 43 44 /* The first bytes of the kernel image must be an instruction, so we 45 * manually allocate and define the literal constant we need for a jx 46 * instruction. 47 */ 48 49 __HEAD 50 .globl _start 51_start: _j 2f 52 .align 4 531: .word _startup 542: l32r a0, 1b 55 jx a0 56 57 .section .init.text, "ax" 58 .align 4 59_startup: 60 61 /* Disable interrupts and exceptions. */ 62 63 movi a0, LOCKLEVEL 64 wsr a0, PS 65 66 /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ 67 68 wsr a2, EXCSAVE_1 69 70 /* Start with a fresh windowbase and windowstart. */ 71 72 movi a1, 1 73 movi a0, 0 74 wsr a1, WINDOWSTART 75 wsr a0, WINDOWBASE 76 rsync 77 78 /* Set a0 to 0 for the remaining initialization. */ 79 80 movi a0, 0 81 82 /* Clear debugging registers. */ 83 84#if XCHAL_HAVE_DEBUG 85 wsr a0, IBREAKENABLE 86 wsr a0, ICOUNT 87 movi a1, 15 88 wsr a0, ICOUNTLEVEL 89 90 .set _index, 0 91 .rept XCHAL_NUM_DBREAK - 1 92 wsr a0, DBREAKC + _index 93 .set _index, _index + 1 94 .endr 95#endif 96 97 /* Clear CCOUNT (not really necessary, but nice) */ 98 99 wsr a0, CCOUNT # not really necessary, but nice 100 101 /* Disable zero-loops. */ 102 103#if XCHAL_HAVE_LOOPS 104 wsr a0, LCOUNT 105#endif 106 107 /* Disable all timers. */ 108 109 .set _index, 0 110 .rept XCHAL_NUM_TIMERS - 1 111 wsr a0, CCOMPARE + _index 112 .set _index, _index + 1 113 .endr 114 115 /* Interrupt initialization. */ 116 117 movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE 118 wsr a0, INTENABLE 119 wsr a2, INTCLEAR 120 121 /* Disable coprocessors. */ 122 123#if XCHAL_CP_NUM > 0 124 wsr a0, CPENABLE 125#endif 126 127 /* Set PS.INTLEVEL=1, PS.WOE=0, kernel stack, PS.EXCM=0 128 * 129 * Note: PS.EXCM must be cleared before using any loop 130 * instructions; otherwise, they are silently disabled, and 131 * at most one iteration of the loop is executed. 132 */ 133 134 movi a1, 1 135 wsr a1, PS 136 rsync 137 138 /* Initialize the caches. 139 * a2, a3 are just working registers (clobbered). 140 */ 141 142#if XCHAL_DCACHE_LINE_LOCKABLE 143 ___unlock_dcache_all a2 a3 144#endif 145 146#if XCHAL_ICACHE_LINE_LOCKABLE 147 ___unlock_icache_all a2 a3 148#endif 149 150 ___invalidate_dcache_all a2 a3 151 ___invalidate_icache_all a2 a3 152 153 isync 154 155 /* Unpack data sections 156 * 157 * The linker script used to build the Linux kernel image 158 * creates a table located at __boot_reloc_table_start 159 * that contans the information what data needs to be unpacked. 160 * 161 * Uses a2-a7. 162 */ 163 164 movi a2, __boot_reloc_table_start 165 movi a3, __boot_reloc_table_end 166 1671: beq a2, a3, 3f # no more entries? 168 l32i a4, a2, 0 # start destination (in RAM) 169 l32i a5, a2, 4 # end desination (in RAM) 170 l32i a6, a2, 8 # start source (in ROM) 171 addi a2, a2, 12 # next entry 172 beq a4, a5, 1b # skip, empty entry 173 beq a4, a6, 1b # skip, source and dest. are the same 174 1752: l32i a7, a6, 0 # load word 176 addi a6, a6, 4 177 s32i a7, a4, 0 # store word 178 addi a4, a4, 4 179 bltu a4, a5, 2b 180 j 1b 181 1823: 183 /* All code and initialized data segments have been copied. 184 * Now clear the BSS segment. 185 */ 186 187 movi a2, _bss_start # start of BSS 188 movi a3, _bss_end # end of BSS 189 190 __loopt a2, a3, a4, 2 191 s32i a0, a2, 0 192 __endla a2, a4, 4 193 194#if XCHAL_DCACHE_IS_WRITEBACK 195 196 /* After unpacking, flush the writeback cache to memory so the 197 * instructions/data are available. 198 */ 199 200 ___flush_dcache_all a2 a3 201#endif 202 203 /* Setup stack and enable window exceptions (keep irqs disabled) */ 204 205 movi a1, init_thread_union 206 addi a1, a1, KERNEL_STACK_SIZE 207 208 movi a2, 0x00040001 # WOE=1, INTLEVEL=1, UM=0 209 wsr a2, PS # (enable reg-windows; progmode stack) 210 rsync 211 212 /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/ 213 214 movi a2, debug_exception 215 wsr a2, EXCSAVE + XCHAL_DEBUGLEVEL 216 217 /* Set up EXCSAVE[1] to point to the exc_table. */ 218 219 movi a6, exc_table 220 xsr a6, EXCSAVE_1 221 222 /* init_arch kick-starts the linux kernel */ 223 224 movi a4, init_arch 225 callx4 a4 226 227 movi a4, start_kernel 228 callx4 a4 229 230should_never_return: 231 j should_never_return 232 233 234/* 235 * BSS section 236 */ 237 238__PAGE_ALIGNED_BSS 239#ifdef CONFIG_MMU 240ENTRY(swapper_pg_dir) 241 .fill PAGE_SIZE, 1, 0 242#endif 243ENTRY(empty_zero_page) 244 .fill PAGE_SIZE, 1, 0 245