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11#define DEBUG
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <scsi/scsi_host.h>
22#include <linux/ata.h>
23#include <linux/libata.h>
24#include <linux/err.h>
25#include <linux/io.h>
26
27#include <mach/board.h>
28#include <mach/smc.h>
29
30#define DRV_NAME "pata_at32"
31#define DRV_VERSION "0.0.3"
32
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45
46
47#define CF_IDE_OFFSET 0x00c00000
48#define CF_ALT_IDE_OFFSET 0x00e00000
49#define CF_RES_SIZE 2048
50
51
52
53
54
55#undef DEBUG_BUS
56
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68
69
70enum {
71 PIO_MASK = ATA_PIO4,
72};
73
74
75
76
77struct at32_ide_info {
78 unsigned int irq;
79 struct resource res_ide;
80 struct resource res_alt;
81 void __iomem *ide_addr;
82 void __iomem *alt_addr;
83 unsigned int cs;
84 struct smc_config smc;
85};
86
87
88
89
90static int pata_at32_setup_timing(struct device *dev,
91 struct at32_ide_info *info,
92 const struct ata_timing *ata)
93{
94 struct smc_config *smc = &info->smc;
95 struct smc_timing timing;
96
97 int active;
98 int recover;
99
100 memset(&timing, 0, sizeof(struct smc_timing));
101
102
103 timing.read_cycle = ata->cyc8b;
104
105
106 timing.nrd_setup = ata->setup;
107 timing.nrd_pulse = ata->act8b;
108 timing.nrd_recover = ata->rec8b;
109
110
111 smc_set_timing(smc, &timing);
112
113
114 smc->nrd_setup = smc->nrd_setup + 1;
115
116 active = smc->nrd_setup + smc->nrd_pulse;
117 recover = smc->read_cycle - active;
118
119
120 if (recover < 2)
121 smc->read_cycle = active + 2;
122
123
124 smc->ncs_read_setup = 1;
125 smc->ncs_read_pulse = smc->read_cycle - 2;
126
127
128 smc->write_cycle = smc->read_cycle;
129 smc->nwe_setup = smc->nrd_setup;
130 smc->nwe_pulse = smc->nrd_pulse;
131 smc->ncs_write_setup = smc->ncs_read_setup;
132 smc->ncs_write_pulse = smc->ncs_read_pulse;
133
134
135 dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
136 ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
137
138 dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
139 smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
140 smc->ncs_read_setup, smc->ncs_read_pulse);
141
142
143 return smc_set_configuration(info->cs, smc);
144}
145
146
147
148
149static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
150{
151 struct ata_timing timing;
152 struct at32_ide_info *info = ap->host->private_data;
153
154 int ret;
155
156
157 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
158 if (ret) {
159 dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
160 return;
161 }
162
163
164 ret = pata_at32_setup_timing(ap->dev, info, &timing);
165 if (ret) {
166 dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
167 return;
168 }
169}
170
171static struct scsi_host_template at32_sht = {
172 ATA_PIO_SHT(DRV_NAME),
173};
174
175static struct ata_port_operations at32_port_ops = {
176 .inherits = &ata_sff_port_ops,
177 .cable_detect = ata_cable_40wire,
178 .set_piomode = pata_at32_set_piomode,
179};
180
181static int __init pata_at32_init_one(struct device *dev,
182 struct at32_ide_info *info)
183{
184 struct ata_host *host;
185 struct ata_port *ap;
186
187 host = ata_host_alloc(dev, 1);
188 if (!host)
189 return -ENOMEM;
190
191 ap = host->ports[0];
192
193
194 ap->ops = &at32_port_ops;
195 ap->pio_mask = PIO_MASK;
196 ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
197
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209
210 ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
211 ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1);
212
213 ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1);
214 ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1);
215 ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1);
216 ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1);
217 ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1);
218 ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1);
219 ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1);
220 ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1);
221 ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1);
222 ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1);
223
224
225 host->private_data = info;
226
227
228 return ata_host_activate(host, info->irq, ata_sff_interrupt,
229 IRQF_SHARED | IRQF_TRIGGER_RISING,
230 &at32_sht);
231}
232
233
234
235
236
237#ifdef DEBUG_BUS
238
239static void __init pata_at32_debug_bus(struct device *dev,
240 struct at32_ide_info *info)
241{
242 const int d1 = 0xff;
243 const int d2 = 0x00;
244
245 int i;
246
247
248 iowrite8(d1, info->alt_addr + (0x06 << 1));
249 iowrite8(d2, info->alt_addr + (0x06 << 1));
250
251 for (i = 0; i < 8; i++) {
252 iowrite8(d1, info->ide_addr + (i << 1));
253 iowrite8(d2, info->ide_addr + (i << 1));
254 }
255
256
257 iowrite16(d1, info->ide_addr);
258 iowrite16(d1 << 8, info->ide_addr);
259
260 iowrite16(d1, info->ide_addr);
261 iowrite16(d1 << 8, info->ide_addr);
262}
263
264#endif
265
266static int __init pata_at32_probe(struct platform_device *pdev)
267{
268 const struct ata_timing initial_timing =
269 {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
270
271 struct device *dev = &pdev->dev;
272 struct at32_ide_info *info;
273 struct ide_platform_data *board = pdev->dev.platform_data;
274 struct resource *res;
275
276 int irq;
277 int ret;
278
279 if (!board)
280 return -ENXIO;
281
282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
283 if (!res)
284 return -ENXIO;
285
286
287 irq = platform_get_irq(pdev, 0);
288 if (irq < 0)
289 return irq;
290
291
292 info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
293 if (!info)
294 return -ENOMEM;
295
296 info->irq = irq;
297 info->cs = board->cs;
298
299
300 info->res_ide.start = res->start + CF_IDE_OFFSET;
301 info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1;
302 info->res_ide.name = "ide";
303 info->res_ide.flags = IORESOURCE_MEM;
304
305 ret = request_resource(res, &info->res_ide);
306 if (ret)
307 goto err_req_res_ide;
308
309 info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
310 info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1;
311 info->res_alt.name = "alt";
312 info->res_alt.flags = IORESOURCE_MEM;
313
314 ret = request_resource(res, &info->res_alt);
315 if (ret)
316 goto err_req_res_alt;
317
318
319 info->smc.bus_width = 2;
320 info->smc.nrd_controlled = 1;
321 info->smc.nwe_controlled = 0;
322 info->smc.nwait_mode = 3;
323 info->smc.byte_write = 0;
324 info->smc.tdf_mode = 0;
325 info->smc.tdf_cycles = 0;
326
327
328 ret = pata_at32_setup_timing(dev, info, &initial_timing);
329 if (ret)
330 goto err_setup_timing;
331
332
333 ret = -ENOMEM;
334 info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
335 info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
336 if (!info->ide_addr || !info->alt_addr)
337 goto err_ioremap;
338
339#ifdef DEBUG_BUS
340 pata_at32_debug_bus(dev, info);
341#endif
342
343
344 ret = pata_at32_init_one(dev, info);
345 if (ret)
346 goto err_ata_device;
347
348 return 0;
349
350 err_ata_device:
351 err_ioremap:
352 err_setup_timing:
353 release_resource(&info->res_alt);
354 err_req_res_alt:
355 release_resource(&info->res_ide);
356 err_req_res_ide:
357 kfree(info);
358
359 return ret;
360}
361
362static int __exit pata_at32_remove(struct platform_device *pdev)
363{
364 struct ata_host *host = platform_get_drvdata(pdev);
365 struct at32_ide_info *info;
366
367 if (!host)
368 return 0;
369
370 info = host->private_data;
371 ata_host_detach(host);
372
373 if (!info)
374 return 0;
375
376 release_resource(&info->res_ide);
377 release_resource(&info->res_alt);
378
379 kfree(info);
380
381 return 0;
382}
383
384
385MODULE_ALIAS("platform:at32_ide");
386
387static struct platform_driver pata_at32_driver = {
388 .remove = __exit_p(pata_at32_remove),
389 .driver = {
390 .name = "at32_ide",
391 .owner = THIS_MODULE,
392 },
393};
394
395static int __init pata_at32_init(void)
396{
397 return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
398}
399
400static void __exit pata_at32_exit(void)
401{
402 platform_driver_unregister(&pata_at32_driver);
403}
404
405module_init(pata_at32_init);
406module_exit(pata_at32_exit);
407
408MODULE_LICENSE("GPL");
409MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
410MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
411MODULE_VERSION(DRV_VERSION);
412