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17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME "pata_hpt37x"
27#define DRV_VERSION "0.6.12"
28
29struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32};
33
34struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38};
39
40
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62
63static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 },
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
71
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
75
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
81};
82
83static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
91
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
95
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
101};
102
103static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 },
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
111
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
115
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
121};
122
123
124static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
128 hpt37x_timings_33,
129 NULL,
130 NULL,
131 NULL
132 }
133};
134
135static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
139 hpt37x_timings_33,
140 NULL,
141 hpt37x_timings_50,
142 NULL
143 }
144};
145
146static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
150 hpt37x_timings_33,
151 NULL,
152 hpt37x_timings_50,
153 hpt37x_timings_66
154 }
155};
156
157static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
161 hpt37x_timings_33,
162 NULL,
163 hpt37x_timings_50,
164 hpt37x_timings_66
165 }
166};
167
168static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
172 hpt37x_timings_33,
173 NULL,
174 hpt37x_timings_50,
175 hpt37x_timings_66
176 }
177};
178
179static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
183 hpt37x_timings_33,
184 NULL,
185 hpt37x_timings_50,
186 hpt37x_timings_66
187 }
188};
189
190static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
194 hpt37x_timings_33,
195 NULL,
196 NULL,
197 NULL
198 }
199};
200
201
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207
208
209
210static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
213
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU;
221}
222
223static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224{
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
226 int i = 0;
227
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
229
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239}
240
241static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250};
251
252static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269};
270
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276
277
278static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
279{
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
285 }
286 return ata_bmdma_mode_filter(adev, mask);
287}
288
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294
295
296static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
297{
298 if (adev->class == ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
301 }
302 return ata_bmdma_mode_filter(adev, mask);
303}
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312
313static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
314{
315 u8 scr2, ata66;
316 struct ata_port *ap = link->ap;
317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
318 static const struct pci_bits hpt37x_enable_bits[] = {
319 { 0x50, 1, 0x04, 0x04 },
320 { 0x54, 1, 0x04, 0x04 }
321 };
322 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
323 return -ENOENT;
324
325 pci_read_config_byte(pdev, 0x5B, &scr2);
326 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
327
328 pci_read_config_byte(pdev, 0x5A, &ata66);
329
330 pci_write_config_byte(pdev, 0x5B, scr2);
331
332 if (ata66 & (2 >> ap->port_no))
333 ap->cbl = ATA_CBL_PATA40;
334 else
335 ap->cbl = ATA_CBL_PATA80;
336
337
338 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
339 udelay(100);
340
341 return ata_sff_prereset(link, deadline);
342}
343
344static int hpt374_fn1_pre_reset(struct ata_link *link, unsigned long deadline)
345{
346 static const struct pci_bits hpt37x_enable_bits[] = {
347 { 0x50, 1, 0x04, 0x04 },
348 { 0x54, 1, 0x04, 0x04 }
349 };
350 u16 mcr3;
351 u8 ata66;
352 struct ata_port *ap = link->ap;
353 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
354 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
355
356 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
357 return -ENOENT;
358
359
360 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
361
362
363 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
364 pci_read_config_byte(pdev, 0x5A, &ata66);
365
366 pci_write_config_word(pdev, mcrbase + 2, mcr3);
367
368 if (ata66 & (2 >> ap->port_no))
369 ap->cbl = ATA_CBL_PATA40;
370 else
371 ap->cbl = ATA_CBL_PATA80;
372
373
374 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
375 udelay(100);
376
377 return ata_sff_prereset(link, deadline);
378}
379
380
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386
387
388static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
389{
390 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
391 u32 addr1, addr2;
392 u32 reg;
393 u32 mode;
394 u8 fast;
395
396 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
397 addr2 = 0x51 + 4 * ap->port_no;
398
399
400 pci_read_config_byte(pdev, addr2, &fast);
401 fast &= ~0x02;
402 fast |= 0x01;
403 pci_write_config_byte(pdev, addr2, fast);
404
405 pci_read_config_dword(pdev, addr1, ®);
406 mode = hpt37x_find_mode(ap, adev->pio_mode);
407 mode &= ~0x8000000;
408 mode &= ~0x30070000;
409 reg &= 0x30070000;
410 pci_write_config_dword(pdev, addr1, reg | mode);
411}
412
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420
421
422static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
423{
424 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
425 u32 addr1, addr2;
426 u32 reg;
427 u32 mode;
428 u8 fast;
429
430 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
431 addr2 = 0x51 + 4 * ap->port_no;
432
433
434 pci_read_config_byte(pdev, addr2, &fast);
435 fast &= ~0x02;
436 fast |= 0x01;
437 pci_write_config_byte(pdev, addr2, fast);
438
439 pci_read_config_dword(pdev, addr1, ®);
440 mode = hpt37x_find_mode(ap, adev->dma_mode);
441 mode |= 0x8000000;
442 mode &= ~0xC0000000;
443 reg &= 0xC0000000;
444 pci_write_config_dword(pdev, addr1, reg | mode);
445}
446
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448
449
450
451
452
453
454static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
455{
456 struct ata_port *ap = qc->ap;
457 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
458 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
459 u8 dma_cmd;
460 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
461
462 if (dma_stat & 0x01) {
463 udelay(20);
464 dma_stat = ioread8(bmdma + 2);
465 }
466 if (dma_stat & 0x01) {
467
468 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
469 udelay(10);
470
471 dma_cmd = ioread8(bmdma );
472 iowrite8(dma_cmd & 0xFE, bmdma);
473
474 dma_stat = ioread8(bmdma + 2);
475 iowrite8(dma_stat | 0x06 , bmdma + 2);
476
477 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
478 udelay(10);
479 }
480 ata_bmdma_stop(qc);
481}
482
483
484
485
486
487
488
489
490
491static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
492{
493 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
494 u32 addr1, addr2;
495 u32 reg;
496 u32 mode;
497 u8 fast;
498
499 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
500 addr2 = 0x51 + 4 * ap->port_no;
501
502
503 pci_read_config_byte(pdev, addr2, &fast);
504 fast &= ~0x07;
505 pci_write_config_byte(pdev, addr2, fast);
506
507 pci_read_config_dword(pdev, addr1, ®);
508 mode = hpt37x_find_mode(ap, adev->pio_mode);
509
510 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
511 mode &= ~0x80000000;
512 mode &= ~0x30070000;
513 reg &= 0x30070000;
514 pci_write_config_dword(pdev, addr1, reg | mode);
515}
516
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524
525
526static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
527{
528 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
529 u32 addr1, addr2;
530 u32 reg;
531 u32 mode;
532 u8 fast;
533
534 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
535 addr2 = 0x51 + 4 * ap->port_no;
536
537
538 pci_read_config_byte(pdev, addr2, &fast);
539 fast &= ~0x07;
540 pci_write_config_byte(pdev, addr2, fast);
541
542 pci_read_config_dword(pdev, addr1, ®);
543 mode = hpt37x_find_mode(ap, adev->dma_mode);
544 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
545 mode &= ~0xC0000000;
546 mode |= 0x80000000;
547 reg &= 0xC0000000;
548 pci_write_config_dword(pdev, addr1, reg | mode);
549}
550
551
552
553
554
555
556
557
558static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
559{
560 struct ata_port *ap = qc->ap;
561 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
562 int mscreg = 0x50 + 4 * ap->port_no;
563 u8 bwsr_stat, msc_stat;
564
565 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
566 pci_read_config_byte(pdev, mscreg, &msc_stat);
567 if (bwsr_stat & (1 << ap->port_no))
568 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
569 ata_bmdma_stop(qc);
570}
571
572
573static struct scsi_host_template hpt37x_sht = {
574 ATA_BMDMA_SHT(DRV_NAME),
575};
576
577
578
579
580
581static struct ata_port_operations hpt370_port_ops = {
582 .inherits = &ata_bmdma_port_ops,
583
584 .bmdma_stop = hpt370_bmdma_stop,
585
586 .mode_filter = hpt370_filter,
587 .set_piomode = hpt370_set_piomode,
588 .set_dmamode = hpt370_set_dmamode,
589 .prereset = hpt37x_pre_reset,
590};
591
592
593
594
595
596static struct ata_port_operations hpt370a_port_ops = {
597 .inherits = &hpt370_port_ops,
598 .mode_filter = hpt370a_filter,
599};
600
601
602
603
604
605
606static struct ata_port_operations hpt372_port_ops = {
607 .inherits = &ata_bmdma_port_ops,
608
609 .bmdma_stop = hpt37x_bmdma_stop,
610
611 .set_piomode = hpt372_set_piomode,
612 .set_dmamode = hpt372_set_dmamode,
613 .prereset = hpt37x_pre_reset,
614};
615
616
617
618
619
620
621static struct ata_port_operations hpt374_fn1_port_ops = {
622 .inherits = &hpt372_port_ops,
623 .prereset = hpt374_fn1_pre_reset,
624};
625
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629
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631
632
633
634
635static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
636{
637 unsigned int f = (base * freq) / 192;
638 if (f < 40)
639 return 0;
640 if (f < 45)
641 return 1;
642 if (f < 55)
643 return 2;
644 return 3;
645}
646
647
648
649
650
651
652
653
654
655static int hpt37x_calibrate_dpll(struct pci_dev *dev)
656{
657 u8 reg5b;
658 u32 reg5c;
659 int tries;
660
661 for(tries = 0; tries < 0x5000; tries++) {
662 udelay(50);
663 pci_read_config_byte(dev, 0x5b, ®5b);
664 if (reg5b & 0x80) {
665
666 for(tries = 0; tries < 0x1000; tries ++) {
667 pci_read_config_byte(dev, 0x5b, ®5b);
668
669 if ((reg5b & 0x80) == 0)
670 return 0;
671 }
672
673 pci_read_config_dword(dev, 0x5c, ®5c);
674 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
675 return 1;
676 }
677 }
678
679 return 0;
680}
681
682static u32 hpt374_read_freq(struct pci_dev *pdev)
683{
684 u32 freq;
685 unsigned long io_base = pci_resource_start(pdev, 4);
686 if (PCI_FUNC(pdev->devfn) & 1) {
687 struct pci_dev *pdev_0;
688
689 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
690
691 if (pdev_0 == NULL)
692 return 0;
693 io_base = pci_resource_start(pdev_0, 4);
694 freq = inl(io_base + 0x90);
695 pci_dev_put(pdev_0);
696 } else
697 freq = inl(io_base + 0x90);
698 return freq;
699}
700
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731
732
733static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
734{
735
736 static const struct ata_port_info info_hpt370 = {
737 .flags = ATA_FLAG_SLAVE_POSS,
738 .pio_mask = ATA_PIO4,
739 .mwdma_mask = ATA_MWDMA2,
740 .udma_mask = ATA_UDMA5,
741 .port_ops = &hpt370_port_ops
742 };
743
744 static const struct ata_port_info info_hpt370a = {
745 .flags = ATA_FLAG_SLAVE_POSS,
746 .pio_mask = ATA_PIO4,
747 .mwdma_mask = ATA_MWDMA2,
748 .udma_mask = ATA_UDMA5,
749 .port_ops = &hpt370a_port_ops
750 };
751
752 static const struct ata_port_info info_hpt370_33 = {
753 .flags = ATA_FLAG_SLAVE_POSS,
754 .pio_mask = ATA_PIO4,
755 .mwdma_mask = ATA_MWDMA2,
756 .udma_mask = ATA_UDMA5,
757 .port_ops = &hpt370_port_ops
758 };
759
760 static const struct ata_port_info info_hpt370a_33 = {
761 .flags = ATA_FLAG_SLAVE_POSS,
762 .pio_mask = ATA_PIO4,
763 .mwdma_mask = ATA_MWDMA2,
764 .udma_mask = ATA_UDMA5,
765 .port_ops = &hpt370a_port_ops
766 };
767
768 static const struct ata_port_info info_hpt372 = {
769 .flags = ATA_FLAG_SLAVE_POSS,
770 .pio_mask = ATA_PIO4,
771 .mwdma_mask = ATA_MWDMA2,
772 .udma_mask = ATA_UDMA6,
773 .port_ops = &hpt372_port_ops
774 };
775
776 static const struct ata_port_info info_hpt374_fn0 = {
777 .flags = ATA_FLAG_SLAVE_POSS,
778 .pio_mask = ATA_PIO4,
779 .mwdma_mask = ATA_MWDMA2,
780 .udma_mask = ATA_UDMA5,
781 .port_ops = &hpt372_port_ops
782 };
783 static const struct ata_port_info info_hpt374_fn1 = {
784 .flags = ATA_FLAG_SLAVE_POSS,
785 .pio_mask = ATA_PIO4,
786 .mwdma_mask = ATA_MWDMA2,
787 .udma_mask = ATA_UDMA5,
788 .port_ops = &hpt374_fn1_port_ops
789 };
790
791 static const int MHz[4] = { 33, 40, 50, 66 };
792 void *private_data = NULL;
793 const struct ata_port_info *ppi[] = { NULL, NULL };
794
795 u8 irqmask;
796 u32 class_rev;
797 u8 mcr1;
798 u32 freq;
799 int prefer_dpll = 1;
800
801 unsigned long iobase = pci_resource_start(dev, 4);
802
803 const struct hpt_chip *chip_table;
804 int clock_slot;
805 int rc;
806
807 rc = pcim_enable_device(dev);
808 if (rc)
809 return rc;
810
811 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
812 class_rev &= 0xFF;
813
814 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
815
816
817 if (class_rev < 3)
818 return -ENODEV;
819
820 if (class_rev == 6)
821 return -ENODEV;
822
823 switch(class_rev) {
824 case 3:
825 ppi[0] = &info_hpt370;
826 chip_table = &hpt370;
827 prefer_dpll = 0;
828 break;
829 case 4:
830 ppi[0] = &info_hpt370a;
831 chip_table = &hpt370a;
832 prefer_dpll = 0;
833 break;
834 case 5:
835 ppi[0] = &info_hpt372;
836 chip_table = &hpt372;
837 break;
838 default:
839 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
840 return -ENODEV;
841 }
842 } else {
843 switch(dev->device) {
844 case PCI_DEVICE_ID_TTI_HPT372:
845
846 if (class_rev >= 2)
847 return -ENODEV;
848 ppi[0] = &info_hpt372;
849 chip_table = &hpt372a;
850 break;
851 case PCI_DEVICE_ID_TTI_HPT302:
852
853 if (class_rev > 1)
854 return -ENODEV;
855 ppi[0] = &info_hpt372;
856
857 chip_table = &hpt302;
858 break;
859 case PCI_DEVICE_ID_TTI_HPT371:
860 if (class_rev > 1)
861 return -ENODEV;
862 ppi[0] = &info_hpt372;
863 chip_table = &hpt371;
864
865
866
867 pci_read_config_byte(dev, 0x50, &mcr1);
868 mcr1 &= ~0x04;
869 pci_write_config_byte(dev, 0x50, mcr1);
870 break;
871 case PCI_DEVICE_ID_TTI_HPT374:
872 chip_table = &hpt374;
873 if (!(PCI_FUNC(dev->devfn) & 1))
874 *ppi = &info_hpt374_fn0;
875 else
876 *ppi = &info_hpt374_fn1;
877 break;
878 default:
879 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
880 return -ENODEV;
881 }
882 }
883
884
885 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
886 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
887 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
888 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
889
890 pci_read_config_byte(dev, 0x5A, &irqmask);
891 irqmask &= ~0x10;
892 pci_write_config_byte(dev, 0x5a, irqmask);
893
894
895
896
897
898
899
900
901 pci_write_config_byte(dev, 0x5b, 0x23);
902
903
904
905
906
907 if (chip_table == &hpt372a)
908 outb(0x0e, iobase + 0x9c);
909
910
911
912
913
914 if (chip_table == &hpt374) {
915 freq = hpt374_read_freq(dev);
916 if (freq == 0)
917 return -ENODEV;
918 } else
919 freq = inl(iobase + 0x90);
920
921 if ((freq >> 12) != 0xABCDE) {
922 int i;
923 u8 sr;
924 u32 total = 0;
925
926 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
927
928
929 for(i = 0; i < 128; i++) {
930 pci_read_config_byte(dev, 0x78, &sr);
931 total += sr & 0x1FF;
932 udelay(15);
933 }
934 freq = total / 128;
935 }
936 freq &= 0x1FF;
937
938
939
940
941
942
943 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
944 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
945
946
947
948
949
950
951 unsigned int f_low, f_high;
952 int dpll, adjust;
953
954
955 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
956
957 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
958 f_high = f_low + 2;
959 if (clock_slot > 1)
960 f_high += 2;
961
962
963 pci_write_config_byte(dev, 0x5b, 0x21);
964 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
965
966 for(adjust = 0; adjust < 8; adjust++) {
967 if (hpt37x_calibrate_dpll(dev))
968 break;
969
970 if (adjust & 1)
971 f_low -= adjust >> 1;
972 else
973 f_high += adjust >> 1;
974 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
975 }
976 if (adjust == 8) {
977 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
978 return -ENODEV;
979 }
980 if (dpll == 3)
981 private_data = (void *)hpt37x_timings_66;
982 else
983 private_data = (void *)hpt37x_timings_50;
984
985 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
986 MHz[clock_slot], MHz[dpll]);
987 } else {
988 private_data = (void *)chip_table->clocks[clock_slot];
989
990
991
992
993
994
995 if (clock_slot < 2 && ppi[0] == &info_hpt370)
996 ppi[0] = &info_hpt370_33;
997 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
998 ppi[0] = &info_hpt370a_33;
999 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1000 chip_table->name, MHz[clock_slot]);
1001 }
1002
1003
1004 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
1005}
1006
1007static const struct pci_device_id hpt37x[] = {
1008 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1009 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1010 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1011 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1012 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1013
1014 { },
1015};
1016
1017static struct pci_driver hpt37x_pci_driver = {
1018 .name = DRV_NAME,
1019 .id_table = hpt37x,
1020 .probe = hpt37x_init_one,
1021 .remove = ata_pci_remove_one
1022};
1023
1024static int __init hpt37x_init(void)
1025{
1026 return pci_register_driver(&hpt37x_pci_driver);
1027}
1028
1029static void __exit hpt37x_exit(void)
1030{
1031 pci_unregister_driver(&hpt37x_pci_driver);
1032}
1033
1034MODULE_AUTHOR("Alan Cox");
1035MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1036MODULE_LICENSE("GPL");
1037MODULE_DEVICE_TABLE(pci, hpt37x);
1038MODULE_VERSION(DRV_VERSION);
1039
1040module_init(hpt37x_init);
1041module_exit(hpt37x_exit);
1042