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18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
28#define DRV_VERSION "0.3.4"
29
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
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71static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2c },
84
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
90 { 0, 0x0d029d5e }
91};
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103
104static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105{
106 struct hpt_clock *clocks = hpt3x2n_clocks;
107
108 while(clocks->xfer_speed) {
109 if (clocks->xfer_speed == speed)
110 return clocks->timing;
111 clocks++;
112 }
113 BUG();
114 return 0xffffffffU;
115}
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123
124static int hpt3x2n_cable_detect(struct ata_port *ap)
125{
126 u8 scr2, ata66;
127 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
128
129 pci_read_config_byte(pdev, 0x5B, &scr2);
130 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
131
132 pci_read_config_byte(pdev, 0x5A, &ata66);
133
134 pci_write_config_byte(pdev, 0x5B, scr2);
135
136 if (ata66 & (1 << ap->port_no))
137 return ATA_CBL_PATA40;
138 else
139 return ATA_CBL_PATA80;
140}
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150
151static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
152{
153 struct ata_port *ap = link->ap;
154 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
155
156 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
157 udelay(100);
158
159 return ata_sff_prereset(link, deadline);
160}
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169
170static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
171{
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173 u32 addr1, addr2;
174 u32 reg;
175 u32 mode;
176 u8 fast;
177
178 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
179 addr2 = 0x51 + 4 * ap->port_no;
180
181
182 pci_read_config_byte(pdev, addr2, &fast);
183 fast &= ~0x07;
184 pci_write_config_byte(pdev, addr2, fast);
185
186 pci_read_config_dword(pdev, addr1, ®);
187 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
188 mode &= ~0x8000000;
189 mode &= ~0x30070000;
190 reg &= 0x30070000;
191 pci_write_config_dword(pdev, addr1, reg | mode);
192}
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203static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
204{
205 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
206 u32 addr1, addr2;
207 u32 reg;
208 u32 mode;
209 u8 fast;
210
211 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
212 addr2 = 0x51 + 4 * ap->port_no;
213
214
215 pci_read_config_byte(pdev, addr2, &fast);
216 fast &= ~0x07;
217 pci_write_config_byte(pdev, addr2, fast);
218
219 pci_read_config_dword(pdev, addr1, ®);
220 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
221 mode |= 0x8000000;
222 mode &= ~0xC0000000;
223 reg &= 0xC0000000;
224 pci_write_config_dword(pdev, addr1, reg | mode);
225}
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233
234static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
235{
236 struct ata_port *ap = qc->ap;
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
238 int mscreg = 0x50 + 2 * ap->port_no;
239 u8 bwsr_stat, msc_stat;
240
241 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
242 pci_read_config_byte(pdev, mscreg, &msc_stat);
243 if (bwsr_stat & (1 << ap->port_no))
244 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
245 ata_bmdma_stop(qc);
246}
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264static void hpt3x2n_set_clock(struct ata_port *ap, int source)
265{
266 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
267
268
269 iowrite8(0x80, bmdma+0x73);
270 iowrite8(0x80, bmdma+0x77);
271
272
273 iowrite8(source, bmdma+0x7B);
274 iowrite8(0xC0, bmdma+0x79);
275
276
277 iowrite8(0x37, bmdma+0x70);
278 iowrite8(0x37, bmdma+0x74);
279
280
281 iowrite8(0x00, bmdma+0x79);
282
283
284 iowrite8(0x00, bmdma+0x73);
285 iowrite8(0x00, bmdma+0x77);
286}
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290static int hpt3x2n_pair_idle(struct ata_port *ap)
291{
292 struct ata_host *host = ap->host;
293 struct ata_port *pair = host->ports[ap->port_no ^ 1];
294
295 if (pair->hsm_task_state == HSM_ST_IDLE)
296 return 1;
297 return 0;
298}
299
300static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
301{
302 long flags = (long)ap->host->private_data;
303
304 if (writing)
305 return USE_DPLL;
306 if (flags & PCI66)
307 return USE_DPLL;
308 return 0;
309}
310
311static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
312{
313 struct ata_taskfile *tf = &qc->tf;
314 struct ata_port *ap = qc->ap;
315 int flags = (long)ap->host->private_data;
316
317 if (hpt3x2n_pair_idle(ap)) {
318 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
319 if ((flags & USE_DPLL) != dpll) {
320 if (dpll == 1)
321 hpt3x2n_set_clock(ap, 0x21);
322 else
323 hpt3x2n_set_clock(ap, 0x23);
324 }
325 }
326 return ata_sff_qc_issue(qc);
327}
328
329static struct scsi_host_template hpt3x2n_sht = {
330 ATA_BMDMA_SHT(DRV_NAME),
331};
332
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336
337static struct ata_port_operations hpt3x2n_port_ops = {
338 .inherits = &ata_bmdma_port_ops,
339
340 .bmdma_stop = hpt3x2n_bmdma_stop,
341 .qc_issue = hpt3x2n_qc_issue,
342
343 .cable_detect = hpt3x2n_cable_detect,
344 .set_piomode = hpt3x2n_set_piomode,
345 .set_dmamode = hpt3x2n_set_dmamode,
346 .prereset = hpt3x2n_pre_reset,
347};
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357static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
358{
359 u8 reg5b;
360 u32 reg5c;
361 int tries;
362
363 for(tries = 0; tries < 0x5000; tries++) {
364 udelay(50);
365 pci_read_config_byte(dev, 0x5b, ®5b);
366 if (reg5b & 0x80) {
367
368 for(tries = 0; tries < 0x1000; tries ++) {
369 pci_read_config_byte(dev, 0x5b, ®5b);
370
371 if ((reg5b & 0x80) == 0)
372 return 0;
373 }
374
375 pci_read_config_dword(dev, 0x5c, ®5c);
376 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
377 return 1;
378 }
379 }
380
381 return 0;
382}
383
384static int hpt3x2n_pci_clock(struct pci_dev *pdev)
385{
386 unsigned long freq;
387 u32 fcnt;
388 unsigned long iobase = pci_resource_start(pdev, 4);
389
390 fcnt = inl(iobase + 0x90);
391 if ((fcnt >> 12) != 0xABCDE) {
392 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
393 return 33;
394 }
395 fcnt &= 0x1FF;
396
397 freq = (fcnt * 77) / 192;
398
399
400 if (freq < 40)
401 return 33;
402 if (freq < 45)
403 return 40;
404 if (freq < 55)
405 return 50;
406 return 66;
407}
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439static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
440{
441
442 static const struct ata_port_info info = {
443 .flags = ATA_FLAG_SLAVE_POSS,
444 .pio_mask = ATA_PIO4,
445 .mwdma_mask = ATA_MWDMA2,
446 .udma_mask = ATA_UDMA6,
447 .port_ops = &hpt3x2n_port_ops
448 };
449 const struct ata_port_info *ppi[] = { &info, NULL };
450
451 u8 irqmask;
452 u32 class_rev;
453
454 unsigned int pci_mhz;
455 unsigned int f_low, f_high;
456 int adjust;
457 unsigned long iobase = pci_resource_start(dev, 4);
458 void *hpriv = NULL;
459 int rc;
460
461 rc = pcim_enable_device(dev);
462 if (rc)
463 return rc;
464
465 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
466 class_rev &= 0xFF;
467
468 switch(dev->device) {
469 case PCI_DEVICE_ID_TTI_HPT366:
470 if (class_rev < 6)
471 return -ENODEV;
472 break;
473 case PCI_DEVICE_ID_TTI_HPT371:
474 if (class_rev < 2)
475 return -ENODEV;
476
477 break;
478 case PCI_DEVICE_ID_TTI_HPT372:
479
480 if (class_rev < 2)
481 return -ENODEV;
482 break;
483 case PCI_DEVICE_ID_TTI_HPT302:
484 if (class_rev < 2)
485 return -ENODEV;
486 break;
487 case PCI_DEVICE_ID_TTI_HPT372N:
488 break;
489 default:
490 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
491 return -ENODEV;
492 }
493
494
495
496 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
497 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
498 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
499 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
500
501 pci_read_config_byte(dev, 0x5A, &irqmask);
502 irqmask &= ~0x10;
503 pci_write_config_byte(dev, 0x5a, irqmask);
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510
511 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
512 u8 mcr1;
513 pci_read_config_byte(dev, 0x50, &mcr1);
514 mcr1 &= ~0x04;
515 pci_write_config_byte(dev, 0x50, mcr1);
516 }
517
518
519
520
521 pci_mhz = hpt3x2n_pci_clock(dev);
522
523 f_low = (pci_mhz * 48) / 66;
524 f_high = f_low + 2;
525
526 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
527
528 pci_write_config_byte(dev, 0x5B, 0x21);
529
530
531 for(adjust = 0; adjust < 8; adjust++) {
532 if (hpt3xn_calibrate_dpll(dev))
533 break;
534 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
535 }
536 if (adjust == 8) {
537 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
538 return -ENODEV;
539 }
540
541 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
542 pci_mhz);
543
544
545 if (pci_mhz > 60) {
546 hpriv = (void *)PCI66;
547
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551
552 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
553 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
554 }
555
556
557 return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
558}
559
560static const struct pci_device_id hpt3x2n[] = {
561 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
562 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
563 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
564 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
565 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
566
567 { },
568};
569
570static struct pci_driver hpt3x2n_pci_driver = {
571 .name = DRV_NAME,
572 .id_table = hpt3x2n,
573 .probe = hpt3x2n_init_one,
574 .remove = ata_pci_remove_one
575};
576
577static int __init hpt3x2n_init(void)
578{
579 return pci_register_driver(&hpt3x2n_pci_driver);
580}
581
582static void __exit hpt3x2n_exit(void)
583{
584 pci_unregister_driver(&hpt3x2n_pci_driver);
585}
586
587MODULE_AUTHOR("Alan Cox");
588MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
589MODULE_LICENSE("GPL");
590MODULE_DEVICE_TABLE(pci, hpt3x2n);
591MODULE_VERSION(DRV_VERSION);
592
593module_init(hpt3x2n_init);
594module_exit(hpt3x2n_exit);
595