1#ifndef CCISS_H
2#define CCISS_H
3
4#include <linux/genhd.h>
5#include <linux/mutex.h>
6
7#include "cciss_cmd.h"
8
9
10#define NWD_SHIFT 4
11#define MAX_PART (1 << NWD_SHIFT)
12
13#define IO_OK 0
14#define IO_ERROR 1
15#define IO_NEEDS_RETRY 3
16
17#define VENDOR_LEN 8
18#define MODEL_LEN 16
19#define REV_LEN 4
20
21struct ctlr_info;
22typedef struct ctlr_info ctlr_info_t;
23
24struct access_method {
25 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
26 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
27 unsigned long (*fifo_full)(ctlr_info_t *h);
28 unsigned long (*intr_pending)(ctlr_info_t *h);
29 unsigned long (*command_completed)(ctlr_info_t *h);
30};
31typedef struct _drive_info_struct
32{
33 unsigned char LunID[8];
34 int usage_count;
35 struct request_queue *queue;
36 sector_t nr_blocks;
37 int block_size;
38 int heads;
39 int sectors;
40 int cylinders;
41 int raid_level;
42
43
44 int busy_configuring;
45
46
47
48 struct device dev;
49 __u8 serial_no[16];
50
51
52 char vendor[VENDOR_LEN + 1];
53 char model[MODEL_LEN + 1];
54 char rev[REV_LEN + 1];
55 char device_initialized;
56} drive_info_struct;
57
58struct ctlr_info
59{
60 int ctlr;
61 char devname[8];
62 char *product_name;
63 char firm_ver[4];
64 struct pci_dev *pdev;
65 __u32 board_id;
66 void __iomem *vaddr;
67 unsigned long paddr;
68 int nr_cmds;
69 CfgTable_struct __iomem *cfgtable;
70 int interrupts_enabled;
71 int major;
72 int max_commands;
73 int commands_outstanding;
74 int max_outstanding;
75 int num_luns;
76 int highest_lun;
77 int usage_count;
78# define DOORBELL_INT 0
79# define PERF_MODE_INT 1
80# define SIMPLE_MODE_INT 2
81# define MEMQ_MODE_INT 3
82 unsigned int intr[4];
83 unsigned int msix_vector;
84 unsigned int msi_vector;
85 int cciss_max_sectors;
86 BYTE cciss_read;
87 BYTE cciss_write;
88 BYTE cciss_read_capacity;
89
90
91 drive_info_struct *drv[CISS_MAX_LUN];
92
93 struct access_method access;
94
95
96 struct hlist_head reqQ;
97 struct hlist_head cmpQ;
98 unsigned int Qdepth;
99 unsigned int maxQsinceinit;
100 unsigned int maxSG;
101 spinlock_t lock;
102
103
104 CommandList_struct *cmd_pool;
105 dma_addr_t cmd_pool_dhandle;
106 ErrorInfo_struct *errinfo_pool;
107 dma_addr_t errinfo_pool_dhandle;
108 unsigned long *cmd_pool_bits;
109 int nr_allocs;
110 int nr_frees;
111 int busy_configuring;
112 int busy_initializing;
113 int busy_scanning;
114 struct mutex busy_shutting_down;
115
116
117
118
119 int next_to_run;
120
121
122 struct gendisk *gendisk[CISS_MAX_LUN];
123#ifdef CONFIG_CISS_SCSI_TAPE
124 void *scsi_ctlr;
125
126
127#endif
128 unsigned char alive;
129 struct list_head scan_list;
130 struct completion scan_wait;
131 struct device dev;
132};
133
134
135
136
137
138#define SA5_DOORBELL 0x20
139#define SA5_REQUEST_PORT_OFFSET 0x40
140#define SA5_REPLY_INTR_MASK_OFFSET 0x34
141#define SA5_REPLY_PORT_OFFSET 0x44
142#define SA5_INTR_STATUS 0x30
143#define SA5_SCRATCHPAD_OFFSET 0xB0
144
145#define SA5_CTCFG_OFFSET 0xB4
146#define SA5_CTMEM_OFFSET 0xB8
147
148#define SA5_INTR_OFF 0x08
149#define SA5B_INTR_OFF 0x04
150#define SA5_INTR_PENDING 0x08
151#define SA5B_INTR_PENDING 0x04
152#define FIFO_EMPTY 0xffffffff
153#define CCISS_FIRMWARE_READY 0xffff0000
154
155#define CISS_ERROR_BIT 0x02
156
157#define CCISS_INTR_ON 1
158#define CCISS_INTR_OFF 0
159
160
161
162static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
163{
164#ifdef CCISS_DEBUG
165 printk("Sending %x - down to controller\n", c->busaddr );
166#endif
167 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
168 h->commands_outstanding++;
169 if ( h->commands_outstanding > h->max_outstanding)
170 h->max_outstanding = h->commands_outstanding;
171}
172
173
174
175
176
177
178static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
179{
180 if (val)
181 {
182 h->interrupts_enabled = 1;
183 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
184 } else
185 {
186 h->interrupts_enabled = 0;
187 writel( SA5_INTR_OFF,
188 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
189 }
190}
191
192
193
194
195
196static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
197{
198 if (val)
199 {
200 h->interrupts_enabled = 1;
201 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
202 } else
203 {
204 h->interrupts_enabled = 0;
205 writel( SA5B_INTR_OFF,
206 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
207 }
208}
209
210
211
212
213static unsigned long SA5_fifo_full(ctlr_info_t *h)
214{
215 if( h->commands_outstanding >= h->max_commands)
216 return(1);
217 else
218 return(0);
219
220}
221
222
223
224
225static unsigned long SA5_completed(ctlr_info_t *h)
226{
227 unsigned long register_value
228 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
229 if(register_value != FIFO_EMPTY)
230 {
231 h->commands_outstanding--;
232#ifdef CCISS_DEBUG
233 printk("cciss: Read %lx back from board\n", register_value);
234#endif
235 }
236#ifdef CCISS_DEBUG
237 else
238 {
239 printk("cciss: FIFO Empty read\n");
240 }
241#endif
242 return ( register_value);
243
244}
245
246
247
248static unsigned long SA5_intr_pending(ctlr_info_t *h)
249{
250 unsigned long register_value =
251 readl(h->vaddr + SA5_INTR_STATUS);
252#ifdef CCISS_DEBUG
253 printk("cciss: intr_pending %lx\n", register_value);
254#endif
255 if( register_value & SA5_INTR_PENDING)
256 return 1;
257 return 0 ;
258}
259
260
261
262
263static unsigned long SA5B_intr_pending(ctlr_info_t *h)
264{
265 unsigned long register_value =
266 readl(h->vaddr + SA5_INTR_STATUS);
267#ifdef CCISS_DEBUG
268 printk("cciss: intr_pending %lx\n", register_value);
269#endif
270 if( register_value & SA5B_INTR_PENDING)
271 return 1;
272 return 0 ;
273}
274
275
276static struct access_method SA5_access = {
277 SA5_submit_command,
278 SA5_intr_mask,
279 SA5_fifo_full,
280 SA5_intr_pending,
281 SA5_completed,
282};
283
284static struct access_method SA5B_access = {
285 SA5_submit_command,
286 SA5B_intr_mask,
287 SA5_fifo_full,
288 SA5B_intr_pending,
289 SA5_completed,
290};
291
292struct board_type {
293 __u32 board_id;
294 char *product_name;
295 struct access_method *access;
296 int nr_cmds;
297};
298
299#define CCISS_LOCK(i) (&hba[i]->lock)
300
301#endif
302
303