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12#include <linux/acpi.h>
13#include <linux/module.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/agp_backend.h>
17#include <linux/log2.h>
18
19#include <asm/acpi-ext.h>
20
21#include "agp.h"
22
23#define HP_ZX1_IOC_OFFSET 0x1000
24
25
26#define HP_ZX1_IBASE 0x300
27#define HP_ZX1_IMASK 0x308
28#define HP_ZX1_PCOM 0x310
29#define HP_ZX1_TCNFG 0x318
30#define HP_ZX1_PDIR_BASE 0x320
31
32#define HP_ZX1_IOVA_BASE GB(1UL)
33#define HP_ZX1_IOVA_SIZE GB(1UL)
34#define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2)
35#define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
36
37#define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL
38#define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift)
39
40#define AGP8X_MODE_BIT 3
41#define AGP8X_MODE (1 << AGP8X_MODE_BIT)
42
43
44static struct pci_dev fake_bridge_dev;
45
46static int hp_zx1_gart_found;
47
48static struct aper_size_info_fixed hp_zx1_sizes[] =
49{
50 {0, 0, 0},
51};
52
53static struct gatt_mask hp_zx1_masks[] =
54{
55 {.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0}
56};
57
58static struct _hp_private {
59 volatile u8 __iomem *ioc_regs;
60 volatile u8 __iomem *lba_regs;
61 int lba_cap_offset;
62 u64 *io_pdir;
63 u64 *gatt;
64 u64 gatt_entries;
65 u64 iova_base;
66 u64 gart_base;
67 u64 gart_size;
68 u64 io_pdir_size;
69 int io_pdir_owner;
70 int io_page_size;
71 int io_tlb_shift;
72 int io_tlb_ps;
73 int io_pages_per_kpage;
74} hp_private;
75
76static int __init hp_zx1_ioc_shared(void)
77{
78 struct _hp_private *hp = &hp_private;
79
80 printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n");
81
82
83
84
85
86
87
88 hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
89 switch (hp->io_tlb_ps) {
90 case 0: hp->io_tlb_shift = 12; break;
91 case 1: hp->io_tlb_shift = 13; break;
92 case 2: hp->io_tlb_shift = 14; break;
93 case 3: hp->io_tlb_shift = 16; break;
94 default:
95 printk(KERN_ERR PFX "Invalid IOTLB page size "
96 "configuration 0x%x\n", hp->io_tlb_ps);
97 hp->gatt = NULL;
98 hp->gatt_entries = 0;
99 return -ENODEV;
100 }
101 hp->io_page_size = 1 << hp->io_tlb_shift;
102 hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
103
104 hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
105 hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;
106
107 hp->gart_size = HP_ZX1_GART_SIZE;
108 hp->gatt_entries = hp->gart_size / hp->io_page_size;
109
110 hp->io_pdir = phys_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
111 hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
112
113 if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
114
115 hp->gatt = NULL;
116 hp->gatt_entries = 0;
117 printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
118 "GART disabled\n");
119 return -ENODEV;
120 }
121
122 return 0;
123}
124
125static int __init
126hp_zx1_ioc_owner (void)
127{
128 struct _hp_private *hp = &hp_private;
129
130 printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n");
131
132
133
134
135 if (PAGE_SIZE >= KB(64)) {
136 hp->io_tlb_shift = 16;
137 hp->io_tlb_ps = 3;
138 } else if (PAGE_SIZE >= KB(16)) {
139 hp->io_tlb_shift = 14;
140 hp->io_tlb_ps = 2;
141 } else if (PAGE_SIZE >= KB(8)) {
142 hp->io_tlb_shift = 13;
143 hp->io_tlb_ps = 1;
144 } else {
145 hp->io_tlb_shift = 12;
146 hp->io_tlb_ps = 0;
147 }
148 hp->io_page_size = 1 << hp->io_tlb_shift;
149 hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
150
151 hp->iova_base = HP_ZX1_IOVA_BASE;
152 hp->gart_size = HP_ZX1_GART_SIZE;
153 hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size;
154
155 hp->gatt_entries = hp->gart_size / hp->io_page_size;
156 hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64);
157
158 return 0;
159}
160
161static int __init
162hp_zx1_ioc_init (u64 hpa)
163{
164 struct _hp_private *hp = &hp_private;
165
166 hp->ioc_regs = ioremap(hpa, 1024);
167 if (!hp->ioc_regs)
168 return -ENOMEM;
169
170
171
172
173
174 hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;
175
176 if (hp->io_pdir_owner)
177 return hp_zx1_ioc_owner();
178
179 return hp_zx1_ioc_shared();
180}
181
182static int
183hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap)
184{
185 u16 status;
186 u8 pos, id;
187 int ttl = 48;
188
189 status = readw(hpa+PCI_STATUS);
190 if (!(status & PCI_STATUS_CAP_LIST))
191 return 0;
192 pos = readb(hpa+PCI_CAPABILITY_LIST);
193 while (ttl-- && pos >= 0x40) {
194 pos &= ~3;
195 id = readb(hpa+pos+PCI_CAP_LIST_ID);
196 if (id == 0xff)
197 break;
198 if (id == cap)
199 return pos;
200 pos = readb(hpa+pos+PCI_CAP_LIST_NEXT);
201 }
202 return 0;
203}
204
205static int __init
206hp_zx1_lba_init (u64 hpa)
207{
208 struct _hp_private *hp = &hp_private;
209 int cap;
210
211 hp->lba_regs = ioremap(hpa, 256);
212 if (!hp->lba_regs)
213 return -ENOMEM;
214
215 hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);
216
217 cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff;
218 if (cap != PCI_CAP_ID_AGP) {
219 printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
220 cap, hp->lba_cap_offset);
221 iounmap(hp->lba_regs);
222 return -ENODEV;
223 }
224
225 return 0;
226}
227
228static int
229hp_zx1_fetch_size(void)
230{
231 int size;
232
233 size = hp_private.gart_size / MB(1);
234 hp_zx1_sizes[0].size = size;
235 agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
236 return size;
237}
238
239static int
240hp_zx1_configure (void)
241{
242 struct _hp_private *hp = &hp_private;
243
244 agp_bridge->gart_bus_addr = hp->gart_base;
245 agp_bridge->capndx = hp->lba_cap_offset;
246 agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
247
248 if (hp->io_pdir_owner) {
249 writel(virt_to_phys(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE);
250 readl(hp->ioc_regs+HP_ZX1_PDIR_BASE);
251 writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG);
252 readl(hp->ioc_regs+HP_ZX1_TCNFG);
253 writel((unsigned int)(~(HP_ZX1_IOVA_SIZE-1)), hp->ioc_regs+HP_ZX1_IMASK);
254 readl(hp->ioc_regs+HP_ZX1_IMASK);
255 writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE);
256 readl(hp->ioc_regs+HP_ZX1_IBASE);
257 writel(hp->iova_base|ilog2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM);
258 readl(hp->ioc_regs+HP_ZX1_PCOM);
259 }
260
261 return 0;
262}
263
264static void
265hp_zx1_cleanup (void)
266{
267 struct _hp_private *hp = &hp_private;
268
269 if (hp->ioc_regs) {
270 if (hp->io_pdir_owner) {
271 writeq(0, hp->ioc_regs+HP_ZX1_IBASE);
272 readq(hp->ioc_regs+HP_ZX1_IBASE);
273 }
274 iounmap(hp->ioc_regs);
275 }
276 if (hp->lba_regs)
277 iounmap(hp->lba_regs);
278}
279
280static void
281hp_zx1_tlbflush (struct agp_memory *mem)
282{
283 struct _hp_private *hp = &hp_private;
284
285 writeq(hp->gart_base | ilog2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM);
286 readq(hp->ioc_regs+HP_ZX1_PCOM);
287}
288
289static int
290hp_zx1_create_gatt_table (struct agp_bridge_data *bridge)
291{
292 struct _hp_private *hp = &hp_private;
293 int i;
294
295 if (hp->io_pdir_owner) {
296 hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL,
297 get_order(hp->io_pdir_size));
298 if (!hp->io_pdir) {
299 printk(KERN_ERR PFX "Couldn't allocate contiguous "
300 "memory for I/O PDIR\n");
301 hp->gatt = NULL;
302 hp->gatt_entries = 0;
303 return -ENOMEM;
304 }
305 memset(hp->io_pdir, 0, hp->io_pdir_size);
306
307 hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
308 }
309
310 for (i = 0; i < hp->gatt_entries; i++) {
311 hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
312 }
313
314 return 0;
315}
316
317static int
318hp_zx1_free_gatt_table (struct agp_bridge_data *bridge)
319{
320 struct _hp_private *hp = &hp_private;
321
322 if (hp->io_pdir_owner)
323 free_pages((unsigned long) hp->io_pdir,
324 get_order(hp->io_pdir_size));
325 else
326 hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE;
327 return 0;
328}
329
330static int
331hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
332{
333 struct _hp_private *hp = &hp_private;
334 int i, k;
335 off_t j, io_pg_start;
336 int io_pg_count;
337
338 if (type != 0 || mem->type != 0) {
339 return -EINVAL;
340 }
341
342 io_pg_start = hp->io_pages_per_kpage * pg_start;
343 io_pg_count = hp->io_pages_per_kpage * mem->page_count;
344 if ((io_pg_start + io_pg_count) > hp->gatt_entries) {
345 return -EINVAL;
346 }
347
348 j = io_pg_start;
349 while (j < (io_pg_start + io_pg_count)) {
350 if (hp->gatt[j]) {
351 return -EBUSY;
352 }
353 j++;
354 }
355
356 if (!mem->is_flushed) {
357 global_cache_flush();
358 mem->is_flushed = true;
359 }
360
361 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
362 unsigned long paddr;
363
364 paddr = page_to_phys(mem->pages[i]);
365 for (k = 0;
366 k < hp->io_pages_per_kpage;
367 k++, j++, paddr += hp->io_page_size) {
368 hp->gatt[j] = HP_ZX1_PDIR_VALID_BIT | paddr;
369 }
370 }
371
372 agp_bridge->driver->tlb_flush(mem);
373 return 0;
374}
375
376static int
377hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
378{
379 struct _hp_private *hp = &hp_private;
380 int i, io_pg_start, io_pg_count;
381
382 if (type != 0 || mem->type != 0) {
383 return -EINVAL;
384 }
385
386 io_pg_start = hp->io_pages_per_kpage * pg_start;
387 io_pg_count = hp->io_pages_per_kpage * mem->page_count;
388 for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
389 hp->gatt[i] = agp_bridge->scratch_page;
390 }
391
392 agp_bridge->driver->tlb_flush(mem);
393 return 0;
394}
395
396static unsigned long
397hp_zx1_mask_memory (struct agp_bridge_data *bridge, dma_addr_t addr, int type)
398{
399 return HP_ZX1_PDIR_VALID_BIT | addr;
400}
401
402static void
403hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode)
404{
405 struct _hp_private *hp = &hp_private;
406 u32 command;
407
408 command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS);
409 command = agp_collect_device_status(bridge, mode, command);
410 command |= 0x00000100;
411
412 writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND);
413
414 agp_device_command(command, (mode & AGP8X_MODE) != 0);
415}
416
417const struct agp_bridge_driver hp_zx1_driver = {
418 .owner = THIS_MODULE,
419 .size_type = FIXED_APER_SIZE,
420 .configure = hp_zx1_configure,
421 .fetch_size = hp_zx1_fetch_size,
422 .cleanup = hp_zx1_cleanup,
423 .tlb_flush = hp_zx1_tlbflush,
424 .mask_memory = hp_zx1_mask_memory,
425 .masks = hp_zx1_masks,
426 .agp_enable = hp_zx1_enable,
427 .cache_flush = global_cache_flush,
428 .create_gatt_table = hp_zx1_create_gatt_table,
429 .free_gatt_table = hp_zx1_free_gatt_table,
430 .insert_memory = hp_zx1_insert_memory,
431 .remove_memory = hp_zx1_remove_memory,
432 .alloc_by_type = agp_generic_alloc_by_type,
433 .free_by_type = agp_generic_free_by_type,
434 .agp_alloc_page = agp_generic_alloc_page,
435 .agp_alloc_pages = agp_generic_alloc_pages,
436 .agp_destroy_page = agp_generic_destroy_page,
437 .agp_destroy_pages = agp_generic_destroy_pages,
438 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
439 .cant_use_aperture = true,
440};
441
442static int __init
443hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa)
444{
445 struct agp_bridge_data *bridge;
446 int error = 0;
447
448 error = hp_zx1_ioc_init(ioc_hpa);
449 if (error)
450 goto fail;
451
452 error = hp_zx1_lba_init(lba_hpa);
453 if (error)
454 goto fail;
455
456 bridge = agp_alloc_bridge();
457 if (!bridge) {
458 error = -ENOMEM;
459 goto fail;
460 }
461 bridge->driver = &hp_zx1_driver;
462
463 fake_bridge_dev.vendor = PCI_VENDOR_ID_HP;
464 fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA;
465 bridge->dev = &fake_bridge_dev;
466
467 error = agp_add_bridge(bridge);
468 fail:
469 if (error)
470 hp_zx1_cleanup();
471 return error;
472}
473
474static acpi_status __init
475zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret)
476{
477 acpi_handle handle, parent;
478 acpi_status status;
479 struct acpi_device_info *info;
480 u64 lba_hpa, sba_hpa, length;
481 int match;
482
483 status = hp_acpi_csr_space(obj, &lba_hpa, &length);
484 if (ACPI_FAILURE(status))
485 return AE_OK;
486
487
488 handle = obj;
489 do {
490 status = acpi_get_object_info(handle, &info);
491 if (ACPI_SUCCESS(status)) {
492
493 info->hardware_id.string[sizeof(info->hardware_id.length)-1] = '\0';
494 match = (strcmp(info->hardware_id.string, "HWP0001") == 0);
495 kfree(info);
496 if (match) {
497 status = hp_acpi_csr_space(handle, &sba_hpa, &length);
498 if (ACPI_SUCCESS(status))
499 break;
500 else {
501 printk(KERN_ERR PFX "Detected HP ZX1 "
502 "AGP LBA but no IOC.\n");
503 return AE_OK;
504 }
505 }
506 }
507
508 status = acpi_get_parent(handle, &parent);
509 handle = parent;
510 } while (ACPI_SUCCESS(status));
511
512 if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa))
513 return AE_OK;
514
515 printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset "
516 "(ioc=%llx, lba=%llx)\n", (char *)context,
517 sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa);
518
519 hp_zx1_gart_found = 1;
520 return AE_CTRL_TERMINATE;
521}
522
523static int __init
524agp_hp_init (void)
525{
526 if (agp_off)
527 return -EINVAL;
528
529 acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
530 if (hp_zx1_gart_found)
531 return 0;
532
533 acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL);
534 if (hp_zx1_gart_found)
535 return 0;
536
537 return -ENODEV;
538}
539
540static void __exit
541agp_hp_cleanup (void)
542{
543}
544
545module_init(agp_hp_init);
546module_exit(agp_hp_cleanup);
547
548MODULE_LICENSE("GPL and additional rights");
549
