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55
56#if defined(__i386__)
57# define BREAKPOINT() asm(" int $3");
58#else
59# define BREAKPOINT() { }
60#endif
61
62#define MAX_ISA_DEVICES 10
63#define MAX_PCI_DEVICES 10
64#define MAX_TOTAL_DEVICES 20
65
66#include <linux/module.h>
67#include <linux/errno.h>
68#include <linux/signal.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/pci.h>
73#include <linux/tty.h>
74#include <linux/tty_flip.h>
75#include <linux/serial.h>
76#include <linux/major.h>
77#include <linux/string.h>
78#include <linux/fcntl.h>
79#include <linux/ptrace.h>
80#include <linux/ioport.h>
81#include <linux/mm.h>
82#include <linux/seq_file.h>
83#include <linux/slab.h>
84#include <linux/smp_lock.h>
85#include <linux/delay.h>
86#include <linux/netdevice.h>
87#include <linux/vmalloc.h>
88#include <linux/init.h>
89#include <linux/ioctl.h>
90#include <linux/synclink.h>
91
92#include <asm/system.h>
93#include <asm/io.h>
94#include <asm/irq.h>
95#include <asm/dma.h>
96#include <linux/bitops.h>
97#include <asm/types.h>
98#include <linux/termios.h>
99#include <linux/workqueue.h>
100#include <linux/hdlc.h>
101#include <linux/dma-mapping.h>
102
103#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
104#define SYNCLINK_GENERIC_HDLC 1
105#else
106#define SYNCLINK_GENERIC_HDLC 0
107#endif
108
109#define GET_USER(error,value,addr) error = get_user(value,addr)
110#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111#define PUT_USER(error,value,addr) error = put_user(value,addr)
112#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
113
114#include <asm/uaccess.h>
115
116#define RCLRVALUE 0xffff
117
118static MGSL_PARAMS default_params = {
119 MGSL_MODE_HDLC,
120 0,
121 HDLC_FLAG_UNDERRUN_ABORT15,
122 HDLC_ENCODING_NRZI_SPACE,
123 0,
124 0xff,
125 HDLC_CRC_16_CCITT,
126 HDLC_PREAMBLE_LENGTH_8BITS,
127 HDLC_PREAMBLE_PATTERN_NONE,
128 9600,
129 8,
130 1,
131 ASYNC_PARITY_NONE
132};
133
134#define SHARED_MEM_ADDRESS_SIZE 0x40000
135#define BUFFERLISTSIZE 4096
136#define DMABUFFERSIZE 4096
137#define MAXRXFRAMES 7
138
139typedef struct _DMABUFFERENTRY
140{
141 u32 phys_addr;
142 volatile u16 count;
143 volatile u16 status;
144 volatile u16 rcc;
145 u16 reserved;
146 u32 link;
147 char *virt_addr;
148 u32 phys_entry;
149 dma_addr_t dma_addr;
150} DMABUFFERENTRY, *DMAPBUFFERENTRY;
151
152
153
154#define BH_RECEIVE 1
155#define BH_TRANSMIT 2
156#define BH_STATUS 4
157
158#define IO_PIN_SHUTDOWN_LIMIT 100
159
160struct _input_signal_events {
161 int ri_up;
162 int ri_down;
163 int dsr_up;
164 int dsr_down;
165 int dcd_up;
166 int dcd_down;
167 int cts_up;
168 int cts_down;
169};
170
171
172#define MAX_TX_HOLDING_BUFFERS 5
173struct tx_holding_buffer {
174 int buffer_size;
175 unsigned char * buffer;
176};
177
178
179
180
181
182
183struct mgsl_struct {
184 int magic;
185 struct tty_port port;
186 int line;
187 int hw_version;
188
189 struct mgsl_icount icount;
190
191 int timeout;
192 int x_char;
193 u16 read_status_mask;
194 u16 ignore_status_mask;
195 unsigned char *xmit_buf;
196 int xmit_head;
197 int xmit_tail;
198 int xmit_cnt;
199
200 wait_queue_head_t status_event_wait_q;
201 wait_queue_head_t event_wait_q;
202 struct timer_list tx_timer;
203 struct mgsl_struct *next_device;
204
205 spinlock_t irq_spinlock;
206 struct work_struct task;
207
208 u32 EventMask;
209 u32 RecordedEvents;
210
211 u32 max_frame_size;
212
213 u32 pending_bh;
214
215 bool bh_running;
216 int isr_overflow;
217 bool bh_requested;
218
219 int dcd_chkcount;
220 int cts_chkcount;
221 int dsr_chkcount;
222 int ri_chkcount;
223
224 char *buffer_list;
225 u32 buffer_list_phys;
226 dma_addr_t buffer_list_dma_addr;
227
228 unsigned int rx_buffer_count;
229 DMABUFFERENTRY *rx_buffer_list;
230 unsigned int current_rx_buffer;
231
232 int num_tx_dma_buffers;
233 int tx_dma_buffers_used;
234 unsigned int tx_buffer_count;
235 DMABUFFERENTRY *tx_buffer_list;
236 int start_tx_dma_buffer;
237 int current_tx_buffer;
238
239 unsigned char *intermediate_rxbuffer;
240
241 int num_tx_holding_buffers;
242 int get_tx_holding_index;
243 int put_tx_holding_index;
244 int tx_holding_count;
245 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
246
247 bool rx_enabled;
248 bool rx_overflow;
249 bool rx_rcc_underrun;
250
251 bool tx_enabled;
252 bool tx_active;
253 u32 idle_mode;
254
255 u16 cmr_value;
256 u16 tcsr_value;
257
258 char device_name[25];
259
260 unsigned int bus_type;
261 unsigned char bus;
262 unsigned char function;
263
264 unsigned int io_base;
265 unsigned int io_addr_size;
266 bool io_addr_requested;
267
268 unsigned int irq_level;
269 unsigned long irq_flags;
270 bool irq_requested;
271
272 unsigned int dma_level;
273 bool dma_requested;
274
275 u16 mbre_bit;
276 u16 loopback_bits;
277 u16 usc_idle_mode;
278
279 MGSL_PARAMS params;
280
281 unsigned char serial_signals;
282
283 bool irq_occurred;
284 unsigned int init_error;
285 int fDiagnosticsmode;
286
287 u32 last_mem_alloc;
288 unsigned char* memory_base;
289 u32 phys_memory_base;
290 bool shared_mem_requested;
291
292 unsigned char* lcr_base;
293 u32 phys_lcr_base;
294 u32 lcr_offset;
295 bool lcr_mem_requested;
296
297 u32 misc_ctrl_value;
298 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
299 char char_buf[MAX_ASYNC_BUFFER_SIZE];
300 bool drop_rts_on_tx_done;
301
302 bool loopmode_insert_requested;
303 bool loopmode_send_done_requested;
304
305 struct _input_signal_events input_signal_events;
306
307
308 int netcount;
309 spinlock_t netlock;
310
311#if SYNCLINK_GENERIC_HDLC
312 struct net_device *netdev;
313#endif
314};
315
316#define MGSL_MAGIC 0x5401
317
318
319
320
321#ifndef SERIAL_XMIT_SIZE
322#define SERIAL_XMIT_SIZE 4096
323#endif
324
325
326
327
328
329
330
331#define DCPIN 2
332#define SDPIN 4
333
334#define DCAR 0
335#define CCAR SDPIN
336#define DATAREG DCPIN + SDPIN
337#define MSBONLY 0x41
338#define LSBONLY 0x40
339
340
341
342
343
344
345#define CMR 0x02
346#define CCSR 0x04
347#define CCR 0x06
348#define PSR 0x08
349#define PCR 0x0a
350#define TMDR 0x0c
351#define TMCR 0x0e
352#define CMCR 0x10
353#define HCR 0x12
354#define IVR 0x14
355#define IOCR 0x16
356#define ICR 0x18
357#define DCCR 0x1a
358#define MISR 0x1c
359#define SICR 0x1e
360#define RDR 0x20
361#define RMR 0x22
362#define RCSR 0x24
363#define RICR 0x26
364#define RSR 0x28
365#define RCLR 0x2a
366#define RCCR 0x2c
367#define TC0R 0x2e
368#define TDR 0x30
369#define TMR 0x32
370#define TCSR 0x34
371#define TICR 0x36
372#define TSR 0x38
373#define TCLR 0x3a
374#define TCCR 0x3c
375#define TC1R 0x3e
376
377
378
379
380
381
382#define DCR 0x06
383#define DACR 0x08
384#define BDCR 0x12
385#define DIVR 0x14
386#define DICR 0x18
387#define CDIR 0x1a
388#define SDIR 0x1c
389
390#define TDMR 0x02
391#define TDIAR 0x1e
392#define TBCR 0x2a
393#define TARL 0x2c
394#define TARU 0x2e
395#define NTBCR 0x3a
396#define NTARL 0x3c
397#define NTARU 0x3e
398
399#define RDMR 0x82
400#define RDIAR 0x9e
401#define RBCR 0xaa
402#define RARL 0xac
403#define RARU 0xae
404#define NRBCR 0xba
405#define NRARL 0xbc
406#define NRARU 0xbe
407
408
409
410
411
412
413#define MODEMSTATUS_DTR 0x80
414#define MODEMSTATUS_DSR 0x40
415#define MODEMSTATUS_RTS 0x20
416#define MODEMSTATUS_CTS 0x10
417#define MODEMSTATUS_RI 0x04
418#define MODEMSTATUS_DCD 0x01
419
420
421
422
423
424
425#define RTCmd_Null 0x0000
426#define RTCmd_ResetHighestIus 0x1000
427#define RTCmd_TriggerChannelLoadDma 0x2000
428#define RTCmd_TriggerRxDma 0x2800
429#define RTCmd_TriggerTxDma 0x3000
430#define RTCmd_TriggerRxAndTxDma 0x3800
431#define RTCmd_PurgeRxFifo 0x4800
432#define RTCmd_PurgeTxFifo 0x5000
433#define RTCmd_PurgeRxAndTxFifo 0x5800
434#define RTCmd_LoadRcc 0x6800
435#define RTCmd_LoadTcc 0x7000
436#define RTCmd_LoadRccAndTcc 0x7800
437#define RTCmd_LoadTC0 0x8800
438#define RTCmd_LoadTC1 0x9000
439#define RTCmd_LoadTC0AndTC1 0x9800
440#define RTCmd_SerialDataLSBFirst 0xa000
441#define RTCmd_SerialDataMSBFirst 0xa800
442#define RTCmd_SelectBigEndian 0xb000
443#define RTCmd_SelectLittleEndian 0xb800
444
445
446
447
448
449
450#define DmaCmd_Null 0x0000
451#define DmaCmd_ResetTxChannel 0x1000
452#define DmaCmd_ResetRxChannel 0x1200
453#define DmaCmd_StartTxChannel 0x2000
454#define DmaCmd_StartRxChannel 0x2200
455#define DmaCmd_ContinueTxChannel 0x3000
456#define DmaCmd_ContinueRxChannel 0x3200
457#define DmaCmd_PauseTxChannel 0x4000
458#define DmaCmd_PauseRxChannel 0x4200
459#define DmaCmd_AbortTxChannel 0x5000
460#define DmaCmd_AbortRxChannel 0x5200
461#define DmaCmd_InitTxChannel 0x7000
462#define DmaCmd_InitRxChannel 0x7200
463#define DmaCmd_ResetHighestDmaIus 0x8000
464#define DmaCmd_ResetAllChannels 0x9000
465#define DmaCmd_StartAllChannels 0xa000
466#define DmaCmd_ContinueAllChannels 0xb000
467#define DmaCmd_PauseAllChannels 0xc000
468#define DmaCmd_AbortAllChannels 0xd000
469#define DmaCmd_InitAllChannels 0xf000
470
471#define TCmd_Null 0x0000
472#define TCmd_ClearTxCRC 0x2000
473#define TCmd_SelectTicrTtsaData 0x4000
474#define TCmd_SelectTicrTxFifostatus 0x5000
475#define TCmd_SelectTicrIntLevel 0x6000
476#define TCmd_SelectTicrdma_level 0x7000
477#define TCmd_SendFrame 0x8000
478#define TCmd_SendAbort 0x9000
479#define TCmd_EnableDleInsertion 0xc000
480#define TCmd_DisableDleInsertion 0xd000
481#define TCmd_ClearEofEom 0xe000
482#define TCmd_SetEofEom 0xf000
483
484#define RCmd_Null 0x0000
485#define RCmd_ClearRxCRC 0x2000
486#define RCmd_EnterHuntmode 0x3000
487#define RCmd_SelectRicrRtsaData 0x4000
488#define RCmd_SelectRicrRxFifostatus 0x5000
489#define RCmd_SelectRicrIntLevel 0x6000
490#define RCmd_SelectRicrdma_level 0x7000
491
492
493
494
495
496#define RECEIVE_STATUS BIT5
497#define RECEIVE_DATA BIT4
498#define TRANSMIT_STATUS BIT3
499#define TRANSMIT_DATA BIT2
500#define IO_PIN BIT1
501#define MISC BIT0
502
503
504
505
506
507
508#define RXSTATUS_SHORT_FRAME BIT8
509#define RXSTATUS_CODE_VIOLATION BIT8
510#define RXSTATUS_EXITED_HUNT BIT7
511#define RXSTATUS_IDLE_RECEIVED BIT6
512#define RXSTATUS_BREAK_RECEIVED BIT5
513#define RXSTATUS_ABORT_RECEIVED BIT5
514#define RXSTATUS_RXBOUND BIT4
515#define RXSTATUS_CRC_ERROR BIT3
516#define RXSTATUS_FRAMING_ERROR BIT3
517#define RXSTATUS_ABORT BIT2
518#define RXSTATUS_PARITY_ERROR BIT2
519#define RXSTATUS_OVERRUN BIT1
520#define RXSTATUS_DATA_AVAILABLE BIT0
521#define RXSTATUS_ALL 0x01f6
522#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
523
524
525
526
527
528#define IDLEMODE_FLAGS 0x0000
529#define IDLEMODE_ALT_ONE_ZERO 0x0100
530#define IDLEMODE_ZERO 0x0200
531#define IDLEMODE_ONE 0x0300
532#define IDLEMODE_ALT_MARK_SPACE 0x0500
533#define IDLEMODE_SPACE 0x0600
534#define IDLEMODE_MARK 0x0700
535#define IDLEMODE_MASK 0x0700
536
537
538
539
540#define IUSC_SL1660 0x4d44
541#define IUSC_PRE_SL1660 0x4553
542
543
544
545
546
547#define TCSR_PRESERVE 0x0F00
548
549#define TCSR_UNDERWAIT BIT11
550#define TXSTATUS_PREAMBLE_SENT BIT7
551#define TXSTATUS_IDLE_SENT BIT6
552#define TXSTATUS_ABORT_SENT BIT5
553#define TXSTATUS_EOF_SENT BIT4
554#define TXSTATUS_EOM_SENT BIT4
555#define TXSTATUS_CRC_SENT BIT3
556#define TXSTATUS_ALL_SENT BIT2
557#define TXSTATUS_UNDERRUN BIT1
558#define TXSTATUS_FIFO_EMPTY BIT0
559#define TXSTATUS_ALL 0x00fa
560#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
561
562
563#define MISCSTATUS_RXC_LATCHED BIT15
564#define MISCSTATUS_RXC BIT14
565#define MISCSTATUS_TXC_LATCHED BIT13
566#define MISCSTATUS_TXC BIT12
567#define MISCSTATUS_RI_LATCHED BIT11
568#define MISCSTATUS_RI BIT10
569#define MISCSTATUS_DSR_LATCHED BIT9
570#define MISCSTATUS_DSR BIT8
571#define MISCSTATUS_DCD_LATCHED BIT7
572#define MISCSTATUS_DCD BIT6
573#define MISCSTATUS_CTS_LATCHED BIT5
574#define MISCSTATUS_CTS BIT4
575#define MISCSTATUS_RCC_UNDERRUN BIT3
576#define MISCSTATUS_DPLL_NO_SYNC BIT2
577#define MISCSTATUS_BRG1_ZERO BIT1
578#define MISCSTATUS_BRG0_ZERO BIT0
579
580#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
581#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
582
583#define SICR_RXC_ACTIVE BIT15
584#define SICR_RXC_INACTIVE BIT14
585#define SICR_RXC (BIT15+BIT14)
586#define SICR_TXC_ACTIVE BIT13
587#define SICR_TXC_INACTIVE BIT12
588#define SICR_TXC (BIT13+BIT12)
589#define SICR_RI_ACTIVE BIT11
590#define SICR_RI_INACTIVE BIT10
591#define SICR_RI (BIT11+BIT10)
592#define SICR_DSR_ACTIVE BIT9
593#define SICR_DSR_INACTIVE BIT8
594#define SICR_DSR (BIT9+BIT8)
595#define SICR_DCD_ACTIVE BIT7
596#define SICR_DCD_INACTIVE BIT6
597#define SICR_DCD (BIT7+BIT6)
598#define SICR_CTS_ACTIVE BIT5
599#define SICR_CTS_INACTIVE BIT4
600#define SICR_CTS (BIT5+BIT4)
601#define SICR_RCC_UNDERFLOW BIT3
602#define SICR_DPLL_NO_SYNC BIT2
603#define SICR_BRG1_ZERO BIT1
604#define SICR_BRG0_ZERO BIT0
605
606void usc_DisableMasterIrqBit( struct mgsl_struct *info );
607void usc_EnableMasterIrqBit( struct mgsl_struct *info );
608void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
609void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
610void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
611
612#define usc_EnableInterrupts( a, b ) \
613 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
614
615#define usc_DisableInterrupts( a, b ) \
616 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
617
618#define usc_EnableMasterIrqBit(a) \
619 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
620
621#define usc_DisableMasterIrqBit(a) \
622 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
623
624#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
625
626
627
628
629
630
631#define TXSTATUS_PREAMBLE_SENT BIT7
632#define TXSTATUS_IDLE_SENT BIT6
633#define TXSTATUS_ABORT_SENT BIT5
634#define TXSTATUS_EOF BIT4
635#define TXSTATUS_CRC_SENT BIT3
636#define TXSTATUS_ALL_SENT BIT2
637#define TXSTATUS_UNDERRUN BIT1
638#define TXSTATUS_FIFO_EMPTY BIT0
639
640#define DICR_MASTER BIT15
641#define DICR_TRANSMIT BIT0
642#define DICR_RECEIVE BIT1
643
644#define usc_EnableDmaInterrupts(a,b) \
645 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
646
647#define usc_DisableDmaInterrupts(a,b) \
648 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
649
650#define usc_EnableStatusIrqs(a,b) \
651 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
652
653#define usc_DisablestatusIrqs(a,b) \
654 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
655
656
657
658
659
660#define DISABLE_UNCONDITIONAL 0
661#define DISABLE_END_OF_FRAME 1
662#define ENABLE_UNCONDITIONAL 2
663#define ENABLE_AUTO_CTS 3
664#define ENABLE_AUTO_DCD 3
665#define usc_EnableTransmitter(a,b) \
666 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
667#define usc_EnableReceiver(a,b) \
668 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
669
670static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
671static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
672static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
673
674static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
675static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
676static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
677void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
678void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
679
680#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
681#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
682
683#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
684
685static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
686static void usc_start_receiver( struct mgsl_struct *info );
687static void usc_stop_receiver( struct mgsl_struct *info );
688
689static void usc_start_transmitter( struct mgsl_struct *info );
690static void usc_stop_transmitter( struct mgsl_struct *info );
691static void usc_set_txidle( struct mgsl_struct *info );
692static void usc_load_txfifo( struct mgsl_struct *info );
693
694static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
695static void usc_enable_loopback( struct mgsl_struct *info, int enable );
696
697static void usc_get_serial_signals( struct mgsl_struct *info );
698static void usc_set_serial_signals( struct mgsl_struct *info );
699
700static void usc_reset( struct mgsl_struct *info );
701
702static void usc_set_sync_mode( struct mgsl_struct *info );
703static void usc_set_sdlc_mode( struct mgsl_struct *info );
704static void usc_set_async_mode( struct mgsl_struct *info );
705static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
706
707static void usc_loopback_frame( struct mgsl_struct *info );
708
709static void mgsl_tx_timeout(unsigned long context);
710
711
712static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
713static void usc_loopmode_insert_request( struct mgsl_struct * info );
714static int usc_loopmode_active( struct mgsl_struct * info);
715static void usc_loopmode_send_done( struct mgsl_struct * info );
716
717static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
718
719#if SYNCLINK_GENERIC_HDLC
720#define dev_to_port(D) (dev_to_hdlc(D)->priv)
721static void hdlcdev_tx_done(struct mgsl_struct *info);
722static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
723static int hdlcdev_init(struct mgsl_struct *info);
724static void hdlcdev_exit(struct mgsl_struct *info);
725#endif
726
727
728
729
730
731
732#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
733(0x00400020 + \
734((WrHold) << 30) + \
735((WrDly) << 28) + \
736((RdDly) << 26) + \
737((Nwdd) << 20) + \
738((Nwad) << 15) + \
739((Nxda) << 13) + \
740((Nrdd) << 11) + \
741((Nrad) << 6) )
742
743static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
744
745
746
747
748static bool mgsl_register_test( struct mgsl_struct *info );
749static bool mgsl_irq_test( struct mgsl_struct *info );
750static bool mgsl_dma_test( struct mgsl_struct *info );
751static bool mgsl_memory_test( struct mgsl_struct *info );
752static int mgsl_adapter_test( struct mgsl_struct *info );
753
754
755
756
757static int mgsl_claim_resources(struct mgsl_struct *info);
758static void mgsl_release_resources(struct mgsl_struct *info);
759static void mgsl_add_device(struct mgsl_struct *info);
760static struct mgsl_struct* mgsl_allocate_device(void);
761
762
763
764
765static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
766static bool mgsl_get_rx_frame( struct mgsl_struct *info );
767static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
768static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
769static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
770static int num_free_tx_dma_buffers(struct mgsl_struct *info);
771static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
772static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
773
774
775
776
777static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
778static void mgsl_free_dma_buffers(struct mgsl_struct *info);
779static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
780static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
781static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
782static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
783static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
784static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
785static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
786static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
787static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
788static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
789
790
791
792
793static void mgsl_bh_handler(struct work_struct *work);
794static void mgsl_bh_receive(struct mgsl_struct *info);
795static void mgsl_bh_transmit(struct mgsl_struct *info);
796static void mgsl_bh_status(struct mgsl_struct *info);
797
798
799
800
801static void mgsl_isr_null( struct mgsl_struct *info );
802static void mgsl_isr_transmit_data( struct mgsl_struct *info );
803static void mgsl_isr_receive_data( struct mgsl_struct *info );
804static void mgsl_isr_receive_status( struct mgsl_struct *info );
805static void mgsl_isr_transmit_status( struct mgsl_struct *info );
806static void mgsl_isr_io_pin( struct mgsl_struct *info );
807static void mgsl_isr_misc( struct mgsl_struct *info );
808static void mgsl_isr_receive_dma( struct mgsl_struct *info );
809static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
810
811typedef void (*isr_dispatch_func)(struct mgsl_struct *);
812
813static isr_dispatch_func UscIsrTable[7] =
814{
815 mgsl_isr_null,
816 mgsl_isr_misc,
817 mgsl_isr_io_pin,
818 mgsl_isr_transmit_data,
819 mgsl_isr_transmit_status,
820 mgsl_isr_receive_data,
821 mgsl_isr_receive_status
822};
823
824
825
826
827static int tiocmget(struct tty_struct *tty, struct file *file);
828static int tiocmset(struct tty_struct *tty, struct file *file,
829 unsigned int set, unsigned int clear);
830static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
831 __user *user_icount);
832static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
833static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
834static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
835static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
836static int mgsl_txenable(struct mgsl_struct * info, int enable);
837static int mgsl_txabort(struct mgsl_struct * info);
838static int mgsl_rxenable(struct mgsl_struct * info, int enable);
839static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
840static int mgsl_loopmode_send_done( struct mgsl_struct * info );
841
842
843static bool pci_registered;
844
845
846
847
848static struct mgsl_struct *mgsl_device_list;
849static int mgsl_device_count;
850
851
852
853
854
855
856static int break_on_load;
857
858
859
860
861
862static int ttymajor;
863
864
865
866
867static int io[MAX_ISA_DEVICES];
868static int irq[MAX_ISA_DEVICES];
869static int dma[MAX_ISA_DEVICES];
870static int debug_level;
871static int maxframe[MAX_TOTAL_DEVICES];
872static int txdmabufs[MAX_TOTAL_DEVICES];
873static int txholdbufs[MAX_TOTAL_DEVICES];
874
875module_param(break_on_load, bool, 0);
876module_param(ttymajor, int, 0);
877module_param_array(io, int, NULL, 0);
878module_param_array(irq, int, NULL, 0);
879module_param_array(dma, int, NULL, 0);
880module_param(debug_level, int, 0);
881module_param_array(maxframe, int, NULL, 0);
882module_param_array(txdmabufs, int, NULL, 0);
883module_param_array(txholdbufs, int, NULL, 0);
884
885static char *driver_name = "SyncLink serial driver";
886static char *driver_version = "$Revision: 4.38 $";
887
888static int synclink_init_one (struct pci_dev *dev,
889 const struct pci_device_id *ent);
890static void synclink_remove_one (struct pci_dev *dev);
891
892static struct pci_device_id synclink_pci_tbl[] = {
893 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
894 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
895 { 0, },
896};
897MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
898
899MODULE_LICENSE("GPL");
900
901static struct pci_driver synclink_pci_driver = {
902 .name = "synclink",
903 .id_table = synclink_pci_tbl,
904 .probe = synclink_init_one,
905 .remove = __devexit_p(synclink_remove_one),
906};
907
908static struct tty_driver *serial_driver;
909
910
911#define WAKEUP_CHARS 256
912
913
914static void mgsl_change_params(struct mgsl_struct *info);
915static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
916
917
918
919
920
921
922
923static void* mgsl_get_text_ptr(void)
924{
925 return mgsl_get_text_ptr;
926}
927
928static inline int mgsl_paranoia_check(struct mgsl_struct *info,
929 char *name, const char *routine)
930{
931#ifdef MGSL_PARANOIA_CHECK
932 static const char *badmagic =
933 "Warning: bad magic number for mgsl struct (%s) in %s\n";
934 static const char *badinfo =
935 "Warning: null mgsl_struct for (%s) in %s\n";
936
937 if (!info) {
938 printk(badinfo, name, routine);
939 return 1;
940 }
941 if (info->magic != MGSL_MAGIC) {
942 printk(badmagic, name, routine);
943 return 1;
944 }
945#else
946 if (!info)
947 return 1;
948#endif
949 return 0;
950}
951
952
953
954
955
956
957
958
959
960
961static void ldisc_receive_buf(struct tty_struct *tty,
962 const __u8 *data, char *flags, int count)
963{
964 struct tty_ldisc *ld;
965 if (!tty)
966 return;
967 ld = tty_ldisc_ref(tty);
968 if (ld) {
969 if (ld->ops->receive_buf)
970 ld->ops->receive_buf(tty, data, flags, count);
971 tty_ldisc_deref(ld);
972 }
973}
974
975
976
977
978
979
980static void mgsl_stop(struct tty_struct *tty)
981{
982 struct mgsl_struct *info = tty->driver_data;
983 unsigned long flags;
984
985 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
986 return;
987
988 if ( debug_level >= DEBUG_LEVEL_INFO )
989 printk("mgsl_stop(%s)\n",info->device_name);
990
991 spin_lock_irqsave(&info->irq_spinlock,flags);
992 if (info->tx_enabled)
993 usc_stop_transmitter(info);
994 spin_unlock_irqrestore(&info->irq_spinlock,flags);
995
996}
997
998
999
1000
1001
1002
1003static void mgsl_start(struct tty_struct *tty)
1004{
1005 struct mgsl_struct *info = tty->driver_data;
1006 unsigned long flags;
1007
1008 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1009 return;
1010
1011 if ( debug_level >= DEBUG_LEVEL_INFO )
1012 printk("mgsl_start(%s)\n",info->device_name);
1013
1014 spin_lock_irqsave(&info->irq_spinlock,flags);
1015 if (!info->tx_enabled)
1016 usc_start_transmitter(info);
1017 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1018
1019}
1020
1021
1022
1023
1024
1025
1026
1027
1028static int mgsl_bh_action(struct mgsl_struct *info)
1029{
1030 unsigned long flags;
1031 int rc = 0;
1032
1033 spin_lock_irqsave(&info->irq_spinlock,flags);
1034
1035 if (info->pending_bh & BH_RECEIVE) {
1036 info->pending_bh &= ~BH_RECEIVE;
1037 rc = BH_RECEIVE;
1038 } else if (info->pending_bh & BH_TRANSMIT) {
1039 info->pending_bh &= ~BH_TRANSMIT;
1040 rc = BH_TRANSMIT;
1041 } else if (info->pending_bh & BH_STATUS) {
1042 info->pending_bh &= ~BH_STATUS;
1043 rc = BH_STATUS;
1044 }
1045
1046 if (!rc) {
1047
1048 info->bh_running = false;
1049 info->bh_requested = false;
1050 }
1051
1052 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1053
1054 return rc;
1055}
1056
1057
1058
1059
1060static void mgsl_bh_handler(struct work_struct *work)
1061{
1062 struct mgsl_struct *info =
1063 container_of(work, struct mgsl_struct, task);
1064 int action;
1065
1066 if (!info)
1067 return;
1068
1069 if ( debug_level >= DEBUG_LEVEL_BH )
1070 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1071 __FILE__,__LINE__,info->device_name);
1072
1073 info->bh_running = true;
1074
1075 while((action = mgsl_bh_action(info)) != 0) {
1076
1077
1078 if ( debug_level >= DEBUG_LEVEL_BH )
1079 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1080 __FILE__,__LINE__,action);
1081
1082 switch (action) {
1083
1084 case BH_RECEIVE:
1085 mgsl_bh_receive(info);
1086 break;
1087 case BH_TRANSMIT:
1088 mgsl_bh_transmit(info);
1089 break;
1090 case BH_STATUS:
1091 mgsl_bh_status(info);
1092 break;
1093 default:
1094
1095 printk("Unknown work item ID=%08X!\n", action);
1096 break;
1097 }
1098 }
1099
1100 if ( debug_level >= DEBUG_LEVEL_BH )
1101 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1102 __FILE__,__LINE__,info->device_name);
1103}
1104
1105static void mgsl_bh_receive(struct mgsl_struct *info)
1106{
1107 bool (*get_rx_frame)(struct mgsl_struct *info) =
1108 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1109
1110 if ( debug_level >= DEBUG_LEVEL_BH )
1111 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1112 __FILE__,__LINE__,info->device_name);
1113
1114 do
1115 {
1116 if (info->rx_rcc_underrun) {
1117 unsigned long flags;
1118 spin_lock_irqsave(&info->irq_spinlock,flags);
1119 usc_start_receiver(info);
1120 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1121 return;
1122 }
1123 } while(get_rx_frame(info));
1124}
1125
1126static void mgsl_bh_transmit(struct mgsl_struct *info)
1127{
1128 struct tty_struct *tty = info->port.tty;
1129 unsigned long flags;
1130
1131 if ( debug_level >= DEBUG_LEVEL_BH )
1132 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1133 __FILE__,__LINE__,info->device_name);
1134
1135 if (tty)
1136 tty_wakeup(tty);
1137
1138
1139
1140
1141 spin_lock_irqsave(&info->irq_spinlock,flags);
1142 if ( !info->tx_active && info->loopmode_send_done_requested )
1143 usc_loopmode_send_done( info );
1144 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1145}
1146
1147static void mgsl_bh_status(struct mgsl_struct *info)
1148{
1149 if ( debug_level >= DEBUG_LEVEL_BH )
1150 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1151 __FILE__,__LINE__,info->device_name);
1152
1153 info->ri_chkcount = 0;
1154 info->dsr_chkcount = 0;
1155 info->dcd_chkcount = 0;
1156 info->cts_chkcount = 0;
1157}
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168static void mgsl_isr_receive_status( struct mgsl_struct *info )
1169{
1170 u16 status = usc_InReg( info, RCSR );
1171
1172 if ( debug_level >= DEBUG_LEVEL_ISR )
1173 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1174 __FILE__,__LINE__,status);
1175
1176 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1177 info->loopmode_insert_requested &&
1178 usc_loopmode_active(info) )
1179 {
1180 ++info->icount.rxabort;
1181 info->loopmode_insert_requested = false;
1182
1183
1184 info->cmr_value &= ~BIT13;
1185 usc_OutReg(info, CMR, info->cmr_value);
1186
1187
1188 usc_OutReg(info, RICR,
1189 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1190 }
1191
1192 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1193 if (status & RXSTATUS_EXITED_HUNT)
1194 info->icount.exithunt++;
1195 if (status & RXSTATUS_IDLE_RECEIVED)
1196 info->icount.rxidle++;
1197 wake_up_interruptible(&info->event_wait_q);
1198 }
1199
1200 if (status & RXSTATUS_OVERRUN){
1201 info->icount.rxover++;
1202 usc_process_rxoverrun_sync( info );
1203 }
1204
1205 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1206 usc_UnlatchRxstatusBits( info, status );
1207
1208}
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1221{
1222 u16 status = usc_InReg( info, TCSR );
1223
1224 if ( debug_level >= DEBUG_LEVEL_ISR )
1225 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1226 __FILE__,__LINE__,status);
1227
1228 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1229 usc_UnlatchTxstatusBits( info, status );
1230
1231 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1232 {
1233
1234
1235
1236
1237
1238 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1239 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1240 }
1241
1242 if ( status & TXSTATUS_EOF_SENT )
1243 info->icount.txok++;
1244 else if ( status & TXSTATUS_UNDERRUN )
1245 info->icount.txunder++;
1246 else if ( status & TXSTATUS_ABORT_SENT )
1247 info->icount.txabort++;
1248 else
1249 info->icount.txunder++;
1250
1251 info->tx_active = false;
1252 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1253 del_timer(&info->tx_timer);
1254
1255 if ( info->drop_rts_on_tx_done ) {
1256 usc_get_serial_signals( info );
1257 if ( info->serial_signals & SerialSignal_RTS ) {
1258 info->serial_signals &= ~SerialSignal_RTS;
1259 usc_set_serial_signals( info );
1260 }
1261 info->drop_rts_on_tx_done = false;
1262 }
1263
1264#if SYNCLINK_GENERIC_HDLC
1265 if (info->netcount)
1266 hdlcdev_tx_done(info);
1267 else
1268#endif
1269 {
1270 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1271 usc_stop_transmitter(info);
1272 return;
1273 }
1274 info->pending_bh |= BH_TRANSMIT;
1275 }
1276
1277}
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287static void mgsl_isr_io_pin( struct mgsl_struct *info )
1288{
1289 struct mgsl_icount *icount;
1290 u16 status = usc_InReg( info, MISR );
1291
1292 if ( debug_level >= DEBUG_LEVEL_ISR )
1293 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1294 __FILE__,__LINE__,status);
1295
1296 usc_ClearIrqPendingBits( info, IO_PIN );
1297 usc_UnlatchIostatusBits( info, status );
1298
1299 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1300 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1301 icount = &info->icount;
1302
1303 if (status & MISCSTATUS_RI_LATCHED) {
1304 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1305 usc_DisablestatusIrqs(info,SICR_RI);
1306 icount->rng++;
1307 if ( status & MISCSTATUS_RI )
1308 info->input_signal_events.ri_up++;
1309 else
1310 info->input_signal_events.ri_down++;
1311 }
1312 if (status & MISCSTATUS_DSR_LATCHED) {
1313 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1314 usc_DisablestatusIrqs(info,SICR_DSR);
1315 icount->dsr++;
1316 if ( status & MISCSTATUS_DSR )
1317 info->input_signal_events.dsr_up++;
1318 else
1319 info->input_signal_events.dsr_down++;
1320 }
1321 if (status & MISCSTATUS_DCD_LATCHED) {
1322 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1323 usc_DisablestatusIrqs(info,SICR_DCD);
1324 icount->dcd++;
1325 if (status & MISCSTATUS_DCD) {
1326 info->input_signal_events.dcd_up++;
1327 } else
1328 info->input_signal_events.dcd_down++;
1329#if SYNCLINK_GENERIC_HDLC
1330 if (info->netcount) {
1331 if (status & MISCSTATUS_DCD)
1332 netif_carrier_on(info->netdev);
1333 else
1334 netif_carrier_off(info->netdev);
1335 }
1336#endif
1337 }
1338 if (status & MISCSTATUS_CTS_LATCHED)
1339 {
1340 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1341 usc_DisablestatusIrqs(info,SICR_CTS);
1342 icount->cts++;
1343 if ( status & MISCSTATUS_CTS )
1344 info->input_signal_events.cts_up++;
1345 else
1346 info->input_signal_events.cts_down++;
1347 }
1348 wake_up_interruptible(&info->status_event_wait_q);
1349 wake_up_interruptible(&info->event_wait_q);
1350
1351 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1352 (status & MISCSTATUS_DCD_LATCHED) ) {
1353 if ( debug_level >= DEBUG_LEVEL_ISR )
1354 printk("%s CD now %s...", info->device_name,
1355 (status & MISCSTATUS_DCD) ? "on" : "off");
1356 if (status & MISCSTATUS_DCD)
1357 wake_up_interruptible(&info->port.open_wait);
1358 else {
1359 if ( debug_level >= DEBUG_LEVEL_ISR )
1360 printk("doing serial hangup...");
1361 if (info->port.tty)
1362 tty_hangup(info->port.tty);
1363 }
1364 }
1365
1366 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1367 (status & MISCSTATUS_CTS_LATCHED) ) {
1368 if (info->port.tty->hw_stopped) {
1369 if (status & MISCSTATUS_CTS) {
1370 if ( debug_level >= DEBUG_LEVEL_ISR )
1371 printk("CTS tx start...");
1372 if (info->port.tty)
1373 info->port.tty->hw_stopped = 0;
1374 usc_start_transmitter(info);
1375 info->pending_bh |= BH_TRANSMIT;
1376 return;
1377 }
1378 } else {
1379 if (!(status & MISCSTATUS_CTS)) {
1380 if ( debug_level >= DEBUG_LEVEL_ISR )
1381 printk("CTS tx stop...");
1382 if (info->port.tty)
1383 info->port.tty->hw_stopped = 1;
1384 usc_stop_transmitter(info);
1385 }
1386 }
1387 }
1388 }
1389
1390 info->pending_bh |= BH_STATUS;
1391
1392
1393 if ( status & MISCSTATUS_TXC_LATCHED ){
1394 usc_OutReg( info, SICR,
1395 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1396 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1397 info->irq_occurred = true;
1398 }
1399
1400}
1401
1402
1403
1404
1405
1406
1407
1408
1409static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1410{
1411 if ( debug_level >= DEBUG_LEVEL_ISR )
1412 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1413 __FILE__,__LINE__,info->xmit_cnt);
1414
1415 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1416
1417 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1418 usc_stop_transmitter(info);
1419 return;
1420 }
1421
1422 if ( info->xmit_cnt )
1423 usc_load_txfifo( info );
1424 else
1425 info->tx_active = false;
1426
1427 if (info->xmit_cnt < WAKEUP_CHARS)
1428 info->pending_bh |= BH_TRANSMIT;
1429
1430}
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441static void mgsl_isr_receive_data( struct mgsl_struct *info )
1442{
1443 int Fifocount;
1444 u16 status;
1445 int work = 0;
1446 unsigned char DataByte;
1447 struct tty_struct *tty = info->port.tty;
1448 struct mgsl_icount *icount = &info->icount;
1449
1450 if ( debug_level >= DEBUG_LEVEL_ISR )
1451 printk("%s(%d):mgsl_isr_receive_data\n",
1452 __FILE__,__LINE__);
1453
1454 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1455
1456
1457 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1458
1459
1460
1461 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1462
1463
1464
1465 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1466 int flag;
1467
1468
1469 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1470 info->io_base + CCAR );
1471 DataByte = inb( info->io_base + CCAR );
1472
1473
1474 status = usc_InReg(info, RCSR);
1475 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1476 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1477 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1478
1479 icount->rx++;
1480
1481 flag = 0;
1482 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1483 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1484 printk("rxerr=%04X\n",status);
1485
1486 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1487 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1488 icount->brk++;
1489 } else if (status & RXSTATUS_PARITY_ERROR)
1490 icount->parity++;
1491 else if (status & RXSTATUS_FRAMING_ERROR)
1492 icount->frame++;
1493 else if (status & RXSTATUS_OVERRUN) {
1494
1495
1496 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1497 icount->overrun++;
1498 }
1499
1500
1501 if (status & info->ignore_status_mask)
1502 continue;
1503
1504 status &= info->read_status_mask;
1505
1506 if (status & RXSTATUS_BREAK_RECEIVED) {
1507 flag = TTY_BREAK;
1508 if (info->port.flags & ASYNC_SAK)
1509 do_SAK(tty);
1510 } else if (status & RXSTATUS_PARITY_ERROR)
1511 flag = TTY_PARITY;
1512 else if (status & RXSTATUS_FRAMING_ERROR)
1513 flag = TTY_FRAME;
1514 }
1515 tty_insert_flip_char(tty, DataByte, flag);
1516 if (status & RXSTATUS_OVERRUN) {
1517
1518
1519
1520
1521 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1522 }
1523 }
1524
1525 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1526 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1527 __FILE__,__LINE__,icount->rx,icount->brk,
1528 icount->parity,icount->frame,icount->overrun);
1529 }
1530
1531 if(work)
1532 tty_flip_buffer_push(tty);
1533}
1534
1535
1536
1537
1538
1539
1540
1541
1542static void mgsl_isr_misc( struct mgsl_struct *info )
1543{
1544 u16 status = usc_InReg( info, MISR );
1545
1546 if ( debug_level >= DEBUG_LEVEL_ISR )
1547 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1548 __FILE__,__LINE__,status);
1549
1550 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1551 (info->params.mode == MGSL_MODE_HDLC)) {
1552
1553
1554 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1555 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1556 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1557 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1558 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1559
1560
1561 info->pending_bh |= BH_RECEIVE;
1562 info->rx_rcc_underrun = true;
1563 }
1564
1565 usc_ClearIrqPendingBits( info, MISC );
1566 usc_UnlatchMiscstatusBits( info, status );
1567
1568}
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578static void mgsl_isr_null( struct mgsl_struct *info )
1579{
1580
1581}
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1603{
1604 u16 status;
1605
1606
1607 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1608
1609
1610
1611 status = usc_InDmaReg( info, RDMR );
1612
1613 if ( debug_level >= DEBUG_LEVEL_ISR )
1614 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1615 __FILE__,__LINE__,info->device_name,status);
1616
1617 info->pending_bh |= BH_RECEIVE;
1618
1619 if ( status & BIT3 ) {
1620 info->rx_overflow = true;
1621 info->icount.buf_overrun++;
1622 }
1623
1624}
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1647{
1648 u16 status;
1649
1650
1651 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1652
1653
1654
1655
1656 status = usc_InDmaReg( info, TDMR );
1657
1658 if ( debug_level >= DEBUG_LEVEL_ISR )
1659 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1660 __FILE__,__LINE__,info->device_name,status);
1661
1662 if ( status & BIT2 ) {
1663 --info->tx_dma_buffers_used;
1664
1665
1666
1667
1668 if ( load_next_tx_holding_buffer(info) ) {
1669
1670
1671
1672 info->pending_bh |= BH_TRANSMIT;
1673 }
1674 }
1675
1676}
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1690{
1691 struct mgsl_struct *info = dev_id;
1692 u16 UscVector;
1693 u16 DmaVector;
1694
1695 if ( debug_level >= DEBUG_LEVEL_ISR )
1696 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1697 __FILE__, __LINE__, info->irq_level);
1698
1699 spin_lock(&info->irq_spinlock);
1700
1701 for(;;) {
1702
1703 UscVector = usc_InReg(info, IVR) >> 9;
1704 DmaVector = usc_InDmaReg(info, DIVR);
1705
1706 if ( debug_level >= DEBUG_LEVEL_ISR )
1707 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1708 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1709
1710 if ( !UscVector && !DmaVector )
1711 break;
1712
1713
1714 if ( UscVector )
1715 (*UscIsrTable[UscVector])(info);
1716 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1717 mgsl_isr_transmit_dma(info);
1718 else
1719 mgsl_isr_receive_dma(info);
1720
1721 if ( info->isr_overflow ) {
1722 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1723 __FILE__, __LINE__, info->device_name, info->irq_level);
1724 usc_DisableMasterIrqBit(info);
1725 usc_DisableDmaInterrupts(info,DICR_MASTER);
1726 break;
1727 }
1728 }
1729
1730
1731
1732
1733
1734 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1735 if ( debug_level >= DEBUG_LEVEL_ISR )
1736 printk("%s(%d):%s queueing bh task.\n",
1737 __FILE__,__LINE__,info->device_name);
1738 schedule_work(&info->task);
1739 info->bh_requested = true;
1740 }
1741
1742 spin_unlock(&info->irq_spinlock);
1743
1744 if ( debug_level >= DEBUG_LEVEL_ISR )
1745 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1746 __FILE__, __LINE__, info->irq_level);
1747
1748 return IRQ_HANDLED;
1749}
1750
1751
1752
1753
1754
1755
1756
1757
1758static int startup(struct mgsl_struct * info)
1759{
1760 int retval = 0;
1761
1762 if ( debug_level >= DEBUG_LEVEL_INFO )
1763 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1764
1765 if (info->port.flags & ASYNC_INITIALIZED)
1766 return 0;
1767
1768 if (!info->xmit_buf) {
1769
1770 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1771 if (!info->xmit_buf) {
1772 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1773 __FILE__,__LINE__,info->device_name);
1774 return -ENOMEM;
1775 }
1776 }
1777
1778 info->pending_bh = 0;
1779
1780 memset(&info->icount, 0, sizeof(info->icount));
1781
1782 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1783
1784
1785 retval = mgsl_claim_resources(info);
1786
1787
1788 if ( !retval )
1789 retval = mgsl_adapter_test(info);
1790
1791 if ( retval ) {
1792 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1793 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1794 mgsl_release_resources(info);
1795 return retval;
1796 }
1797
1798
1799 mgsl_change_params(info);
1800
1801 if (info->port.tty)
1802 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1803
1804 info->port.flags |= ASYNC_INITIALIZED;
1805
1806 return 0;
1807
1808}
1809
1810
1811
1812
1813
1814
1815
1816
1817static void shutdown(struct mgsl_struct * info)
1818{
1819 unsigned long flags;
1820
1821 if (!(info->port.flags & ASYNC_INITIALIZED))
1822 return;
1823
1824 if (debug_level >= DEBUG_LEVEL_INFO)
1825 printk("%s(%d):mgsl_shutdown(%s)\n",
1826 __FILE__,__LINE__, info->device_name );
1827
1828
1829
1830 wake_up_interruptible(&info->status_event_wait_q);
1831 wake_up_interruptible(&info->event_wait_q);
1832
1833 del_timer_sync(&info->tx_timer);
1834
1835 if (info->xmit_buf) {
1836 free_page((unsigned long) info->xmit_buf);
1837 info->xmit_buf = NULL;
1838 }
1839
1840 spin_lock_irqsave(&info->irq_spinlock,flags);
1841 usc_DisableMasterIrqBit(info);
1842 usc_stop_receiver(info);
1843 usc_stop_transmitter(info);
1844 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1845 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1846 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1847
1848
1849
1850
1851 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1852
1853
1854
1855
1856 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1857
1858 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1859 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1860 usc_set_serial_signals(info);
1861 }
1862
1863 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1864
1865 mgsl_release_resources(info);
1866
1867 if (info->port.tty)
1868 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1869
1870 info->port.flags &= ~ASYNC_INITIALIZED;
1871
1872}
1873
1874static void mgsl_program_hw(struct mgsl_struct *info)
1875{
1876 unsigned long flags;
1877
1878 spin_lock_irqsave(&info->irq_spinlock,flags);
1879
1880 usc_stop_receiver(info);
1881 usc_stop_transmitter(info);
1882 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1883
1884 if (info->params.mode == MGSL_MODE_HDLC ||
1885 info->params.mode == MGSL_MODE_RAW ||
1886 info->netcount)
1887 usc_set_sync_mode(info);
1888 else
1889 usc_set_async_mode(info);
1890
1891 usc_set_serial_signals(info);
1892
1893 info->dcd_chkcount = 0;
1894 info->cts_chkcount = 0;
1895 info->ri_chkcount = 0;
1896 info->dsr_chkcount = 0;
1897
1898 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1899 usc_EnableInterrupts(info, IO_PIN);
1900 usc_get_serial_signals(info);
1901
1902 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1903 usc_start_receiver(info);
1904
1905 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1906}
1907
1908
1909
1910static void mgsl_change_params(struct mgsl_struct *info)
1911{
1912 unsigned cflag;
1913 int bits_per_char;
1914
1915 if (!info->port.tty || !info->port.tty->termios)
1916 return;
1917
1918 if (debug_level >= DEBUG_LEVEL_INFO)
1919 printk("%s(%d):mgsl_change_params(%s)\n",
1920 __FILE__,__LINE__, info->device_name );
1921
1922 cflag = info->port.tty->termios->c_cflag;
1923
1924
1925
1926 if (cflag & CBAUD)
1927 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1928 else
1929 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1930
1931
1932
1933 switch (cflag & CSIZE) {
1934 case CS5: info->params.data_bits = 5; break;
1935 case CS6: info->params.data_bits = 6; break;
1936 case CS7: info->params.data_bits = 7; break;
1937 case CS8: info->params.data_bits = 8; break;
1938
1939 default: info->params.data_bits = 7; break;
1940 }
1941
1942 if (cflag & CSTOPB)
1943 info->params.stop_bits = 2;
1944 else
1945 info->params.stop_bits = 1;
1946
1947 info->params.parity = ASYNC_PARITY_NONE;
1948 if (cflag & PARENB) {
1949 if (cflag & PARODD)
1950 info->params.parity = ASYNC_PARITY_ODD;
1951 else
1952 info->params.parity = ASYNC_PARITY_EVEN;
1953#ifdef CMSPAR
1954 if (cflag & CMSPAR)
1955 info->params.parity = ASYNC_PARITY_SPACE;
1956#endif
1957 }
1958
1959
1960
1961
1962 bits_per_char = info->params.data_bits +
1963 info->params.stop_bits + 1;
1964
1965
1966
1967
1968
1969 if (info->params.data_rate <= 460800)
1970 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1971
1972 if ( info->params.data_rate ) {
1973 info->timeout = (32*HZ*bits_per_char) /
1974 info->params.data_rate;
1975 }
1976 info->timeout += HZ/50;
1977
1978 if (cflag & CRTSCTS)
1979 info->port.flags |= ASYNC_CTS_FLOW;
1980 else
1981 info->port.flags &= ~ASYNC_CTS_FLOW;
1982
1983 if (cflag & CLOCAL)
1984 info->port.flags &= ~ASYNC_CHECK_CD;
1985 else
1986 info->port.flags |= ASYNC_CHECK_CD;
1987
1988
1989
1990 info->read_status_mask = RXSTATUS_OVERRUN;
1991 if (I_INPCK(info->port.tty))
1992 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1993 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1994 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1995
1996 if (I_IGNPAR(info->port.tty))
1997 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1998 if (I_IGNBRK(info->port.tty)) {
1999 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2000
2001
2002
2003 if (I_IGNPAR(info->port.tty))
2004 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2005 }
2006
2007 mgsl_program_hw(info);
2008
2009}
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2021{
2022 struct mgsl_struct *info = tty->driver_data;
2023 unsigned long flags;
2024 int ret = 0;
2025
2026 if (debug_level >= DEBUG_LEVEL_INFO) {
2027 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2028 __FILE__, __LINE__, ch, info->device_name);
2029 }
2030
2031 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2032 return 0;
2033
2034 if (!tty || !info->xmit_buf)
2035 return 0;
2036
2037 spin_lock_irqsave(&info->irq_spinlock, flags);
2038
2039 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2040 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2041 info->xmit_buf[info->xmit_head++] = ch;
2042 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2043 info->xmit_cnt++;
2044 ret = 1;
2045 }
2046 }
2047 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2048 return ret;
2049
2050}
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060static void mgsl_flush_chars(struct tty_struct *tty)
2061{
2062 struct mgsl_struct *info = tty->driver_data;
2063 unsigned long flags;
2064
2065 if ( debug_level >= DEBUG_LEVEL_INFO )
2066 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2067 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2068
2069 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2070 return;
2071
2072 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2073 !info->xmit_buf)
2074 return;
2075
2076 if ( debug_level >= DEBUG_LEVEL_INFO )
2077 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2078 __FILE__,__LINE__,info->device_name );
2079
2080 spin_lock_irqsave(&info->irq_spinlock,flags);
2081
2082 if (!info->tx_active) {
2083 if ( (info->params.mode == MGSL_MODE_HDLC ||
2084 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2085
2086
2087
2088 mgsl_load_tx_dma_buffer(info,
2089 info->xmit_buf,info->xmit_cnt);
2090 }
2091 usc_start_transmitter(info);
2092 }
2093
2094 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2095
2096}
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110static int mgsl_write(struct tty_struct * tty,
2111 const unsigned char *buf, int count)
2112{
2113 int c, ret = 0;
2114 struct mgsl_struct *info = tty->driver_data;
2115 unsigned long flags;
2116
2117 if ( debug_level >= DEBUG_LEVEL_INFO )
2118 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2119 __FILE__,__LINE__,info->device_name,count);
2120
2121 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2122 goto cleanup;
2123
2124 if (!tty || !info->xmit_buf)
2125 goto cleanup;
2126
2127 if ( info->params.mode == MGSL_MODE_HDLC ||
2128 info->params.mode == MGSL_MODE_RAW ) {
2129
2130
2131 if (info->tx_active) {
2132
2133 if ( info->params.mode == MGSL_MODE_HDLC ) {
2134 ret = 0;
2135 goto cleanup;
2136 }
2137
2138
2139
2140
2141
2142 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2143
2144 ret = 0;
2145 goto cleanup;
2146 }
2147
2148
2149 ret = count;
2150 save_tx_buffer_request(info,buf,count);
2151
2152
2153
2154
2155 spin_lock_irqsave(&info->irq_spinlock,flags);
2156 load_next_tx_holding_buffer(info);
2157 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2158 goto cleanup;
2159 }
2160
2161
2162
2163
2164
2165 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2166 !usc_loopmode_active(info) )
2167 {
2168 ret = 0;
2169 goto cleanup;
2170 }
2171
2172 if ( info->xmit_cnt ) {
2173
2174
2175 ret = 0;
2176
2177
2178
2179 mgsl_load_tx_dma_buffer(info,
2180 info->xmit_buf,info->xmit_cnt);
2181 if ( debug_level >= DEBUG_LEVEL_INFO )
2182 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2183 __FILE__,__LINE__,info->device_name);
2184 } else {
2185 if ( debug_level >= DEBUG_LEVEL_INFO )
2186 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2187 __FILE__,__LINE__,info->device_name);
2188 ret = count;
2189 info->xmit_cnt = count;
2190 mgsl_load_tx_dma_buffer(info,buf,count);
2191 }
2192 } else {
2193 while (1) {
2194 spin_lock_irqsave(&info->irq_spinlock,flags);
2195 c = min_t(int, count,
2196 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2197 SERIAL_XMIT_SIZE - info->xmit_head));
2198 if (c <= 0) {
2199 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2200 break;
2201 }
2202 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2203 info->xmit_head = ((info->xmit_head + c) &
2204 (SERIAL_XMIT_SIZE-1));
2205 info->xmit_cnt += c;
2206 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2207 buf += c;
2208 count -= c;
2209 ret += c;
2210 }
2211 }
2212
2213 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2214 spin_lock_irqsave(&info->irq_spinlock,flags);
2215 if (!info->tx_active)
2216 usc_start_transmitter(info);
2217 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2218 }
2219cleanup:
2220 if ( debug_level >= DEBUG_LEVEL_INFO )
2221 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2222 __FILE__,__LINE__,info->device_name,ret);
2223
2224 return ret;
2225
2226}
2227
2228
2229
2230
2231
2232
2233
2234
2235static int mgsl_write_room(struct tty_struct *tty)
2236{
2237 struct mgsl_struct *info = tty->driver_data;
2238 int ret;
2239
2240 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2241 return 0;
2242 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2243 if (ret < 0)
2244 ret = 0;
2245
2246 if (debug_level >= DEBUG_LEVEL_INFO)
2247 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2248 __FILE__,__LINE__, info->device_name,ret );
2249
2250 if ( info->params.mode == MGSL_MODE_HDLC ||
2251 info->params.mode == MGSL_MODE_RAW ) {
2252
2253 if ( info->tx_active )
2254 return 0;
2255 else
2256 return HDLC_MAX_FRAME_SIZE;
2257 }
2258
2259 return ret;
2260
2261}
2262
2263
2264
2265
2266
2267
2268
2269
2270static int mgsl_chars_in_buffer(struct tty_struct *tty)
2271{
2272 struct mgsl_struct *info = tty->driver_data;
2273
2274 if (debug_level >= DEBUG_LEVEL_INFO)
2275 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2276 __FILE__,__LINE__, info->device_name );
2277
2278 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2279 return 0;
2280
2281 if (debug_level >= DEBUG_LEVEL_INFO)
2282 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2283 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2284
2285 if ( info->params.mode == MGSL_MODE_HDLC ||
2286 info->params.mode == MGSL_MODE_RAW ) {
2287
2288 if ( info->tx_active )
2289 return info->max_frame_size;
2290 else
2291 return 0;
2292 }
2293
2294 return info->xmit_cnt;
2295}
2296
2297
2298
2299
2300
2301
2302
2303
2304static void mgsl_flush_buffer(struct tty_struct *tty)
2305{
2306 struct mgsl_struct *info = tty->driver_data;
2307 unsigned long flags;
2308
2309 if (debug_level >= DEBUG_LEVEL_INFO)
2310 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2311 __FILE__,__LINE__, info->device_name );
2312
2313 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2314 return;
2315
2316 spin_lock_irqsave(&info->irq_spinlock,flags);
2317 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2318 del_timer(&info->tx_timer);
2319 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2320
2321 tty_wakeup(tty);
2322}
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2333{
2334 struct mgsl_struct *info = tty->driver_data;
2335 unsigned long flags;
2336
2337 if (debug_level >= DEBUG_LEVEL_INFO)
2338 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2339 __FILE__,__LINE__, info->device_name, ch );
2340
2341 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2342 return;
2343
2344 info->x_char = ch;
2345 if (ch) {
2346
2347 spin_lock_irqsave(&info->irq_spinlock,flags);
2348 if (!info->tx_enabled)
2349 usc_start_transmitter(info);
2350 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2351 }
2352}
2353
2354
2355
2356
2357
2358
2359
2360
2361static void mgsl_throttle(struct tty_struct * tty)
2362{
2363 struct mgsl_struct *info = tty->driver_data;
2364 unsigned long flags;
2365
2366 if (debug_level >= DEBUG_LEVEL_INFO)
2367 printk("%s(%d):mgsl_throttle(%s) entry\n",
2368 __FILE__,__LINE__, info->device_name );
2369
2370 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2371 return;
2372
2373 if (I_IXOFF(tty))
2374 mgsl_send_xchar(tty, STOP_CHAR(tty));
2375
2376 if (tty->termios->c_cflag & CRTSCTS) {
2377 spin_lock_irqsave(&info->irq_spinlock,flags);
2378 info->serial_signals &= ~SerialSignal_RTS;
2379 usc_set_serial_signals(info);
2380 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2381 }
2382}
2383
2384
2385
2386
2387
2388
2389
2390
2391static void mgsl_unthrottle(struct tty_struct * tty)
2392{
2393 struct mgsl_struct *info = tty->driver_data;
2394 unsigned long flags;
2395
2396 if (debug_level >= DEBUG_LEVEL_INFO)
2397 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2398 __FILE__,__LINE__, info->device_name );
2399
2400 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2401 return;
2402
2403 if (I_IXOFF(tty)) {
2404 if (info->x_char)
2405 info->x_char = 0;
2406 else
2407 mgsl_send_xchar(tty, START_CHAR(tty));
2408 }
2409
2410 if (tty->termios->c_cflag & CRTSCTS) {
2411 spin_lock_irqsave(&info->irq_spinlock,flags);
2412 info->serial_signals |= SerialSignal_RTS;
2413 usc_set_serial_signals(info);
2414 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2415 }
2416
2417}
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2429{
2430 int err;
2431
2432 if (debug_level >= DEBUG_LEVEL_INFO)
2433 printk("%s(%d):mgsl_get_params(%s)\n",
2434 __FILE__,__LINE__, info->device_name);
2435
2436 if (!user_icount) {
2437 memset(&info->icount, 0, sizeof(info->icount));
2438 } else {
2439 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2440 if (err)
2441 return -EFAULT;
2442 }
2443
2444 return 0;
2445
2446}
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2458{
2459 int err;
2460 if (debug_level >= DEBUG_LEVEL_INFO)
2461 printk("%s(%d):mgsl_get_params(%s)\n",
2462 __FILE__,__LINE__, info->device_name);
2463
2464 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2465 if (err) {
2466 if ( debug_level >= DEBUG_LEVEL_INFO )
2467 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2468 __FILE__,__LINE__,info->device_name);
2469 return -EFAULT;
2470 }
2471
2472 return 0;
2473
2474}
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2488{
2489 unsigned long flags;
2490 MGSL_PARAMS tmp_params;
2491 int err;
2492
2493 if (debug_level >= DEBUG_LEVEL_INFO)
2494 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2495 info->device_name );
2496 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2497 if (err) {
2498 if ( debug_level >= DEBUG_LEVEL_INFO )
2499 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2500 __FILE__,__LINE__,info->device_name);
2501 return -EFAULT;
2502 }
2503
2504 spin_lock_irqsave(&info->irq_spinlock,flags);
2505 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2506 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2507
2508 mgsl_change_params(info);
2509
2510 return 0;
2511
2512}
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2524{
2525 int err;
2526
2527 if (debug_level >= DEBUG_LEVEL_INFO)
2528 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2529 __FILE__,__LINE__, info->device_name, info->idle_mode);
2530
2531 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2532 if (err) {
2533 if ( debug_level >= DEBUG_LEVEL_INFO )
2534 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2535 __FILE__,__LINE__,info->device_name);
2536 return -EFAULT;
2537 }
2538
2539 return 0;
2540
2541}
2542
2543
2544
2545
2546
2547
2548
2549
2550static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2551{
2552 unsigned long flags;
2553
2554 if (debug_level >= DEBUG_LEVEL_INFO)
2555 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2556 info->device_name, idle_mode );
2557
2558 spin_lock_irqsave(&info->irq_spinlock,flags);
2559 info->idle_mode = idle_mode;
2560 usc_set_txidle( info );
2561 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2562 return 0;
2563
2564}
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577static int mgsl_txenable(struct mgsl_struct * info, int enable)
2578{
2579 unsigned long flags;
2580
2581 if (debug_level >= DEBUG_LEVEL_INFO)
2582 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2583 info->device_name, enable);
2584
2585 spin_lock_irqsave(&info->irq_spinlock,flags);
2586 if ( enable ) {
2587 if ( !info->tx_enabled ) {
2588
2589 usc_start_transmitter(info);
2590
2591
2592
2593
2594
2595
2596
2597 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2598 usc_loopmode_insert_request( info );
2599 }
2600 } else {
2601 if ( info->tx_enabled )
2602 usc_stop_transmitter(info);
2603 }
2604 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2605 return 0;
2606
2607}
2608
2609
2610
2611
2612
2613
2614static int mgsl_txabort(struct mgsl_struct * info)
2615{
2616 unsigned long flags;
2617
2618 if (debug_level >= DEBUG_LEVEL_INFO)
2619 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2620 info->device_name);
2621
2622 spin_lock_irqsave(&info->irq_spinlock,flags);
2623 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2624 {
2625 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2626 usc_loopmode_cancel_transmit( info );
2627 else
2628 usc_TCmd(info,TCmd_SendAbort);
2629 }
2630 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2631 return 0;
2632
2633}
2634
2635
2636
2637
2638
2639
2640
2641static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2642{
2643 unsigned long flags;
2644
2645 if (debug_level >= DEBUG_LEVEL_INFO)
2646 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2647 info->device_name, enable);
2648
2649 spin_lock_irqsave(&info->irq_spinlock,flags);
2650 if ( enable ) {
2651 if ( !info->rx_enabled )
2652 usc_start_receiver(info);
2653 } else {
2654 if ( info->rx_enabled )
2655 usc_stop_receiver(info);
2656 }
2657 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2658 return 0;
2659
2660}
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2671{
2672 unsigned long flags;
2673 int s;
2674 int rc=0;
2675 struct mgsl_icount cprev, cnow;
2676 int events;
2677 int mask;
2678 struct _input_signal_events oldsigs, newsigs;
2679 DECLARE_WAITQUEUE(wait, current);
2680
2681 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2682 if (rc) {
2683 return -EFAULT;
2684 }
2685
2686 if (debug_level >= DEBUG_LEVEL_INFO)
2687 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2688 info->device_name, mask);
2689
2690 spin_lock_irqsave(&info->irq_spinlock,flags);
2691
2692
2693 usc_get_serial_signals(info);
2694 s = info->serial_signals;
2695 events = mask &
2696 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2697 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2698 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2699 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2700 if (events) {
2701 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2702 goto exit;
2703 }
2704
2705
2706 cprev = info->icount;
2707 oldsigs = info->input_signal_events;
2708
2709
2710 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2711 u16 oldreg = usc_InReg(info,RICR);
2712 u16 newreg = oldreg +
2713 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2714 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2715 if (oldreg != newreg)
2716 usc_OutReg(info, RICR, newreg);
2717 }
2718
2719 set_current_state(TASK_INTERRUPTIBLE);
2720 add_wait_queue(&info->event_wait_q, &wait);
2721
2722 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2723
2724
2725 for(;;) {
2726 schedule();
2727 if (signal_pending(current)) {
2728 rc = -ERESTARTSYS;
2729 break;
2730 }
2731
2732
2733 spin_lock_irqsave(&info->irq_spinlock,flags);
2734 cnow = info->icount;
2735 newsigs = info->input_signal_events;
2736 set_current_state(TASK_INTERRUPTIBLE);
2737 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2738
2739
2740 if (newsigs.dsr_up == oldsigs.dsr_up &&
2741 newsigs.dsr_down == oldsigs.dsr_down &&
2742 newsigs.dcd_up == oldsigs.dcd_up &&
2743 newsigs.dcd_down == oldsigs.dcd_down &&
2744 newsigs.cts_up == oldsigs.cts_up &&
2745 newsigs.cts_down == oldsigs.cts_down &&
2746 newsigs.ri_up == oldsigs.ri_up &&
2747 newsigs.ri_down == oldsigs.ri_down &&
2748 cnow.exithunt == cprev.exithunt &&
2749 cnow.rxidle == cprev.rxidle) {
2750 rc = -EIO;
2751 break;
2752 }
2753
2754 events = mask &
2755 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2756 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2757 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2758 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2759 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2760 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2761 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2762 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2763 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2764 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2765 if (events)
2766 break;
2767
2768 cprev = cnow;
2769 oldsigs = newsigs;
2770 }
2771
2772 remove_wait_queue(&info->event_wait_q, &wait);
2773 set_current_state(TASK_RUNNING);
2774
2775 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2776 spin_lock_irqsave(&info->irq_spinlock,flags);
2777 if (!waitqueue_active(&info->event_wait_q)) {
2778
2779 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2780 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2781 }
2782 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2783 }
2784exit:
2785 if ( rc == 0 )
2786 PUT_USER(rc, events, mask_ptr);
2787
2788 return rc;
2789
2790}
2791
2792static int modem_input_wait(struct mgsl_struct *info,int arg)
2793{
2794 unsigned long flags;
2795 int rc;
2796 struct mgsl_icount cprev, cnow;
2797 DECLARE_WAITQUEUE(wait, current);
2798
2799
2800 spin_lock_irqsave(&info->irq_spinlock,flags);
2801 cprev = info->icount;
2802 add_wait_queue(&info->status_event_wait_q, &wait);
2803 set_current_state(TASK_INTERRUPTIBLE);
2804 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2805
2806 for(;;) {
2807 schedule();
2808 if (signal_pending(current)) {
2809 rc = -ERESTARTSYS;
2810 break;
2811 }
2812
2813
2814 spin_lock_irqsave(&info->irq_spinlock,flags);
2815 cnow = info->icount;
2816 set_current_state(TASK_INTERRUPTIBLE);
2817 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2818
2819
2820 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2821 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2822 rc = -EIO;
2823 break;
2824 }
2825
2826
2827 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2828 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2829 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2830 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2831 rc = 0;
2832 break;
2833 }
2834
2835 cprev = cnow;
2836 }
2837 remove_wait_queue(&info->status_event_wait_q, &wait);
2838 set_current_state(TASK_RUNNING);
2839 return rc;
2840}
2841
2842
2843
2844static int tiocmget(struct tty_struct *tty, struct file *file)
2845{
2846 struct mgsl_struct *info = tty->driver_data;
2847 unsigned int result;
2848 unsigned long flags;
2849
2850 spin_lock_irqsave(&info->irq_spinlock,flags);
2851 usc_get_serial_signals(info);
2852 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2853
2854 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2855 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2856 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2857 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2858 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2859 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2860
2861 if (debug_level >= DEBUG_LEVEL_INFO)
2862 printk("%s(%d):%s tiocmget() value=%08X\n",
2863 __FILE__,__LINE__, info->device_name, result );
2864 return result;
2865}
2866
2867
2868
2869static int tiocmset(struct tty_struct *tty, struct file *file,
2870 unsigned int set, unsigned int clear)
2871{
2872 struct mgsl_struct *info = tty->driver_data;
2873 unsigned long flags;
2874
2875 if (debug_level >= DEBUG_LEVEL_INFO)
2876 printk("%s(%d):%s tiocmset(%x,%x)\n",
2877 __FILE__,__LINE__,info->device_name, set, clear);
2878
2879 if (set & TIOCM_RTS)
2880 info->serial_signals |= SerialSignal_RTS;
2881 if (set & TIOCM_DTR)
2882 info->serial_signals |= SerialSignal_DTR;
2883 if (clear & TIOCM_RTS)
2884 info->serial_signals &= ~SerialSignal_RTS;
2885 if (clear & TIOCM_DTR)
2886 info->serial_signals &= ~SerialSignal_DTR;
2887
2888 spin_lock_irqsave(&info->irq_spinlock,flags);
2889 usc_set_serial_signals(info);
2890 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2891
2892 return 0;
2893}
2894
2895
2896
2897
2898
2899
2900
2901static int mgsl_break(struct tty_struct *tty, int break_state)
2902{
2903 struct mgsl_struct * info = tty->driver_data;
2904 unsigned long flags;
2905
2906 if (debug_level >= DEBUG_LEVEL_INFO)
2907 printk("%s(%d):mgsl_break(%s,%d)\n",
2908 __FILE__,__LINE__, info->device_name, break_state);
2909
2910 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2911 return -EINVAL;
2912
2913 spin_lock_irqsave(&info->irq_spinlock,flags);
2914 if (break_state == -1)
2915 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2916 else
2917 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2918 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2919 return 0;
2920
2921}
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2935 unsigned int cmd, unsigned long arg)
2936{
2937 struct mgsl_struct * info = tty->driver_data;
2938 int ret;
2939
2940 if (debug_level >= DEBUG_LEVEL_INFO)
2941 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2942 info->device_name, cmd );
2943
2944 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2945 return -ENODEV;
2946
2947 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2948 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2949 if (tty->flags & (1 << TTY_IO_ERROR))
2950 return -EIO;
2951 }
2952
2953 lock_kernel();
2954 ret = mgsl_ioctl_common(info, cmd, arg);
2955 unlock_kernel();
2956 return ret;
2957}
2958
2959static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2960{
2961 int error;
2962 struct mgsl_icount cnow;
2963 void __user *argp = (void __user *)arg;
2964 struct serial_icounter_struct __user *p_cuser;
2965 unsigned long flags;
2966
2967 switch (cmd) {
2968 case MGSL_IOCGPARAMS:
2969 return mgsl_get_params(info, argp);
2970 case MGSL_IOCSPARAMS:
2971 return mgsl_set_params(info, argp);
2972 case MGSL_IOCGTXIDLE:
2973 return mgsl_get_txidle(info, argp);
2974 case MGSL_IOCSTXIDLE:
2975 return mgsl_set_txidle(info,(int)arg);
2976 case MGSL_IOCTXENABLE:
2977 return mgsl_txenable(info,(int)arg);
2978 case MGSL_IOCRXENABLE:
2979 return mgsl_rxenable(info,(int)arg);
2980 case MGSL_IOCTXABORT:
2981 return mgsl_txabort(info);
2982 case MGSL_IOCGSTATS:
2983 return mgsl_get_stats(info, argp);
2984 case MGSL_IOCWAITEVENT:
2985 return mgsl_wait_event(info, argp);
2986 case MGSL_IOCLOOPTXDONE:
2987 return mgsl_loopmode_send_done(info);
2988
2989
2990
2991 case TIOCMIWAIT:
2992 return modem_input_wait(info,(int)arg);
2993
2994
2995
2996
2997
2998
2999
3000 case TIOCGICOUNT:
3001 spin_lock_irqsave(&info->irq_spinlock,flags);
3002 cnow = info->icount;
3003 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3004 p_cuser = argp;
3005 PUT_USER(error,cnow.cts, &p_cuser->cts);
3006 if (error) return error;
3007 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3008 if (error) return error;
3009 PUT_USER(error,cnow.rng, &p_cuser->rng);
3010 if (error) return error;
3011 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3012 if (error) return error;
3013 PUT_USER(error,cnow.rx, &p_cuser->rx);
3014 if (error) return error;
3015 PUT_USER(error,cnow.tx, &p_cuser->tx);
3016 if (error) return error;
3017 PUT_USER(error,cnow.frame, &p_cuser->frame);
3018 if (error) return error;
3019 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3020 if (error) return error;
3021 PUT_USER(error,cnow.parity, &p_cuser->parity);
3022 if (error) return error;
3023 PUT_USER(error,cnow.brk, &p_cuser->brk);
3024 if (error) return error;
3025 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3026 if (error) return error;
3027 return 0;
3028 default:
3029 return -ENOIOCTLCMD;
3030 }
3031 return 0;
3032}
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3046{
3047 struct mgsl_struct *info = tty->driver_data;
3048 unsigned long flags;
3049
3050 if (debug_level >= DEBUG_LEVEL_INFO)
3051 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3052 tty->driver->name );
3053
3054 mgsl_change_params(info);
3055
3056
3057 if (old_termios->c_cflag & CBAUD &&
3058 !(tty->termios->c_cflag & CBAUD)) {
3059 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3060 spin_lock_irqsave(&info->irq_spinlock,flags);
3061 usc_set_serial_signals(info);
3062 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3063 }
3064
3065
3066 if (!(old_termios->c_cflag & CBAUD) &&
3067 tty->termios->c_cflag & CBAUD) {
3068 info->serial_signals |= SerialSignal_DTR;
3069 if (!(tty->termios->c_cflag & CRTSCTS) ||
3070 !test_bit(TTY_THROTTLED, &tty->flags)) {
3071 info->serial_signals |= SerialSignal_RTS;
3072 }
3073 spin_lock_irqsave(&info->irq_spinlock,flags);
3074 usc_set_serial_signals(info);
3075 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3076 }
3077
3078
3079 if (old_termios->c_cflag & CRTSCTS &&
3080 !(tty->termios->c_cflag & CRTSCTS)) {
3081 tty->hw_stopped = 0;
3082 mgsl_start(tty);
3083 }
3084
3085}
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099static void mgsl_close(struct tty_struct *tty, struct file * filp)
3100{
3101 struct mgsl_struct * info = tty->driver_data;
3102
3103 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3104 return;
3105
3106 if (debug_level >= DEBUG_LEVEL_INFO)
3107 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3108 __FILE__,__LINE__, info->device_name, info->port.count);
3109
3110 if (tty_port_close_start(&info->port, tty, filp) == 0)
3111 goto cleanup;
3112
3113 if (info->port.flags & ASYNC_INITIALIZED)
3114 mgsl_wait_until_sent(tty, info->timeout);
3115 mgsl_flush_buffer(tty);
3116 tty_ldisc_flush(tty);
3117 shutdown(info);
3118
3119 tty_port_close_end(&info->port, tty);
3120 info->port.tty = NULL;
3121cleanup:
3122 if (debug_level >= DEBUG_LEVEL_INFO)
3123 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3124 tty->driver->name, info->port.count);
3125
3126}
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3140{
3141 struct mgsl_struct * info = tty->driver_data;
3142 unsigned long orig_jiffies, char_time;
3143
3144 if (!info )
3145 return;
3146
3147 if (debug_level >= DEBUG_LEVEL_INFO)
3148 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3149 __FILE__,__LINE__, info->device_name );
3150
3151 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3152 return;
3153
3154 if (!(info->port.flags & ASYNC_INITIALIZED))
3155 goto exit;
3156
3157 orig_jiffies = jiffies;
3158
3159
3160
3161
3162
3163
3164
3165 lock_kernel();
3166 if ( info->params.data_rate ) {
3167 char_time = info->timeout/(32 * 5);
3168 if (!char_time)
3169 char_time++;
3170 } else
3171 char_time = 1;
3172
3173 if (timeout)
3174 char_time = min_t(unsigned long, char_time, timeout);
3175
3176 if ( info->params.mode == MGSL_MODE_HDLC ||
3177 info->params.mode == MGSL_MODE_RAW ) {
3178 while (info->tx_active) {
3179 msleep_interruptible(jiffies_to_msecs(char_time));
3180 if (signal_pending(current))
3181 break;
3182 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3183 break;
3184 }
3185 } else {
3186 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3187 info->tx_enabled) {
3188 msleep_interruptible(jiffies_to_msecs(char_time));
3189 if (signal_pending(current))
3190 break;
3191 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3192 break;
3193 }
3194 }
3195 unlock_kernel();
3196
3197exit:
3198 if (debug_level >= DEBUG_LEVEL_INFO)
3199 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3200 __FILE__,__LINE__, info->device_name );
3201
3202}
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212static void mgsl_hangup(struct tty_struct *tty)
3213{
3214 struct mgsl_struct * info = tty->driver_data;
3215
3216 if (debug_level >= DEBUG_LEVEL_INFO)
3217 printk("%s(%d):mgsl_hangup(%s)\n",
3218 __FILE__,__LINE__, info->device_name );
3219
3220 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3221 return;
3222
3223 mgsl_flush_buffer(tty);
3224 shutdown(info);
3225
3226 info->port.count = 0;
3227 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3228 info->port.tty = NULL;
3229
3230 wake_up_interruptible(&info->port.open_wait);
3231
3232}
3233
3234
3235
3236
3237
3238
3239
3240static int carrier_raised(struct tty_port *port)
3241{
3242 unsigned long flags;
3243 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3244
3245 spin_lock_irqsave(&info->irq_spinlock, flags);
3246 usc_get_serial_signals(info);
3247 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3248 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3249}
3250
3251static void dtr_rts(struct tty_port *port, int on)
3252{
3253 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3254 unsigned long flags;
3255
3256 spin_lock_irqsave(&info->irq_spinlock,flags);
3257 if (on)
3258 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3259 else
3260 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3261 usc_set_serial_signals(info);
3262 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3263}
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279static int block_til_ready(struct tty_struct *tty, struct file * filp,
3280 struct mgsl_struct *info)
3281{
3282 DECLARE_WAITQUEUE(wait, current);
3283 int retval;
3284 bool do_clocal = false;
3285 bool extra_count = false;
3286 unsigned long flags;
3287 int dcd;
3288 struct tty_port *port = &info->port;
3289
3290 if (debug_level >= DEBUG_LEVEL_INFO)
3291 printk("%s(%d):block_til_ready on %s\n",
3292 __FILE__,__LINE__, tty->driver->name );
3293
3294 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3295
3296 port->flags |= ASYNC_NORMAL_ACTIVE;
3297 return 0;
3298 }
3299
3300 if (tty->termios->c_cflag & CLOCAL)
3301 do_clocal = true;
3302
3303
3304
3305
3306
3307
3308
3309
3310 retval = 0;
3311 add_wait_queue(&port->open_wait, &wait);
3312
3313 if (debug_level >= DEBUG_LEVEL_INFO)
3314 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3315 __FILE__,__LINE__, tty->driver->name, port->count );
3316
3317 spin_lock_irqsave(&info->irq_spinlock, flags);
3318 if (!tty_hung_up_p(filp)) {
3319 extra_count = true;
3320 port->count--;
3321 }
3322 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3323 port->blocked_open++;
3324
3325 while (1) {
3326 if (tty->termios->c_cflag & CBAUD)
3327 tty_port_raise_dtr_rts(port);
3328
3329 set_current_state(TASK_INTERRUPTIBLE);
3330
3331 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3332 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3333 -EAGAIN : -ERESTARTSYS;
3334 break;
3335 }
3336
3337 dcd = tty_port_carrier_raised(&info->port);
3338
3339 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3340 break;
3341
3342 if (signal_pending(current)) {
3343 retval = -ERESTARTSYS;
3344 break;
3345 }
3346
3347 if (debug_level >= DEBUG_LEVEL_INFO)
3348 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3349 __FILE__,__LINE__, tty->driver->name, port->count );
3350
3351 schedule();
3352 }
3353
3354 set_current_state(TASK_RUNNING);
3355 remove_wait_queue(&port->open_wait, &wait);
3356
3357
3358 if (extra_count)
3359 port->count++;
3360 port->blocked_open--;
3361
3362 if (debug_level >= DEBUG_LEVEL_INFO)
3363 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3364 __FILE__,__LINE__, tty->driver->name, port->count );
3365
3366 if (!retval)
3367 port->flags |= ASYNC_NORMAL_ACTIVE;
3368
3369 return retval;
3370
3371}
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383static int mgsl_open(struct tty_struct *tty, struct file * filp)
3384{
3385 struct mgsl_struct *info;
3386 int retval, line;
3387 unsigned long flags;
3388
3389
3390 line = tty->index;
3391 if ((line < 0) || (line >= mgsl_device_count)) {
3392 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3393 __FILE__,__LINE__,line);
3394 return -ENODEV;
3395 }
3396
3397
3398 info = mgsl_device_list;
3399 while(info && info->line != line)
3400 info = info->next_device;
3401 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3402 return -ENODEV;
3403
3404 tty->driver_data = info;
3405 info->port.tty = tty;
3406
3407 if (debug_level >= DEBUG_LEVEL_INFO)
3408 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3409 __FILE__,__LINE__,tty->driver->name, info->port.count);
3410
3411
3412 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3413 if (info->port.flags & ASYNC_CLOSING)
3414 interruptible_sleep_on(&info->port.close_wait);
3415 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3416 -EAGAIN : -ERESTARTSYS);
3417 goto cleanup;
3418 }
3419
3420 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3421
3422 spin_lock_irqsave(&info->netlock, flags);
3423 if (info->netcount) {
3424 retval = -EBUSY;
3425 spin_unlock_irqrestore(&info->netlock, flags);
3426 goto cleanup;
3427 }
3428 info->port.count++;
3429 spin_unlock_irqrestore(&info->netlock, flags);
3430
3431 if (info->port.count == 1) {
3432
3433 retval = startup(info);
3434 if (retval < 0)
3435 goto cleanup;
3436 }
3437
3438 retval = block_til_ready(tty, filp, info);
3439 if (retval) {
3440 if (debug_level >= DEBUG_LEVEL_INFO)
3441 printk("%s(%d):block_til_ready(%s) returned %d\n",
3442 __FILE__,__LINE__, info->device_name, retval);
3443 goto cleanup;
3444 }
3445
3446 if (debug_level >= DEBUG_LEVEL_INFO)
3447 printk("%s(%d):mgsl_open(%s) success\n",
3448 __FILE__,__LINE__, info->device_name);
3449 retval = 0;
3450
3451cleanup:
3452 if (retval) {
3453 if (tty->count == 1)
3454 info->port.tty = NULL;
3455 if(info->port.count)
3456 info->port.count--;
3457 }
3458
3459 return retval;
3460
3461}
3462
3463
3464
3465
3466
3467static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3468{
3469 char stat_buf[30];
3470 unsigned long flags;
3471
3472 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3473 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3474 info->device_name, info->io_base, info->irq_level,
3475 info->phys_memory_base, info->phys_lcr_base);
3476 } else {
3477 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3478 info->device_name, info->io_base,
3479 info->irq_level, info->dma_level);
3480 }
3481
3482
3483 spin_lock_irqsave(&info->irq_spinlock,flags);
3484 usc_get_serial_signals(info);
3485 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3486
3487 stat_buf[0] = 0;
3488 stat_buf[1] = 0;
3489 if (info->serial_signals & SerialSignal_RTS)
3490 strcat(stat_buf, "|RTS");
3491 if (info->serial_signals & SerialSignal_CTS)
3492 strcat(stat_buf, "|CTS");
3493 if (info->serial_signals & SerialSignal_DTR)
3494 strcat(stat_buf, "|DTR");
3495 if (info->serial_signals & SerialSignal_DSR)
3496 strcat(stat_buf, "|DSR");
3497 if (info->serial_signals & SerialSignal_DCD)
3498 strcat(stat_buf, "|CD");
3499 if (info->serial_signals & SerialSignal_RI)
3500 strcat(stat_buf, "|RI");
3501
3502 if (info->params.mode == MGSL_MODE_HDLC ||
3503 info->params.mode == MGSL_MODE_RAW ) {
3504 seq_printf(m, " HDLC txok:%d rxok:%d",
3505 info->icount.txok, info->icount.rxok);
3506 if (info->icount.txunder)
3507 seq_printf(m, " txunder:%d", info->icount.txunder);
3508 if (info->icount.txabort)
3509 seq_printf(m, " txabort:%d", info->icount.txabort);
3510 if (info->icount.rxshort)
3511 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3512 if (info->icount.rxlong)
3513 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3514 if (info->icount.rxover)
3515 seq_printf(m, " rxover:%d", info->icount.rxover);
3516 if (info->icount.rxcrc)
3517 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3518 } else {
3519 seq_printf(m, " ASYNC tx:%d rx:%d",
3520 info->icount.tx, info->icount.rx);
3521 if (info->icount.frame)
3522 seq_printf(m, " fe:%d", info->icount.frame);
3523 if (info->icount.parity)
3524 seq_printf(m, " pe:%d", info->icount.parity);
3525 if (info->icount.brk)
3526 seq_printf(m, " brk:%d", info->icount.brk);
3527 if (info->icount.overrun)
3528 seq_printf(m, " oe:%d", info->icount.overrun);
3529 }
3530
3531
3532 seq_printf(m, " %s\n", stat_buf+1);
3533
3534 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3535 info->tx_active,info->bh_requested,info->bh_running,
3536 info->pending_bh);
3537
3538 spin_lock_irqsave(&info->irq_spinlock,flags);
3539 {
3540 u16 Tcsr = usc_InReg( info, TCSR );
3541 u16 Tdmr = usc_InDmaReg( info, TDMR );
3542 u16 Ticr = usc_InReg( info, TICR );
3543 u16 Rscr = usc_InReg( info, RCSR );
3544 u16 Rdmr = usc_InDmaReg( info, RDMR );
3545 u16 Ricr = usc_InReg( info, RICR );
3546 u16 Icr = usc_InReg( info, ICR );
3547 u16 Dccr = usc_InReg( info, DCCR );
3548 u16 Tmr = usc_InReg( info, TMR );
3549 u16 Tccr = usc_InReg( info, TCCR );
3550 u16 Ccar = inw( info->io_base + CCAR );
3551 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3552 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3553 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3554 }
3555 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3556}
3557
3558
3559static int mgsl_proc_show(struct seq_file *m, void *v)
3560{
3561 struct mgsl_struct *info;
3562
3563 seq_printf(m, "synclink driver:%s\n", driver_version);
3564
3565 info = mgsl_device_list;
3566 while( info ) {
3567 line_info(m, info);
3568 info = info->next_device;
3569 }
3570 return 0;
3571}
3572
3573static int mgsl_proc_open(struct inode *inode, struct file *file)
3574{
3575 return single_open(file, mgsl_proc_show, NULL);
3576}
3577
3578static const struct file_operations mgsl_proc_fops = {
3579 .owner = THIS_MODULE,
3580 .open = mgsl_proc_open,
3581 .read = seq_read,
3582 .llseek = seq_lseek,
3583 .release = single_release,
3584};
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3595{
3596 unsigned short BuffersPerFrame;
3597
3598 info->last_mem_alloc = 0;
3599
3600
3601
3602
3603
3604
3605 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3606 if ( info->max_frame_size % DMABUFFERSIZE )
3607 BuffersPerFrame++;
3608
3609 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3633 info->rx_buffer_count = 62 - info->tx_buffer_count;
3634 } else {
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3646 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3647
3648
3649
3650
3651
3652
3653 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3654 info->rx_buffer_count = 62 - info->tx_buffer_count;
3655
3656 }
3657
3658 if ( debug_level >= DEBUG_LEVEL_INFO )
3659 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3660 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3661
3662 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3663 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3664 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3665 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3666 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3667 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3668 return -ENOMEM;
3669 }
3670
3671 mgsl_reset_rx_dma_buffers( info );
3672 mgsl_reset_tx_dma_buffers( info );
3673
3674 return 0;
3675
3676}
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3702{
3703 unsigned int i;
3704
3705 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3706
3707 info->buffer_list = info->memory_base + info->last_mem_alloc;
3708 info->buffer_list_phys = info->last_mem_alloc;
3709 info->last_mem_alloc += BUFFERLISTSIZE;
3710 } else {
3711
3712
3713
3714
3715
3716
3717 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3718 if (info->buffer_list == NULL)
3719 return -ENOMEM;
3720 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3721 }
3722
3723
3724
3725 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3726
3727
3728
3729
3730 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3731 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3732 info->tx_buffer_list += info->rx_buffer_count;
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3744
3745 info->rx_buffer_list[i].phys_entry =
3746 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3747
3748
3749
3750
3751 info->rx_buffer_list[i].link = info->buffer_list_phys;
3752
3753 if ( i < info->rx_buffer_count - 1 )
3754 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3755 }
3756
3757 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3758
3759 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3760 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3761
3762
3763
3764
3765 info->tx_buffer_list[i].link = info->buffer_list_phys +
3766 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3767
3768 if ( i < info->tx_buffer_count - 1 )
3769 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3770 }
3771
3772 return 0;
3773
3774}
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3786{
3787 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3788 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3789
3790 info->buffer_list = NULL;
3791 info->rx_buffer_list = NULL;
3792 info->tx_buffer_list = NULL;
3793
3794}
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3813{
3814 int i;
3815 u32 phys_addr;
3816
3817
3818
3819 for ( i = 0; i < Buffercount; i++ ) {
3820 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3821
3822 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3823 phys_addr = info->last_mem_alloc;
3824 info->last_mem_alloc += DMABUFFERSIZE;
3825 } else {
3826
3827 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3828 if (BufferList[i].virt_addr == NULL)
3829 return -ENOMEM;
3830 phys_addr = (u32)(BufferList[i].dma_addr);
3831 }
3832 BufferList[i].phys_addr = phys_addr;
3833 }
3834
3835 return 0;
3836
3837}
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3854{
3855 int i;
3856
3857 if ( BufferList ) {
3858 for ( i = 0 ; i < Buffercount ; i++ ) {
3859 if ( BufferList[i].virt_addr ) {
3860 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3861 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3862 BufferList[i].virt_addr = NULL;
3863 }
3864 }
3865 }
3866
3867}
3868
3869
3870
3871
3872
3873
3874
3875
3876static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3877{
3878 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3879 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3880 mgsl_free_buffer_list_memory( info );
3881
3882}
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3898{
3899 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3900 if ( info->intermediate_rxbuffer == NULL )
3901 return -ENOMEM;
3902
3903 return 0;
3904
3905}
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3918{
3919 kfree(info->intermediate_rxbuffer);
3920 info->intermediate_rxbuffer = NULL;
3921
3922}
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3938{
3939 int i;
3940
3941 if ( debug_level >= DEBUG_LEVEL_INFO )
3942 printk("%s %s(%d) allocating %d tx holding buffers\n",
3943 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3944
3945 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3946
3947 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3948 info->tx_holding_buffers[i].buffer =
3949 kmalloc(info->max_frame_size, GFP_KERNEL);
3950 if (info->tx_holding_buffers[i].buffer == NULL) {
3951 for (--i; i >= 0; i--) {
3952 kfree(info->tx_holding_buffers[i].buffer);
3953 info->tx_holding_buffers[i].buffer = NULL;
3954 }
3955 return -ENOMEM;
3956 }
3957 }
3958
3959 return 0;
3960
3961}
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3974{
3975 int i;
3976
3977 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3978 kfree(info->tx_holding_buffers[i].buffer);
3979 info->tx_holding_buffers[i].buffer = NULL;
3980 }
3981
3982 info->get_tx_holding_index = 0;
3983 info->put_tx_holding_index = 0;
3984 info->tx_holding_count = 0;
3985
3986}
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4004{
4005 bool ret = false;
4006
4007 if ( info->tx_holding_count ) {
4008
4009
4010
4011 struct tx_holding_buffer *ptx =
4012 &info->tx_holding_buffers[info->get_tx_holding_index];
4013 int num_free = num_free_tx_dma_buffers(info);
4014 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4015 if ( ptx->buffer_size % DMABUFFERSIZE )
4016 ++num_needed;
4017
4018 if (num_needed <= num_free) {
4019 info->xmit_cnt = ptx->buffer_size;
4020 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4021
4022 --info->tx_holding_count;
4023 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4024 info->get_tx_holding_index=0;
4025
4026
4027 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4028
4029 ret = true;
4030 }
4031 }
4032
4033 return ret;
4034}
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4050{
4051 struct tx_holding_buffer *ptx;
4052
4053 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4054 return 0;
4055 }
4056
4057 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4058 ptx->buffer_size = BufferSize;
4059 memcpy( ptx->buffer, Buffer, BufferSize);
4060
4061 ++info->tx_holding_count;
4062 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4063 info->put_tx_holding_index=0;
4064
4065 return 1;
4066}
4067
4068static int mgsl_claim_resources(struct mgsl_struct *info)
4069{
4070 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4071 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4072 __FILE__,__LINE__,info->device_name, info->io_base);
4073 return -ENODEV;
4074 }
4075 info->io_addr_requested = true;
4076
4077 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4078 info->device_name, info ) < 0 ) {
4079 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4080 __FILE__,__LINE__,info->device_name, info->irq_level );
4081 goto errout;
4082 }
4083 info->irq_requested = true;
4084
4085 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4086 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4087 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4088 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4089 goto errout;
4090 }
4091 info->shared_mem_requested = true;
4092 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4093 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4094 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4095 goto errout;
4096 }
4097 info->lcr_mem_requested = true;
4098
4099 info->memory_base = ioremap_nocache(info->phys_memory_base,
4100 0x40000);
4101 if (!info->memory_base) {
4102 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4103 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4104 goto errout;
4105 }
4106
4107 if ( !mgsl_memory_test(info) ) {
4108 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4109 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4110 goto errout;
4111 }
4112
4113 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4114 PAGE_SIZE);
4115 if (!info->lcr_base) {
4116 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4117 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4118 goto errout;
4119 }
4120 info->lcr_base += info->lcr_offset;
4121
4122 } else {
4123
4124
4125 if (request_dma(info->dma_level,info->device_name) < 0){
4126 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4127 __FILE__,__LINE__,info->device_name, info->dma_level );
4128 mgsl_release_resources( info );
4129 return -ENODEV;
4130 }
4131 info->dma_requested = true;
4132
4133
4134 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4135 enable_dma(info->dma_level);
4136 }
4137
4138 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4139 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4140 __FILE__,__LINE__,info->device_name, info->dma_level );
4141 goto errout;
4142 }
4143
4144 return 0;
4145errout:
4146 mgsl_release_resources(info);
4147 return -ENODEV;
4148
4149}
4150
4151static void mgsl_release_resources(struct mgsl_struct *info)
4152{
4153 if ( debug_level >= DEBUG_LEVEL_INFO )
4154 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4155 __FILE__,__LINE__,info->device_name );
4156
4157 if ( info->irq_requested ) {
4158 free_irq(info->irq_level, info);
4159 info->irq_requested = false;
4160 }
4161 if ( info->dma_requested ) {
4162 disable_dma(info->dma_level);
4163 free_dma(info->dma_level);
4164 info->dma_requested = false;
4165 }
4166 mgsl_free_dma_buffers(info);
4167 mgsl_free_intermediate_rxbuffer_memory(info);
4168 mgsl_free_intermediate_txbuffer_memory(info);
4169
4170 if ( info->io_addr_requested ) {
4171 release_region(info->io_base,info->io_addr_size);
4172 info->io_addr_requested = false;
4173 }
4174 if ( info->shared_mem_requested ) {
4175 release_mem_region(info->phys_memory_base,0x40000);
4176 info->shared_mem_requested = false;
4177 }
4178 if ( info->lcr_mem_requested ) {
4179 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4180 info->lcr_mem_requested = false;
4181 }
4182 if (info->memory_base){
4183 iounmap(info->memory_base);
4184 info->memory_base = NULL;
4185 }
4186 if (info->lcr_base){
4187 iounmap(info->lcr_base - info->lcr_offset);
4188 info->lcr_base = NULL;
4189 }
4190
4191 if ( debug_level >= DEBUG_LEVEL_INFO )
4192 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4193 __FILE__,__LINE__,info->device_name );
4194
4195}
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205static void mgsl_add_device( struct mgsl_struct *info )
4206{
4207 info->next_device = NULL;
4208 info->line = mgsl_device_count;
4209 sprintf(info->device_name,"ttySL%d",info->line);
4210
4211 if (info->line < MAX_TOTAL_DEVICES) {
4212 if (maxframe[info->line])
4213 info->max_frame_size = maxframe[info->line];
4214
4215 if (txdmabufs[info->line]) {
4216 info->num_tx_dma_buffers = txdmabufs[info->line];
4217 if (info->num_tx_dma_buffers < 1)
4218 info->num_tx_dma_buffers = 1;
4219 }
4220
4221 if (txholdbufs[info->line]) {
4222 info->num_tx_holding_buffers = txholdbufs[info->line];
4223 if (info->num_tx_holding_buffers < 1)
4224 info->num_tx_holding_buffers = 1;
4225 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4226 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4227 }
4228 }
4229
4230 mgsl_device_count++;
4231
4232 if ( !mgsl_device_list )
4233 mgsl_device_list = info;
4234 else {
4235 struct mgsl_struct *current_dev = mgsl_device_list;
4236 while( current_dev->next_device )
4237 current_dev = current_dev->next_device;
4238 current_dev->next_device = info;
4239 }
4240
4241 if ( info->max_frame_size < 4096 )
4242 info->max_frame_size = 4096;
4243 else if ( info->max_frame_size > 65535 )
4244 info->max_frame_size = 65535;
4245
4246 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4247 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4248 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4249 info->phys_memory_base, info->phys_lcr_base,
4250 info->max_frame_size );
4251 } else {
4252 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4253 info->device_name, info->io_base, info->irq_level, info->dma_level,
4254 info->max_frame_size );
4255 }
4256
4257#if SYNCLINK_GENERIC_HDLC
4258 hdlcdev_init(info);
4259#endif
4260
4261}
4262
4263static const struct tty_port_operations mgsl_port_ops = {
4264 .carrier_raised = carrier_raised,
4265 .dtr_rts = dtr_rts,
4266};
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276static struct mgsl_struct* mgsl_allocate_device(void)
4277{
4278 struct mgsl_struct *info;
4279
4280 info = kzalloc(sizeof(struct mgsl_struct),
4281 GFP_KERNEL);
4282
4283 if (!info) {
4284 printk("Error can't allocate device instance data\n");
4285 } else {
4286 tty_port_init(&info->port);
4287 info->port.ops = &mgsl_port_ops;
4288 info->magic = MGSL_MAGIC;
4289 INIT_WORK(&info->task, mgsl_bh_handler);
4290 info->max_frame_size = 4096;
4291 info->port.close_delay = 5*HZ/10;
4292 info->port.closing_wait = 30*HZ;
4293 init_waitqueue_head(&info->status_event_wait_q);
4294 init_waitqueue_head(&info->event_wait_q);
4295 spin_lock_init(&info->irq_spinlock);
4296 spin_lock_init(&info->netlock);
4297 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4298 info->idle_mode = HDLC_TXIDLE_FLAGS;
4299 info->num_tx_dma_buffers = 1;
4300 info->num_tx_holding_buffers = 0;
4301 }
4302
4303 return info;
4304
4305}
4306
4307static const struct tty_operations mgsl_ops = {
4308 .open = mgsl_open,
4309 .close = mgsl_close,
4310 .write = mgsl_write,
4311 .put_char = mgsl_put_char,
4312 .flush_chars = mgsl_flush_chars,
4313 .write_room = mgsl_write_room,
4314 .chars_in_buffer = mgsl_chars_in_buffer,
4315 .flush_buffer = mgsl_flush_buffer,
4316 .ioctl = mgsl_ioctl,
4317 .throttle = mgsl_throttle,
4318 .unthrottle = mgsl_unthrottle,
4319 .send_xchar = mgsl_send_xchar,
4320 .break_ctl = mgsl_break,
4321 .wait_until_sent = mgsl_wait_until_sent,
4322 .set_termios = mgsl_set_termios,
4323 .stop = mgsl_stop,
4324 .start = mgsl_start,
4325 .hangup = mgsl_hangup,
4326 .tiocmget = tiocmget,
4327 .tiocmset = tiocmset,
4328 .proc_fops = &mgsl_proc_fops,
4329};
4330
4331
4332
4333
4334static int mgsl_init_tty(void)
4335{
4336 int rc;
4337
4338 serial_driver = alloc_tty_driver(128);
4339 if (!serial_driver)
4340 return -ENOMEM;
4341
4342 serial_driver->owner = THIS_MODULE;
4343 serial_driver->driver_name = "synclink";
4344 serial_driver->name = "ttySL";
4345 serial_driver->major = ttymajor;
4346 serial_driver->minor_start = 64;
4347 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4348 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4349 serial_driver->init_termios = tty_std_termios;
4350 serial_driver->init_termios.c_cflag =
4351 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4352 serial_driver->init_termios.c_ispeed = 9600;
4353 serial_driver->init_termios.c_ospeed = 9600;
4354 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4355 tty_set_operations(serial_driver, &mgsl_ops);
4356 if ((rc = tty_register_driver(serial_driver)) < 0) {
4357 printk("%s(%d):Couldn't register serial driver\n",
4358 __FILE__,__LINE__);
4359 put_tty_driver(serial_driver);
4360 serial_driver = NULL;
4361 return rc;
4362 }
4363
4364 printk("%s %s, tty major#%d\n",
4365 driver_name, driver_version,
4366 serial_driver->major);
4367 return 0;
4368}
4369
4370
4371
4372static void mgsl_enum_isa_devices(void)
4373{
4374 struct mgsl_struct *info;
4375 int i;
4376
4377
4378
4379 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4380 if ( debug_level >= DEBUG_LEVEL_INFO )
4381 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4382 io[i], irq[i], dma[i] );
4383
4384 info = mgsl_allocate_device();
4385 if ( !info ) {
4386
4387 if ( debug_level >= DEBUG_LEVEL_ERROR )
4388 printk( "can't allocate device instance data.\n");
4389 continue;
4390 }
4391
4392
4393 info->io_base = (unsigned int)io[i];
4394 info->irq_level = (unsigned int)irq[i];
4395 info->irq_level = irq_canonicalize(info->irq_level);
4396 info->dma_level = (unsigned int)dma[i];
4397 info->bus_type = MGSL_BUS_TYPE_ISA;
4398 info->io_addr_size = 16;
4399 info->irq_flags = 0;
4400
4401 mgsl_add_device( info );
4402 }
4403}
4404
4405static void synclink_cleanup(void)
4406{
4407 int rc;
4408 struct mgsl_struct *info;
4409 struct mgsl_struct *tmp;
4410
4411 printk("Unloading %s: %s\n", driver_name, driver_version);
4412
4413 if (serial_driver) {
4414 if ((rc = tty_unregister_driver(serial_driver)))
4415 printk("%s(%d) failed to unregister tty driver err=%d\n",
4416 __FILE__,__LINE__,rc);
4417 put_tty_driver(serial_driver);
4418 }
4419
4420 info = mgsl_device_list;
4421 while(info) {
4422#if SYNCLINK_GENERIC_HDLC
4423 hdlcdev_exit(info);
4424#endif
4425 mgsl_release_resources(info);
4426 tmp = info;
4427 info = info->next_device;
4428 kfree(tmp);
4429 }
4430
4431 if (pci_registered)
4432 pci_unregister_driver(&synclink_pci_driver);
4433}
4434
4435static int __init synclink_init(void)
4436{
4437 int rc;
4438
4439 if (break_on_load) {
4440 mgsl_get_text_ptr();
4441 BREAKPOINT();
4442 }
4443
4444 printk("%s %s\n", driver_name, driver_version);
4445
4446 mgsl_enum_isa_devices();
4447 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4448 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4449 else
4450 pci_registered = true;
4451
4452 if ((rc = mgsl_init_tty()) < 0)
4453 goto error;
4454
4455 return 0;
4456
4457error:
4458 synclink_cleanup();
4459 return rc;
4460}
4461
4462static void __exit synclink_exit(void)
4463{
4464 synclink_cleanup();
4465}
4466
4467module_init(synclink_init);
4468module_exit(synclink_exit);
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4492{
4493
4494
4495
4496 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4497
4498
4499 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4500 inw( info->io_base + CCAR );
4501
4502}
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4519{
4520
4521 outw( Cmd + info->mbre_bit, info->io_base );
4522
4523
4524 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4525 inw( info->io_base );
4526
4527}
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4546{
4547
4548
4549
4550 outw( RegAddr + info->mbre_bit, info->io_base );
4551 outw( RegValue, info->io_base );
4552
4553
4554 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4555 inw( info->io_base );
4556
4557}
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4575{
4576
4577
4578
4579 outw( RegAddr + info->mbre_bit, info->io_base );
4580 return inw( info->io_base );
4581
4582}
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4602{
4603 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4604 outw( RegValue, info->io_base + CCAR );
4605
4606
4607 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4608 inw( info->io_base + CCAR );
4609
4610}
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4627{
4628 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4629 return inw( info->io_base + CCAR );
4630
4631}
4632
4633
4634
4635
4636
4637
4638
4639
4640static void usc_set_sdlc_mode( struct mgsl_struct *info )
4641{
4642 u16 RegValue;
4643 bool PreSL1660;
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654 usc_OutReg(info,TMCR,0x1f);
4655 RegValue=usc_InReg(info,TMDR);
4656 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4657
4658 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4659 {
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672 RegValue = 0x8e06;
4673
4674
4675
4676
4677
4678 }
4679 else
4680 {
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692 if (info->params.mode == MGSL_MODE_RAW) {
4693 RegValue = 0x0001;
4694
4695 usc_OutReg( info, IOCR,
4696 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710 RegValue |= 0x0400;
4711 }
4712 else {
4713
4714 RegValue = 0x0606;
4715
4716 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4717 RegValue |= BIT14;
4718 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4719 RegValue |= BIT15;
4720 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4721 RegValue |= BIT15 + BIT14;
4722 }
4723
4724 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4725 RegValue |= BIT13;
4726 }
4727
4728 if ( info->params.mode == MGSL_MODE_HDLC &&
4729 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4730 RegValue |= BIT12;
4731
4732 if ( info->params.addr_filter != 0xff )
4733 {
4734
4735 usc_OutReg( info, RSR, info->params.addr_filter );
4736 RegValue |= BIT4;
4737 }
4738
4739 usc_OutReg( info, CMR, RegValue );
4740 info->cmr_value = RegValue;
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757 RegValue = 0x0500;
4758
4759 switch ( info->params.encoding ) {
4760 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4761 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4762 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4763 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4764 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4765 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4766 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4767 }
4768
4769 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4770 RegValue |= BIT9;
4771 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4772 RegValue |= ( BIT12 | BIT10 | BIT9 );
4773
4774 usc_OutReg( info, RMR, RegValue );
4775
4776
4777
4778
4779
4780
4781
4782
4783 usc_OutReg( info, RCLR, RCLRVALUE );
4784
4785 usc_RCmd( info, RCmd_SelectRicrdma_level );
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805 RegValue = usc_InReg( info, RICR ) & 0xc0;
4806
4807 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4808 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4809 else
4810 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4811
4812
4813
4814 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4815 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832 RegValue = 0x0400;
4833
4834 switch ( info->params.encoding ) {
4835 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4836 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4837 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4838 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4839 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4840 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4841 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4842 }
4843
4844 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4845 RegValue |= BIT9 + BIT8;
4846 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4848
4849 usc_OutReg( info, TMR, RegValue );
4850
4851 usc_set_txidle( info );
4852
4853
4854 usc_TCmd( info, TCmd_SelectTicrdma_level );
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4872 usc_OutReg( info, TICR, 0x0736 );
4873 else
4874 usc_OutReg( info, TICR, 0x1436 );
4875
4876 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4877 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896 info->tcsr_value = 0;
4897
4898 if ( !PreSL1660 )
4899 info->tcsr_value |= TCSR_UNDERWAIT;
4900
4901 usc_OutReg( info, TCSR, info->tcsr_value );
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916 RegValue = 0x0f40;
4917
4918 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4919 RegValue |= 0x0003;
4920 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4921 RegValue |= 0x0004;
4922 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4923 RegValue |= 0x0006;
4924 else
4925 RegValue |= 0x0007;
4926
4927 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4928 RegValue |= 0x0018;
4929 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4930 RegValue |= 0x0020;
4931 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4932 RegValue |= 0x0038;
4933 else
4934 RegValue |= 0x0030;
4935
4936 usc_OutReg( info, CMCR, RegValue );
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954 RegValue = 0x0000;
4955
4956 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4957 u32 XtalSpeed;
4958 u32 DpllDivisor;
4959 u16 Tc;
4960
4961
4962
4963
4964 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4965 XtalSpeed = 11059200;
4966 else
4967 XtalSpeed = 14745600;
4968
4969 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4970 DpllDivisor = 16;
4971 RegValue |= BIT10;
4972 }
4973 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4974 DpllDivisor = 8;
4975 RegValue |= BIT11;
4976 }
4977 else
4978 DpllDivisor = 32;
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994 if ( info->params.clock_speed )
4995 {
4996 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4997 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4998 / info->params.clock_speed) )
4999 Tc--;
5000 }
5001 else
5002 Tc = -1;
5003
5004
5005
5006 usc_OutReg( info, TC1R, Tc );
5007
5008 RegValue |= BIT4;
5009
5010 switch ( info->params.encoding ) {
5011 case HDLC_ENCODING_NRZ:
5012 case HDLC_ENCODING_NRZB:
5013 case HDLC_ENCODING_NRZI_MARK:
5014 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5015 case HDLC_ENCODING_BIPHASE_MARK:
5016 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5017 case HDLC_ENCODING_BIPHASE_LEVEL:
5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5019 }
5020 }
5021
5022 usc_OutReg( info, HCR, RegValue );
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043 usc_OutReg( info, CCSR, 0x1020 );
5044
5045
5046 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5047 usc_OutReg( info, SICR,
5048 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5049 }
5050
5051
5052
5053 usc_EnableMasterIrqBit( info );
5054
5055 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5056 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5057
5058
5059 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5060 usc_EnableInterrupts(info, MISC);
5061
5062 info->mbre_bit = 0;
5063 outw( 0, info->io_base );
5064 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5065 info->mbre_bit = BIT8;
5066 outw( BIT8, info->io_base );
5067
5068 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5069
5070
5071 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5072 }
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5097
5098 usc_OutDmaReg( info, DCR, 0xa00b );
5099 }
5100 else
5101 usc_OutDmaReg( info, DCR, 0x800b );
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117 usc_OutDmaReg( info, RDMR, 0xf200 );
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133 usc_OutDmaReg( info, TDMR, 0xf200 );
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149 usc_OutDmaReg( info, DICR, 0x9000 );
5150
5151 usc_InDmaReg( info, RDMR );
5152 usc_InDmaReg( info, TDMR );
5153 usc_OutDmaReg( info, CDIR, 0x0303 );
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169 RegValue = 0x8080;
5170
5171 switch ( info->params.preamble_length ) {
5172 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5173 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5174 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5175 }
5176
5177 switch ( info->params.preamble ) {
5178 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5179 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5180 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5181 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5182 }
5183
5184 usc_OutReg( info, CCR, RegValue );
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5195
5196 usc_OutDmaReg( info, BDCR, 0x0000 );
5197 }
5198 else
5199 usc_OutDmaReg( info, BDCR, 0x2000 );
5200
5201 usc_stop_transmitter(info);
5202 usc_stop_receiver(info);
5203
5204}
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5217{
5218 if (enable) {
5219
5220 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235 usc_OutReg( info, CMCR, 0x0f64 );
5236
5237
5238
5239 if (info->params.clock_speed) {
5240 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5241 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5242 else
5243 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5244 } else
5245 usc_OutReg(info, TC0R, (u16)8);
5246
5247
5248
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5250
5251
5252 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5253
5254
5255 info->loopback_bits = 0x300;
5256 outw( 0x0300, info->io_base + CCAR );
5257 } else {
5258
5259 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5260
5261
5262 info->loopback_bits = 0;
5263 outw( 0,info->io_base + CCAR );
5264 }
5265
5266}
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5281{
5282 u32 XtalSpeed;
5283 u16 Tc;
5284
5285 if ( data_rate ) {
5286 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5287 XtalSpeed = 11059200;
5288 else
5289 XtalSpeed = 14745600;
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299 Tc = (u16)(XtalSpeed/data_rate);
5300 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5301 Tc--;
5302
5303
5304 usc_OutReg( info, TC0R, Tc );
5305
5306
5307
5308
5309
5310
5311
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5313
5314
5315 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5316 } else {
5317
5318 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5319 }
5320
5321}
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5338{
5339 int start_index;
5340 int end_index;
5341 int frame_start_index;
5342 bool start_of_frame_found = false;
5343 bool end_of_frame_found = false;
5344 bool reprogram_dma = false;
5345
5346 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5347 u32 phys_addr;
5348
5349 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5350 usc_RCmd( info, RCmd_EnterHuntmode );
5351 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5352
5353
5354
5355
5356 frame_start_index = start_index = end_index = info->current_rx_buffer;
5357
5358
5359
5360
5361
5362
5363 while( !buffer_list[end_index].count )
5364 {
5365
5366
5367
5368 if ( !start_of_frame_found )
5369 {
5370 start_of_frame_found = true;
5371 frame_start_index = end_index;
5372 end_of_frame_found = false;
5373 }
5374
5375 if ( buffer_list[end_index].status )
5376 {
5377
5378
5379
5380
5381
5382
5383 start_of_frame_found = false;
5384 end_of_frame_found = true;
5385 }
5386
5387
5388 end_index++;
5389 if ( end_index == info->rx_buffer_count )
5390 end_index = 0;
5391
5392 if ( start_index == end_index )
5393 {
5394
5395
5396
5397 mgsl_reset_rx_dma_buffers( info );
5398 frame_start_index = 0;
5399 start_of_frame_found = false;
5400 reprogram_dma = true;
5401 break;
5402 }
5403 }
5404
5405 if ( start_of_frame_found && !end_of_frame_found )
5406 {
5407
5408
5409
5410
5411
5412
5413
5414 start_index = frame_start_index;
5415
5416 do
5417 {
5418 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5419
5420
5421 if ( start_index == info->rx_buffer_count )
5422 start_index = 0;
5423
5424 } while( start_index != end_index );
5425
5426 reprogram_dma = true;
5427 }
5428
5429 if ( reprogram_dma )
5430 {
5431 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5432 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5433 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5434
5435 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5436
5437
5438 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5439
5440
5441 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5442 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5443 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5444
5445 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5446 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5447 usc_EnableInterrupts( info, RECEIVE_STATUS );
5448
5449
5450
5451
5452 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5453 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5454 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5455 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5456 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5457 else
5458 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5459 }
5460 else
5461 {
5462
5463 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5464 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5465 }
5466
5467}
5468
5469
5470
5471
5472
5473
5474
5475
5476static void usc_stop_receiver( struct mgsl_struct *info )
5477{
5478 if (debug_level >= DEBUG_LEVEL_ISR)
5479 printk("%s(%d):usc_stop_receiver(%s)\n",
5480 __FILE__,__LINE__, info->device_name );
5481
5482
5483
5484 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5485
5486 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5487 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5488 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5489
5490 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5491
5492
5493 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5494 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5495
5496 info->rx_enabled = false;
5497 info->rx_overflow = false;
5498 info->rx_rcc_underrun = false;
5499
5500}
5501
5502
5503
5504
5505
5506
5507
5508
5509static void usc_start_receiver( struct mgsl_struct *info )
5510{
5511 u32 phys_addr;
5512
5513 if (debug_level >= DEBUG_LEVEL_ISR)
5514 printk("%s(%d):usc_start_receiver(%s)\n",
5515 __FILE__,__LINE__, info->device_name );
5516
5517 mgsl_reset_rx_dma_buffers( info );
5518 usc_stop_receiver( info );
5519
5520 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5521 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5522
5523 if ( info->params.mode == MGSL_MODE_HDLC ||
5524 info->params.mode == MGSL_MODE_RAW ) {
5525
5526
5527
5528
5529
5530 phys_addr = info->rx_buffer_list[0].phys_entry;
5531 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5532 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5533
5534 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5535 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5536 usc_EnableInterrupts( info, RECEIVE_STATUS );
5537
5538
5539
5540
5541 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5542 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5543 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5544 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5545 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5546 else
5547 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5548 } else {
5549 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5550 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5551 usc_EnableInterrupts(info, RECEIVE_DATA);
5552
5553 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5554 usc_RCmd( info, RCmd_EnterHuntmode );
5555
5556 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5557 }
5558
5559 usc_OutReg( info, CCSR, 0x1020 );
5560
5561 info->rx_enabled = true;
5562
5563}
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573static void usc_start_transmitter( struct mgsl_struct *info )
5574{
5575 u32 phys_addr;
5576 unsigned int FrameSize;
5577
5578 if (debug_level >= DEBUG_LEVEL_ISR)
5579 printk("%s(%d):usc_start_transmitter(%s)\n",
5580 __FILE__,__LINE__, info->device_name );
5581
5582 if ( info->xmit_cnt ) {
5583
5584
5585
5586
5587
5588 info->drop_rts_on_tx_done = false;
5589
5590 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5591 usc_get_serial_signals( info );
5592 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5593 info->serial_signals |= SerialSignal_RTS;
5594 usc_set_serial_signals( info );
5595 info->drop_rts_on_tx_done = true;
5596 }
5597 }
5598
5599
5600 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5601 if ( !info->tx_active ) {
5602 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5603 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5604 usc_EnableInterrupts(info, TRANSMIT_DATA);
5605 usc_load_txfifo(info);
5606 }
5607 } else {
5608
5609 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5610
5611
5612
5613
5614 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5615
5616
5617
5618
5619
5620 if ( info->params.mode == MGSL_MODE_RAW )
5621 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5622
5623
5624
5625 usc_OutReg( info, TCLR, (u16)FrameSize );
5626
5627 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5628
5629
5630 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5631 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5632 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5633
5634 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5635 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5636 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5637
5638 if ( info->params.mode == MGSL_MODE_RAW &&
5639 info->num_tx_dma_buffers > 1 ) {
5640
5641
5642
5643
5644
5645
5646
5647 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5648 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5649 }
5650
5651
5652 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5653
5654 usc_TCmd( info, TCmd_SendFrame );
5655
5656 mod_timer(&info->tx_timer, jiffies +
5657 msecs_to_jiffies(5000));
5658 }
5659 info->tx_active = true;
5660 }
5661
5662 if ( !info->tx_enabled ) {
5663 info->tx_enabled = true;
5664 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5665 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5666 else
5667 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5668 }
5669
5670}
5671
5672
5673
5674
5675
5676
5677
5678
5679static void usc_stop_transmitter( struct mgsl_struct *info )
5680{
5681 if (debug_level >= DEBUG_LEVEL_ISR)
5682 printk("%s(%d):usc_stop_transmitter(%s)\n",
5683 __FILE__,__LINE__, info->device_name );
5684
5685 del_timer(&info->tx_timer);
5686
5687 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5688 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5689 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5690
5691 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5692 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5693 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5694
5695 info->tx_enabled = false;
5696 info->tx_active = false;
5697
5698}
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708static void usc_load_txfifo( struct mgsl_struct *info )
5709{
5710 int Fifocount;
5711 u8 TwoBytes[2];
5712
5713 if ( !info->xmit_cnt && !info->x_char )
5714 return;
5715
5716
5717 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5718
5719
5720
5721 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5722
5723
5724
5725 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5726
5727
5728 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5729 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5730 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5731 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5732
5733 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5734
5735 info->xmit_cnt -= 2;
5736 info->icount.tx += 2;
5737 } else {
5738
5739
5740 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5741 info->io_base + CCAR );
5742
5743 if (info->x_char) {
5744
5745 outw( info->x_char,info->io_base + CCAR );
5746 info->x_char = 0;
5747 } else {
5748 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5749 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5750 info->xmit_cnt--;
5751 }
5752 info->icount.tx++;
5753 }
5754 }
5755
5756}
5757
5758
5759
5760
5761
5762
5763
5764
5765static void usc_reset( struct mgsl_struct *info )
5766{
5767 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5768 int i;
5769 u32 readval;
5770
5771
5772
5773
5774 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5775 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5776
5777 info->misc_ctrl_value |= BIT30;
5778 *MiscCtrl = info->misc_ctrl_value;
5779
5780
5781
5782
5783
5784
5785 for(i=0;i<10;i++)
5786 readval = *MiscCtrl;
5787
5788 info->misc_ctrl_value &= ~BIT30;
5789 *MiscCtrl = info->misc_ctrl_value;
5790
5791 *LCR0BRDR = BUS_DESCRIPTOR(
5792 1,
5793 2,
5794 2,
5795 0,
5796 4,
5797 0,
5798 0,
5799 5
5800 );
5801 } else {
5802
5803 outb( 0,info->io_base + 8 );
5804 }
5805
5806 info->mbre_bit = 0;
5807 info->loopback_bits = 0;
5808 info->usc_idle_mode = 0;
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827 outw( 0x000c,info->io_base + SDPIN );
5828
5829
5830 outw( 0,info->io_base );
5831 outw( 0,info->io_base + CCAR );
5832
5833
5834 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851 usc_OutReg( info, PCR, 0xf0f5 );
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868 usc_OutReg( info, IOCR, 0x0004 );
5869
5870}
5871
5872
5873
5874
5875
5876
5877
5878
5879static void usc_set_async_mode( struct mgsl_struct *info )
5880{
5881 u16 RegValue;
5882
5883
5884 usc_DisableMasterIrqBit( info );
5885
5886 outw( 0, info->io_base );
5887 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5888
5889 usc_loopback_frame( info );
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903 RegValue = 0;
5904 if ( info->params.stop_bits != 1 )
5905 RegValue |= BIT14;
5906 usc_OutReg( info, CMR, RegValue );
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921 RegValue = 0;
5922
5923 if ( info->params.data_bits != 8 )
5924 RegValue |= BIT4+BIT3+BIT2;
5925
5926 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5927 RegValue |= BIT5;
5928 if ( info->params.parity != ASYNC_PARITY_ODD )
5929 RegValue |= BIT6;
5930 }
5931
5932 usc_OutReg( info, RMR, RegValue );
5933
5934
5935
5936
5937 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960 usc_OutReg( info, RICR, 0x0000 );
5961
5962 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5963 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978 RegValue = 0;
5979
5980 if ( info->params.data_bits != 8 )
5981 RegValue |= BIT4+BIT3+BIT2;
5982
5983 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5984 RegValue |= BIT5;
5985 if ( info->params.parity != ASYNC_PARITY_ODD )
5986 RegValue |= BIT6;
5987 }
5988
5989 usc_OutReg( info, TMR, RegValue );
5990
5991 usc_set_txidle( info );
5992
5993
5994
5995
5996 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014 usc_OutReg( info, TICR, 0x1f40 );
6015
6016 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6017 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6018
6019 usc_enable_async_clock( info, info->params.data_rate );
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040 usc_OutReg( info, CCSR, 0x0020 );
6041
6042 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6043 RECEIVE_DATA + RECEIVE_STATUS );
6044
6045 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6046 RECEIVE_DATA + RECEIVE_STATUS );
6047
6048 usc_EnableMasterIrqBit( info );
6049
6050 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6051
6052
6053 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6054 }
6055
6056 if (info->params.loopback) {
6057 info->loopback_bits = 0x300;
6058 outw(0x0300, info->io_base + CCAR);
6059 }
6060
6061}
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077static void usc_loopback_frame( struct mgsl_struct *info )
6078{
6079 int i;
6080 unsigned long oldmode = info->params.mode;
6081
6082 info->params.mode = MGSL_MODE_HDLC;
6083
6084 usc_DisableMasterIrqBit( info );
6085
6086 usc_set_sdlc_mode( info );
6087 usc_enable_loopback( info, 1 );
6088
6089
6090 usc_OutReg( info, TC0R, 0 );
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106 usc_OutReg( info, CCR, 0x0100 );
6107
6108
6109 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6110 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6111
6112
6113
6114
6115 usc_OutReg( info, TCLR, 2 );
6116 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6117
6118
6119 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6120 outw(0,info->io_base + DATAREG);
6121
6122
6123 usc_TCmd( info, TCmd_SendFrame );
6124 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6125
6126
6127 for (i=0 ; i<1000 ; i++)
6128 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6129 break;
6130
6131
6132 usc_enable_loopback(info, 0);
6133
6134 usc_EnableMasterIrqBit(info);
6135
6136 info->params.mode = oldmode;
6137
6138}
6139
6140
6141
6142
6143
6144
6145static void usc_set_sync_mode( struct mgsl_struct *info )
6146{
6147 usc_loopback_frame( info );
6148 usc_set_sdlc_mode( info );
6149
6150 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6151
6152
6153 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6154 }
6155
6156 usc_enable_aux_clock(info, info->params.clock_speed);
6157
6158 if (info->params.loopback)
6159 usc_enable_loopback(info,1);
6160
6161}
6162
6163
6164
6165
6166
6167
6168static void usc_set_txidle( struct mgsl_struct *info )
6169{
6170 u16 usc_idle_mode = IDLEMODE_FLAGS;
6171
6172
6173
6174 switch( info->idle_mode ){
6175 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6176 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6177 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6178 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6179 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6180 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6181 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6182 }
6183
6184 info->usc_idle_mode = usc_idle_mode;
6185
6186 info->tcsr_value &= ~IDLEMODE_MASK;
6187 info->tcsr_value += usc_idle_mode;
6188 usc_OutReg(info, TCSR, info->tcsr_value);
6189
6190
6191
6192
6193
6194
6195
6196
6197 if ( info->params.mode == MGSL_MODE_RAW ) {
6198 unsigned char syncpat = 0;
6199 switch( info->idle_mode ) {
6200 case HDLC_TXIDLE_FLAGS:
6201 syncpat = 0x7e;
6202 break;
6203 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6204 syncpat = 0x55;
6205 break;
6206 case HDLC_TXIDLE_ZEROS:
6207 case HDLC_TXIDLE_SPACE:
6208 syncpat = 0x00;
6209 break;
6210 case HDLC_TXIDLE_ONES:
6211 case HDLC_TXIDLE_MARK:
6212 syncpat = 0xff;
6213 break;
6214 case HDLC_TXIDLE_ALT_MARK_SPACE:
6215 syncpat = 0xaa;
6216 break;
6217 }
6218
6219 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6220 }
6221
6222}
6223
6224
6225
6226
6227
6228
6229
6230
6231static void usc_get_serial_signals( struct mgsl_struct *info )
6232{
6233 u16 status;
6234
6235
6236 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6237
6238
6239
6240
6241 status = usc_InReg( info, MISR );
6242
6243
6244
6245 if ( status & MISCSTATUS_CTS )
6246 info->serial_signals |= SerialSignal_CTS;
6247
6248 if ( status & MISCSTATUS_DCD )
6249 info->serial_signals |= SerialSignal_DCD;
6250
6251 if ( status & MISCSTATUS_RI )
6252 info->serial_signals |= SerialSignal_RI;
6253
6254 if ( status & MISCSTATUS_DSR )
6255 info->serial_signals |= SerialSignal_DSR;
6256
6257}
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267static void usc_set_serial_signals( struct mgsl_struct *info )
6268{
6269 u16 Control;
6270 unsigned char V24Out = info->serial_signals;
6271
6272
6273
6274 Control = usc_InReg( info, PCR );
6275
6276 if ( V24Out & SerialSignal_RTS )
6277 Control &= ~(BIT6);
6278 else
6279 Control |= BIT6;
6280
6281 if ( V24Out & SerialSignal_DTR )
6282 Control &= ~(BIT4);
6283 else
6284 Control |= BIT4;
6285
6286 usc_OutReg( info, PCR, Control );
6287
6288}
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6300{
6301 if ( data_rate ) {
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316 usc_OutReg( info, CMCR, 0x0f64 );
6317
6318
6319
6320
6321
6322
6323
6324
6325 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6326 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6327 else
6328 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6329
6330
6331
6332
6333
6334
6335
6336
6337 usc_OutReg( info, HCR,
6338 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6339
6340
6341
6342
6343 usc_OutReg( info, IOCR,
6344 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6345 } else {
6346
6347 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6348 }
6349
6350}
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6410{
6411 unsigned int i;
6412
6413 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6414 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6415 }
6416
6417 info->current_tx_buffer = 0;
6418 info->start_tx_dma_buffer = 0;
6419 info->tx_dma_buffers_used = 0;
6420
6421 info->get_tx_holding_index = 0;
6422 info->put_tx_holding_index = 0;
6423 info->tx_holding_count = 0;
6424
6425}
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6436{
6437 return info->tx_buffer_count - info->tx_dma_buffers_used;
6438}
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6451{
6452 unsigned int i;
6453
6454 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6455 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6456
6457
6458 }
6459
6460 info->current_rx_buffer = 0;
6461
6462}
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6479{
6480 bool Done = false;
6481 DMABUFFERENTRY *pBufEntry;
6482 unsigned int Index;
6483
6484
6485
6486
6487 Index = StartIndex;
6488
6489 while( !Done ) {
6490 pBufEntry = &(info->rx_buffer_list[Index]);
6491
6492 if ( Index == EndIndex ) {
6493
6494 Done = true;
6495 }
6496
6497
6498
6499
6500 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6501
6502
6503 Index++;
6504 if ( Index == info->rx_buffer_count )
6505 Index = 0;
6506 }
6507
6508
6509 info->current_rx_buffer = Index;
6510
6511}
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6522{
6523 unsigned int StartIndex, EndIndex;
6524 unsigned short status;
6525 DMABUFFERENTRY *pBufEntry;
6526 unsigned int framesize = 0;
6527 bool ReturnCode = false;
6528 unsigned long flags;
6529 struct tty_struct *tty = info->port.tty;
6530 bool return_frame = false;
6531
6532
6533
6534
6535
6536
6537
6538
6539 StartIndex = EndIndex = info->current_rx_buffer;
6540
6541 while( !info->rx_buffer_list[EndIndex].status ) {
6542
6543
6544
6545
6546
6547
6548
6549 if ( info->rx_buffer_list[EndIndex].count )
6550 goto Cleanup;
6551
6552
6553 EndIndex++;
6554 if ( EndIndex == info->rx_buffer_count )
6555 EndIndex = 0;
6556
6557
6558 if ( EndIndex == StartIndex ) {
6559
6560
6561
6562
6563
6564 if ( info->rx_enabled ){
6565 spin_lock_irqsave(&info->irq_spinlock,flags);
6566 usc_start_receiver(info);
6567 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6568 }
6569 goto Cleanup;
6570 }
6571 }
6572
6573
6574
6575
6576 status = info->rx_buffer_list[EndIndex].status;
6577
6578 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6579 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6580 if ( status & RXSTATUS_SHORT_FRAME )
6581 info->icount.rxshort++;
6582 else if ( status & RXSTATUS_ABORT )
6583 info->icount.rxabort++;
6584 else if ( status & RXSTATUS_OVERRUN )
6585 info->icount.rxover++;
6586 else {
6587 info->icount.rxcrc++;
6588 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6589 return_frame = true;
6590 }
6591 framesize = 0;
6592#if SYNCLINK_GENERIC_HDLC
6593 {
6594 info->netdev->stats.rx_errors++;
6595 info->netdev->stats.rx_frame_errors++;
6596 }
6597#endif
6598 } else
6599 return_frame = true;
6600
6601 if ( return_frame ) {
6602
6603
6604
6605
6606
6607
6608 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6609
6610
6611 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6612 framesize -= 2;
6613 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6614 framesize -= 4;
6615 }
6616
6617 if ( debug_level >= DEBUG_LEVEL_BH )
6618 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6619 __FILE__,__LINE__,info->device_name,status,framesize);
6620
6621 if ( debug_level >= DEBUG_LEVEL_DATA )
6622 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6623 min_t(int, framesize, DMABUFFERSIZE),0);
6624
6625 if (framesize) {
6626 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6627 ((framesize+1) > info->max_frame_size) ) ||
6628 (framesize > info->max_frame_size) )
6629 info->icount.rxlong++;
6630 else {
6631
6632 int copy_count = framesize;
6633 int index = StartIndex;
6634 unsigned char *ptmp = info->intermediate_rxbuffer;
6635
6636 if ( !(status & RXSTATUS_CRC_ERROR))
6637 info->icount.rxok++;
6638
6639 while(copy_count) {
6640 int partial_count;
6641 if ( copy_count > DMABUFFERSIZE )
6642 partial_count = DMABUFFERSIZE;
6643 else
6644 partial_count = copy_count;
6645
6646 pBufEntry = &(info->rx_buffer_list[index]);
6647 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6648 ptmp += partial_count;
6649 copy_count -= partial_count;
6650
6651 if ( ++index == info->rx_buffer_count )
6652 index = 0;
6653 }
6654
6655 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6656 ++framesize;
6657 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6658 RX_CRC_ERROR :
6659 RX_OK);
6660
6661 if ( debug_level >= DEBUG_LEVEL_DATA )
6662 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6663 __FILE__,__LINE__,info->device_name,
6664 *ptmp);
6665 }
6666
6667#if SYNCLINK_GENERIC_HDLC
6668 if (info->netcount)
6669 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6670 else
6671#endif
6672 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6673 }
6674 }
6675
6676 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6677
6678 ReturnCode = true;
6679
6680Cleanup:
6681
6682 if ( info->rx_enabled && info->rx_overflow ) {
6683
6684
6685
6686
6687
6688 if ( !info->rx_buffer_list[EndIndex].status &&
6689 info->rx_buffer_list[EndIndex].count ) {
6690 spin_lock_irqsave(&info->irq_spinlock,flags);
6691 usc_start_receiver(info);
6692 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6693 }
6694 }
6695
6696 return ReturnCode;
6697
6698}
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6720{
6721 unsigned int CurrentIndex, NextIndex;
6722 unsigned short status;
6723 DMABUFFERENTRY *pBufEntry;
6724 unsigned int framesize = 0;
6725 bool ReturnCode = false;
6726 unsigned long flags;
6727 struct tty_struct *tty = info->port.tty;
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744 CurrentIndex = NextIndex = info->current_rx_buffer;
6745 ++NextIndex;
6746 if ( NextIndex == info->rx_buffer_count )
6747 NextIndex = 0;
6748
6749 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6750 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6751 info->rx_buffer_list[NextIndex].count == 0)) {
6752
6753
6754
6755
6756
6757
6758
6759 status = info->rx_buffer_list[CurrentIndex].status;
6760
6761 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6762 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6763 if ( status & RXSTATUS_SHORT_FRAME )
6764 info->icount.rxshort++;
6765 else if ( status & RXSTATUS_ABORT )
6766 info->icount.rxabort++;
6767 else if ( status & RXSTATUS_OVERRUN )
6768 info->icount.rxover++;
6769 else
6770 info->icount.rxcrc++;
6771 framesize = 0;
6772 } else {
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796 if ( status ) {
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808 if ( info->rx_buffer_list[CurrentIndex].rcc )
6809 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6810 else
6811 framesize = DMABUFFERSIZE;
6812 }
6813 else
6814 framesize = DMABUFFERSIZE;
6815 }
6816
6817 if ( framesize > DMABUFFERSIZE ) {
6818
6819
6820
6821
6822
6823
6824 framesize = framesize % DMABUFFERSIZE;
6825 }
6826
6827
6828 if ( debug_level >= DEBUG_LEVEL_BH )
6829 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6830 __FILE__,__LINE__,info->device_name,status,framesize);
6831
6832 if ( debug_level >= DEBUG_LEVEL_DATA )
6833 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6834 min_t(int, framesize, DMABUFFERSIZE),0);
6835
6836 if (framesize) {
6837
6838
6839
6840 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6841 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6842 info->icount.rxok++;
6843
6844 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6845 }
6846
6847
6848 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6849
6850 ReturnCode = true;
6851 }
6852
6853
6854 if ( info->rx_enabled && info->rx_overflow ) {
6855
6856
6857
6858
6859
6860 if ( !info->rx_buffer_list[CurrentIndex].status &&
6861 info->rx_buffer_list[CurrentIndex].count ) {
6862 spin_lock_irqsave(&info->irq_spinlock,flags);
6863 usc_start_receiver(info);
6864 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6865 }
6866 }
6867
6868 return ReturnCode;
6869
6870}
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6885 const char *Buffer, unsigned int BufferSize)
6886{
6887 unsigned short Copycount;
6888 unsigned int i = 0;
6889 DMABUFFERENTRY *pBufEntry;
6890
6891 if ( debug_level >= DEBUG_LEVEL_DATA )
6892 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6893
6894 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6895
6896
6897
6898 info->cmr_value |= BIT13;
6899 }
6900
6901
6902
6903
6904
6905 i = info->current_tx_buffer;
6906 info->start_tx_dma_buffer = i;
6907
6908
6909
6910
6911 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6912 info->tx_buffer_list[i].rcc = BufferSize;
6913 info->tx_buffer_list[i].count = BufferSize;
6914
6915
6916
6917
6918 while( BufferSize ){
6919
6920 pBufEntry = &info->tx_buffer_list[i++];
6921
6922 if ( i == info->tx_buffer_count )
6923 i=0;
6924
6925
6926
6927 if ( BufferSize > DMABUFFERSIZE )
6928 Copycount = DMABUFFERSIZE;
6929 else
6930 Copycount = BufferSize;
6931
6932
6933
6934 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6935 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6936 else
6937 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6938
6939 pBufEntry->count = Copycount;
6940
6941
6942 Buffer += Copycount;
6943 BufferSize -= Copycount;
6944
6945 ++info->tx_dma_buffers_used;
6946 }
6947
6948
6949 info->current_tx_buffer = i;
6950
6951}
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961static bool mgsl_register_test( struct mgsl_struct *info )
6962{
6963 static unsigned short BitPatterns[] =
6964 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6965 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6966 unsigned int i;
6967 bool rc = true;
6968 unsigned long flags;
6969
6970 spin_lock_irqsave(&info->irq_spinlock,flags);
6971 usc_reset(info);
6972
6973
6974
6975 if ( (usc_InReg( info, SICR ) != 0) ||
6976 (usc_InReg( info, IVR ) != 0) ||
6977 (usc_InDmaReg( info, DIVR ) != 0) ){
6978 rc = false;
6979 }
6980
6981 if ( rc ){
6982
6983
6984
6985 for ( i = 0 ; i < Patterncount ; i++ ) {
6986 usc_OutReg( info, TC0R, BitPatterns[i] );
6987 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6988 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6989 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6990 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6991 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6992
6993 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6994 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6995 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6996 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6997 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6998 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6999 rc = false;
7000 break;
7001 }
7002 }
7003 }
7004
7005 usc_reset(info);
7006 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7007
7008 return rc;
7009
7010}
7011
7012
7013
7014
7015
7016
7017static bool mgsl_irq_test( struct mgsl_struct *info )
7018{
7019 unsigned long EndTime;
7020 unsigned long flags;
7021
7022 spin_lock_irqsave(&info->irq_spinlock,flags);
7023 usc_reset(info);
7024
7025
7026
7027
7028
7029
7030 info->irq_occurred = false;
7031
7032
7033
7034
7035
7036 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7037
7038 usc_EnableMasterIrqBit(info);
7039 usc_EnableInterrupts(info, IO_PIN);
7040 usc_ClearIrqPendingBits(info, IO_PIN);
7041
7042 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7043 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7044
7045 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7046
7047 EndTime=100;
7048 while( EndTime-- && !info->irq_occurred ) {
7049 msleep_interruptible(10);
7050 }
7051
7052 spin_lock_irqsave(&info->irq_spinlock,flags);
7053 usc_reset(info);
7054 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7055
7056 return info->irq_occurred;
7057
7058}
7059
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069static bool mgsl_dma_test( struct mgsl_struct *info )
7070{
7071 unsigned short FifoLevel;
7072 unsigned long phys_addr;
7073 unsigned int FrameSize;
7074 unsigned int i;
7075 char *TmpPtr;
7076 bool rc = true;
7077 unsigned short status=0;
7078 unsigned long EndTime;
7079 unsigned long flags;
7080 MGSL_PARAMS tmp_params;
7081
7082
7083 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7084
7085 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7086
7087#define TESTFRAMESIZE 40
7088
7089 spin_lock_irqsave(&info->irq_spinlock,flags);
7090
7091
7092
7093 usc_reset(info);
7094 usc_set_sdlc_mode(info);
7095 usc_enable_loopback(info,1);
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117 usc_OutDmaReg( info, RDMR, 0xe200 );
7118
7119 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7120
7121
7122
7123
7124 FrameSize = TESTFRAMESIZE;
7125
7126
7127
7128
7129 info->tx_buffer_list[0].count = FrameSize;
7130 info->tx_buffer_list[0].rcc = FrameSize;
7131 info->tx_buffer_list[0].status = 0x4000;
7132
7133
7134
7135 TmpPtr = info->tx_buffer_list[0].virt_addr;
7136 for (i = 0; i < FrameSize; i++ )
7137 *TmpPtr++ = i;
7138
7139
7140
7141
7142 info->rx_buffer_list[0].status = 0;
7143 info->rx_buffer_list[0].count = FrameSize + 4;
7144
7145
7146
7147 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7148
7149
7150
7151
7152 info->tx_buffer_list[1].count = 0;
7153 info->rx_buffer_list[1].count = 0;
7154
7155
7156
7157
7158
7159
7160 spin_lock_irqsave(&info->irq_spinlock,flags);
7161
7162
7163 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7164
7165
7166 phys_addr = info->rx_buffer_list[0].phys_entry;
7167 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7168 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7169
7170
7171 usc_InDmaReg( info, RDMR );
7172 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7173
7174
7175 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7176
7177 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7178
7179
7180
7181
7182
7183
7184
7185 EndTime = jiffies + msecs_to_jiffies(100);
7186
7187 for(;;) {
7188 if (time_after(jiffies, EndTime)) {
7189 rc = false;
7190 break;
7191 }
7192
7193 spin_lock_irqsave(&info->irq_spinlock,flags);
7194 status = usc_InDmaReg( info, RDMR );
7195 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7196
7197 if ( !(status & BIT4) && (status & BIT5) ) {
7198
7199
7200
7201 break;
7202 }
7203 }
7204
7205
7206
7207
7208
7209
7210 spin_lock_irqsave(&info->irq_spinlock,flags);
7211
7212
7213
7214
7215 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7216 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7217
7218
7219
7220 phys_addr = info->tx_buffer_list[0].phys_entry;
7221 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7222 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7223
7224
7225
7226 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7227 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7228
7229
7230
7231 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7232
7233 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7234
7235
7236
7237
7238
7239
7240
7241 EndTime = jiffies + msecs_to_jiffies(100);
7242
7243 for(;;) {
7244 if (time_after(jiffies, EndTime)) {
7245 rc = false;
7246 break;
7247 }
7248
7249 spin_lock_irqsave(&info->irq_spinlock,flags);
7250 FifoLevel = usc_InReg(info, TICR) >> 8;
7251 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7252
7253 if ( FifoLevel < 16 )
7254 break;
7255 else
7256 if ( FrameSize < 32 ) {
7257
7258
7259 if ( FifoLevel <= (32 - FrameSize) )
7260 break;
7261 }
7262 }
7263
7264
7265 if ( rc )
7266 {
7267
7268
7269 spin_lock_irqsave(&info->irq_spinlock,flags);
7270
7271
7272 usc_TCmd( info, TCmd_SendFrame );
7273 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7274
7275 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7276
7277
7278
7279
7280
7281
7282
7283 EndTime = jiffies + msecs_to_jiffies(100);
7284
7285
7286
7287 spin_lock_irqsave(&info->irq_spinlock,flags);
7288 status = usc_InReg( info, TCSR );
7289 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7290
7291 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7292 if (time_after(jiffies, EndTime)) {
7293 rc = false;
7294 break;
7295 }
7296
7297 spin_lock_irqsave(&info->irq_spinlock,flags);
7298 status = usc_InReg( info, TCSR );
7299 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7300 }
7301 }
7302
7303
7304 if ( rc ){
7305
7306 if ( status & (BIT5 + BIT1) )
7307 rc = false;
7308 }
7309
7310 if ( rc ) {
7311
7312
7313
7314 EndTime = jiffies + msecs_to_jiffies(100);
7315
7316
7317 status=info->rx_buffer_list[0].status;
7318 while ( status == 0 ) {
7319 if (time_after(jiffies, EndTime)) {
7320 rc = false;
7321 break;
7322 }
7323 status=info->rx_buffer_list[0].status;
7324 }
7325 }
7326
7327
7328 if ( rc ) {
7329
7330 status = info->rx_buffer_list[0].status;
7331
7332 if ( status & (BIT8 + BIT3 + BIT1) ) {
7333
7334 rc = false;
7335 } else {
7336 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7337 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7338 rc = false;
7339 }
7340 }
7341 }
7342
7343 spin_lock_irqsave(&info->irq_spinlock,flags);
7344 usc_reset( info );
7345 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7346
7347
7348 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7349
7350 return rc;
7351
7352}
7353
7354
7355
7356
7357
7358
7359
7360
7361static int mgsl_adapter_test( struct mgsl_struct *info )
7362{
7363 if ( debug_level >= DEBUG_LEVEL_INFO )
7364 printk( "%s(%d):Testing device %s\n",
7365 __FILE__,__LINE__,info->device_name );
7366
7367 if ( !mgsl_register_test( info ) ) {
7368 info->init_error = DiagStatus_AddressFailure;
7369 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7370 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7371 return -ENODEV;
7372 }
7373
7374 if ( !mgsl_irq_test( info ) ) {
7375 info->init_error = DiagStatus_IrqFailure;
7376 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7377 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7378 return -ENODEV;
7379 }
7380
7381 if ( !mgsl_dma_test( info ) ) {
7382 info->init_error = DiagStatus_DmaFailure;
7383 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7384 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7385 return -ENODEV;
7386 }
7387
7388 if ( debug_level >= DEBUG_LEVEL_INFO )
7389 printk( "%s(%d):device %s passed diagnostics\n",
7390 __FILE__,__LINE__,info->device_name );
7391
7392 return 0;
7393
7394}
7395
7396
7397
7398
7399
7400
7401
7402
7403static bool mgsl_memory_test( struct mgsl_struct *info )
7404{
7405 static unsigned long BitPatterns[] =
7406 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7407 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7408 unsigned long i;
7409 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7410 unsigned long * TestAddr;
7411
7412 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7413 return true;
7414
7415 TestAddr = (unsigned long *)info->memory_base;
7416
7417
7418
7419 for ( i = 0 ; i < Patterncount ; i++ ) {
7420 *TestAddr = BitPatterns[i];
7421 if ( *TestAddr != BitPatterns[i] )
7422 return false;
7423 }
7424
7425
7426
7427
7428 for ( i = 0 ; i < TestLimit ; i++ ) {
7429 *TestAddr = i * 4;
7430 TestAddr++;
7431 }
7432
7433 TestAddr = (unsigned long *)info->memory_base;
7434
7435 for ( i = 0 ; i < TestLimit ; i++ ) {
7436 if ( *TestAddr != i * 4 )
7437 return false;
7438 TestAddr++;
7439 }
7440
7441 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7442
7443 return true;
7444
7445}
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7485 unsigned short count )
7486{
7487
7488#define PCI_LOAD_INTERVAL 64
7489
7490 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7491 unsigned short Index;
7492 unsigned long Dummy;
7493
7494 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7495 {
7496 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7497 Dummy = *((volatile unsigned long *)TargetPtr);
7498 TargetPtr += PCI_LOAD_INTERVAL;
7499 SourcePtr += PCI_LOAD_INTERVAL;
7500 }
7501
7502 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7503
7504}
7505
7506static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7507{
7508 int i;
7509 int linecount;
7510 if (xmit)
7511 printk("%s tx data:\n",info->device_name);
7512 else
7513 printk("%s rx data:\n",info->device_name);
7514
7515 while(count) {
7516 if (count > 16)
7517 linecount = 16;
7518 else
7519 linecount = count;
7520
7521 for(i=0;i<linecount;i++)
7522 printk("%02X ",(unsigned char)data[i]);
7523 for(;i<17;i++)
7524 printk(" ");
7525 for(i=0;i<linecount;i++) {
7526 if (data[i]>=040 && data[i]<=0176)
7527 printk("%c",data[i]);
7528 else
7529 printk(".");
7530 }
7531 printk("\n");
7532
7533 data += linecount;
7534 count -= linecount;
7535 }
7536}
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546static void mgsl_tx_timeout(unsigned long context)
7547{
7548 struct mgsl_struct *info = (struct mgsl_struct*)context;
7549 unsigned long flags;
7550
7551 if ( debug_level >= DEBUG_LEVEL_INFO )
7552 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7553 __FILE__,__LINE__,info->device_name);
7554 if(info->tx_active &&
7555 (info->params.mode == MGSL_MODE_HDLC ||
7556 info->params.mode == MGSL_MODE_RAW) ) {
7557 info->icount.txtimeout++;
7558 }
7559 spin_lock_irqsave(&info->irq_spinlock,flags);
7560 info->tx_active = false;
7561 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7562
7563 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7564 usc_loopmode_cancel_transmit( info );
7565
7566 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7567
7568#if SYNCLINK_GENERIC_HDLC
7569 if (info->netcount)
7570 hdlcdev_tx_done(info);
7571 else
7572#endif
7573 mgsl_bh_transmit(info);
7574
7575}
7576
7577
7578
7579
7580
7581static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7582{
7583 unsigned long flags;
7584
7585 spin_lock_irqsave(&info->irq_spinlock,flags);
7586 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7587 if (info->tx_active)
7588 info->loopmode_send_done_requested = true;
7589 else
7590 usc_loopmode_send_done(info);
7591 }
7592 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7593
7594 return 0;
7595}
7596
7597
7598
7599
7600static void usc_loopmode_send_done( struct mgsl_struct * info )
7601{
7602 info->loopmode_send_done_requested = false;
7603
7604 info->cmr_value &= ~BIT13;
7605 usc_OutReg(info, CMR, info->cmr_value);
7606}
7607
7608
7609
7610static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7611{
7612
7613 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7614 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7615 usc_loopmode_send_done( info );
7616}
7617
7618
7619
7620
7621
7622static void usc_loopmode_insert_request( struct mgsl_struct * info )
7623{
7624 info->loopmode_insert_requested = true;
7625
7626
7627
7628
7629 usc_OutReg( info, RICR,
7630 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7631
7632
7633 info->cmr_value |= BIT13;
7634 usc_OutReg(info, CMR, info->cmr_value);
7635}
7636
7637
7638
7639static int usc_loopmode_active( struct mgsl_struct * info)
7640{
7641 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7642}
7643
7644#if SYNCLINK_GENERIC_HDLC
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7657 unsigned short parity)
7658{
7659 struct mgsl_struct *info = dev_to_port(dev);
7660 unsigned char new_encoding;
7661 unsigned short new_crctype;
7662
7663
7664 if (info->port.count)
7665 return -EBUSY;
7666
7667 switch (encoding)
7668 {
7669 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7670 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7671 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7672 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7673 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7674 default: return -EINVAL;
7675 }
7676
7677 switch (parity)
7678 {
7679 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7680 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7681 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7682 default: return -EINVAL;
7683 }
7684
7685 info->params.encoding = new_encoding;
7686 info->params.crc_type = new_crctype;
7687
7688
7689 if (info->netcount)
7690 mgsl_program_hw(info);
7691
7692 return 0;
7693}
7694
7695
7696
7697
7698
7699
7700
7701static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7702 struct net_device *dev)
7703{
7704 struct mgsl_struct *info = dev_to_port(dev);
7705 unsigned long flags;
7706
7707 if (debug_level >= DEBUG_LEVEL_INFO)
7708 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7709
7710
7711 netif_stop_queue(dev);
7712
7713
7714 info->xmit_cnt = skb->len;
7715 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7716
7717
7718 dev->stats.tx_packets++;
7719 dev->stats.tx_bytes += skb->len;
7720
7721
7722 dev_kfree_skb(skb);
7723
7724
7725 dev->trans_start = jiffies;
7726
7727
7728 spin_lock_irqsave(&info->irq_spinlock,flags);
7729 if (!info->tx_active)
7730 usc_start_transmitter(info);
7731 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7732
7733 return NETDEV_TX_OK;
7734}
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744static int hdlcdev_open(struct net_device *dev)
7745{
7746 struct mgsl_struct *info = dev_to_port(dev);
7747 int rc;
7748 unsigned long flags;
7749
7750 if (debug_level >= DEBUG_LEVEL_INFO)
7751 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7752
7753
7754 if ((rc = hdlc_open(dev)))
7755 return rc;
7756
7757
7758 spin_lock_irqsave(&info->netlock, flags);
7759 if (info->port.count != 0 || info->netcount != 0) {
7760 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7761 spin_unlock_irqrestore(&info->netlock, flags);
7762 return -EBUSY;
7763 }
7764 info->netcount=1;
7765 spin_unlock_irqrestore(&info->netlock, flags);
7766
7767
7768 if ((rc = startup(info)) != 0) {
7769 spin_lock_irqsave(&info->netlock, flags);
7770 info->netcount=0;
7771 spin_unlock_irqrestore(&info->netlock, flags);
7772 return rc;
7773 }
7774
7775
7776 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7777 mgsl_program_hw(info);
7778
7779
7780 dev->trans_start = jiffies;
7781 netif_start_queue(dev);
7782
7783
7784 spin_lock_irqsave(&info->irq_spinlock, flags);
7785 usc_get_serial_signals(info);
7786 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7787 if (info->serial_signals & SerialSignal_DCD)
7788 netif_carrier_on(dev);
7789 else
7790 netif_carrier_off(dev);
7791 return 0;
7792}
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802static int hdlcdev_close(struct net_device *dev)
7803{
7804 struct mgsl_struct *info = dev_to_port(dev);
7805 unsigned long flags;
7806
7807 if (debug_level >= DEBUG_LEVEL_INFO)
7808 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7809
7810 netif_stop_queue(dev);
7811
7812
7813 shutdown(info);
7814
7815 hdlc_close(dev);
7816
7817 spin_lock_irqsave(&info->netlock, flags);
7818 info->netcount=0;
7819 spin_unlock_irqrestore(&info->netlock, flags);
7820
7821 return 0;
7822}
7823
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7834{
7835 const size_t size = sizeof(sync_serial_settings);
7836 sync_serial_settings new_line;
7837 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7838 struct mgsl_struct *info = dev_to_port(dev);
7839 unsigned int flags;
7840
7841 if (debug_level >= DEBUG_LEVEL_INFO)
7842 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7843
7844
7845 if (info->port.count)
7846 return -EBUSY;
7847
7848 if (cmd != SIOCWANDEV)
7849 return hdlc_ioctl(dev, ifr, cmd);
7850
7851 switch(ifr->ifr_settings.type) {
7852 case IF_GET_IFACE:
7853
7854 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7855 if (ifr->ifr_settings.size < size) {
7856 ifr->ifr_settings.size = size;
7857 return -ENOBUFS;
7858 }
7859
7860 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7861 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7862 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7863 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7864
7865 switch (flags){
7866 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7867 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7868 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7870 default: new_line.clock_type = CLOCK_DEFAULT;
7871 }
7872
7873 new_line.clock_rate = info->params.clock_speed;
7874 new_line.loopback = info->params.loopback ? 1:0;
7875
7876 if (copy_to_user(line, &new_line, size))
7877 return -EFAULT;
7878 return 0;
7879
7880 case IF_IFACE_SYNC_SERIAL:
7881
7882 if(!capable(CAP_NET_ADMIN))
7883 return -EPERM;
7884 if (copy_from_user(&new_line, line, size))
7885 return -EFAULT;
7886
7887 switch (new_line.clock_type)
7888 {
7889 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7890 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7891 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7892 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7893 case CLOCK_DEFAULT: flags = info->params.flags &
7894 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7895 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7896 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7897 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7898 default: return -EINVAL;
7899 }
7900
7901 if (new_line.loopback != 0 && new_line.loopback != 1)
7902 return -EINVAL;
7903
7904 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7905 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7906 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7907 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7908 info->params.flags |= flags;
7909
7910 info->params.loopback = new_line.loopback;
7911
7912 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7913 info->params.clock_speed = new_line.clock_rate;
7914 else
7915 info->params.clock_speed = 0;
7916
7917
7918 if (info->netcount)
7919 mgsl_program_hw(info);
7920 return 0;
7921
7922 default:
7923 return hdlc_ioctl(dev, ifr, cmd);
7924 }
7925}
7926
7927
7928
7929
7930
7931
7932static void hdlcdev_tx_timeout(struct net_device *dev)
7933{
7934 struct mgsl_struct *info = dev_to_port(dev);
7935 unsigned long flags;
7936
7937 if (debug_level >= DEBUG_LEVEL_INFO)
7938 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7939
7940 dev->stats.tx_errors++;
7941 dev->stats.tx_aborted_errors++;
7942
7943 spin_lock_irqsave(&info->irq_spinlock,flags);
7944 usc_stop_transmitter(info);
7945 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7946
7947 netif_wake_queue(dev);
7948}
7949
7950
7951
7952
7953
7954
7955
7956static void hdlcdev_tx_done(struct mgsl_struct *info)
7957{
7958 if (netif_queue_stopped(info->netdev))
7959 netif_wake_queue(info->netdev);
7960}
7961
7962
7963
7964
7965
7966
7967
7968
7969
7970static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7971{
7972 struct sk_buff *skb = dev_alloc_skb(size);
7973 struct net_device *dev = info->netdev;
7974
7975 if (debug_level >= DEBUG_LEVEL_INFO)
7976 printk("hdlcdev_rx(%s)\n", dev->name);
7977
7978 if (skb == NULL) {
7979 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7980 dev->name);
7981 dev->stats.rx_dropped++;
7982 return;
7983 }
7984
7985 memcpy(skb_put(skb, size), buf, size);
7986
7987 skb->protocol = hdlc_type_trans(skb, dev);
7988
7989 dev->stats.rx_packets++;
7990 dev->stats.rx_bytes += size;
7991
7992 netif_rx(skb);
7993}
7994
7995static const struct net_device_ops hdlcdev_ops = {
7996 .ndo_open = hdlcdev_open,
7997 .ndo_stop = hdlcdev_close,
7998 .ndo_change_mtu = hdlc_change_mtu,
7999 .ndo_start_xmit = hdlc_start_xmit,
8000 .ndo_do_ioctl = hdlcdev_ioctl,
8001 .ndo_tx_timeout = hdlcdev_tx_timeout,
8002};
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012static int hdlcdev_init(struct mgsl_struct *info)
8013{
8014 int rc;
8015 struct net_device *dev;
8016 hdlc_device *hdlc;
8017
8018
8019
8020 if (!(dev = alloc_hdlcdev(info))) {
8021 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8022 return -ENOMEM;
8023 }
8024
8025
8026 dev->base_addr = info->io_base;
8027 dev->irq = info->irq_level;
8028 dev->dma = info->dma_level;
8029
8030
8031 dev->netdev_ops = &hdlcdev_ops;
8032 dev->watchdog_timeo = 10 * HZ;
8033 dev->tx_queue_len = 50;
8034
8035
8036 hdlc = dev_to_hdlc(dev);
8037 hdlc->attach = hdlcdev_attach;
8038 hdlc->xmit = hdlcdev_xmit;
8039
8040
8041 if ((rc = register_hdlc_device(dev))) {
8042 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8043 free_netdev(dev);
8044 return rc;
8045 }
8046
8047 info->netdev = dev;
8048 return 0;
8049}
8050
8051
8052
8053
8054
8055
8056
8057static void hdlcdev_exit(struct mgsl_struct *info)
8058{
8059 unregister_hdlc_device(info->netdev);
8060 free_netdev(info->netdev);
8061 info->netdev = NULL;
8062}
8063
8064#endif
8065
8066
8067static int __devinit synclink_init_one (struct pci_dev *dev,
8068 const struct pci_device_id *ent)
8069{
8070 struct mgsl_struct *info;
8071
8072 if (pci_enable_device(dev)) {
8073 printk("error enabling pci device %p\n", dev);
8074 return -EIO;
8075 }
8076
8077 if (!(info = mgsl_allocate_device())) {
8078 printk("can't allocate device instance data.\n");
8079 return -EIO;
8080 }
8081
8082
8083
8084 info->io_base = pci_resource_start(dev, 2);
8085 info->irq_level = dev->irq;
8086 info->phys_memory_base = pci_resource_start(dev, 3);
8087
8088
8089
8090
8091
8092 info->phys_lcr_base = pci_resource_start(dev, 0);
8093 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8094 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8095
8096 info->bus_type = MGSL_BUS_TYPE_PCI;
8097 info->io_addr_size = 8;
8098 info->irq_flags = IRQF_SHARED;
8099
8100 if (dev->device == 0x0210) {
8101
8102 info->misc_ctrl_value = 0x007c4080;
8103 info->hw_version = 1;
8104 } else {
8105
8106
8107
8108
8109
8110 info->misc_ctrl_value = 0x087e4546;
8111 info->hw_version = 0;
8112 }
8113
8114 mgsl_add_device(info);
8115
8116 return 0;
8117}
8118
8119static void __devexit synclink_remove_one (struct pci_dev *dev)
8120{
8121}
8122
8123