LXR linux/drivers/dma/at_hdmac

   1/*
   2 * Header file for the Atmel AHB DMA Controller driver
   3 *
   4 * Copyright (C) 2008 Atmel Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 */
  11#ifndef AT_HDMAC_REGS_H
  12#define AT_HDMAC_REGS_H
  13
  14#include <mach/at_hdmac.h>
  15
  16#define AT_DMA_MAX_NR_CHANNELS  8
  17
  18
  19#define AT_DMA_GCFG     0x00    /* Global Configuration Register */
  20#define         AT_DMA_IF_BIGEND(i)     (0x1 << (i))    /* AHB-Lite Interface i in Big-endian mode */
  21#define         AT_DMA_ARB_CFG  (0x1 << 4)      /* Arbiter mode. */
  22#define                 AT_DMA_ARB_CFG_FIXED            (0x0 << 4)
  23#define                 AT_DMA_ARB_CFG_ROUND_ROBIN      (0x1 << 4)
  24
  25#define AT_DMA_EN       0x04    /* Controller Enable Register */
  26#define         AT_DMA_ENABLE   (0x1 << 0)
  27
  28#define AT_DMA_SREQ     0x08    /* Software Single Request Register */
  29#define         AT_DMA_SSREQ(x) (0x1 << ((x) << 1))             /* Request a source single transfer on channel x */
  30#define         AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1)))       /* Request a destination single transfer on channel x */
  31
  32#define AT_DMA_CREQ     0x0C    /* Software Chunk Transfer Request Register */
  33#define         AT_DMA_SCREQ(x) (0x1 << ((x) << 1))             /* Request a source chunk transfer on channel x */
  34#define         AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1)))       /* Request a destination chunk transfer on channel x */
  35
  36#define AT_DMA_LAST     0x10    /* Software Last Transfer Flag Register */
  37#define         AT_DMA_SLAST(x) (0x1 << ((x) << 1))             /* This src rq is last tx of buffer on channel x */
  38#define         AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1)))       /* This dst rq is last tx of buffer on channel x */
  39
  40#define AT_DMA_SYNC     0x14    /* Request Synchronization Register */
  41#define         AT_DMA_SYR(h)   (0x1 << (h))                    /* Synchronize handshake line h */
  42
  43/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
  44#define AT_DMA_EBCIER   0x18    /* Enable register */
  45#define AT_DMA_EBCIDR   0x1C    /* Disable register */
  46#define AT_DMA_EBCIMR   0x20    /* Mask Register */
  47#define AT_DMA_EBCISR   0x24    /* Status Register */
  48#define         AT_DMA_CBTC_OFFSET      8
  49#define         AT_DMA_ERR_OFFSET       16
  50#define         AT_DMA_BTC(x)   (0x1 << (x))
  51#define         AT_DMA_CBTC(x)  (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
  52#define         AT_DMA_ERR(x)   (0x1 << (AT_DMA_ERR_OFFSET + (x)))
  53
  54#define AT_DMA_CHER     0x28    /* Channel Handler Enable Register */
  55#define         AT_DMA_ENA(x)   (0x1 << (x))
  56#define         AT_DMA_SUSP(x)  (0x1 << ( 8 + (x)))
  57#define         AT_DMA_KEEP(x)  (0x1 << (24 + (x)))
  58
  59#define AT_DMA_CHDR     0x2C    /* Channel Handler Disable Register */
  60#define         AT_DMA_DIS(x)   (0x1 << (x))
  61#define         AT_DMA_RES(x)   (0x1 << ( 8 + (x)))
  62
  63#define AT_DMA_CHSR     0x30    /* Channel Handler Status Register */
  64#define         AT_DMA_EMPT(x)  (0x1 << (16 + (x)))
  65#define         AT_DMA_STAL(x)  (0x1 << (24 + (x)))
  66
  67
  68#define AT_DMA_CH_REGS_BASE     0x3C    /* Channel registers base address */
  69#define ch_regs(x)      (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
  70
  71/* Hardware register offset for each channel */
  72#define ATC_SADDR_OFFSET        0x00    /* Source Address Register */
  73#define ATC_DADDR_OFFSET        0x04    /* Destination Address Register */
  74#define ATC_DSCR_OFFSET         0x08    /* Descriptor Address Register */
  75#define ATC_CTRLA_OFFSET        0x0C    /* Control A Register */
  76#define ATC_CTRLB_OFFSET        0x10    /* Control B Register */
  77#define ATC_CFG_OFFSET          0x14    /* Configuration Register */
  78#define ATC_SPIP_OFFSET         0x18    /* Src PIP Configuration Register */
  79#define ATC_DPIP_OFFSET         0x1C    /* Dst PIP Configuration Register */
  80
  81
  82/* Bitfield definitions */
  83
  84/* Bitfields in DSCR */
  85#define ATC_DSCR_IF(i)          (0x3 & (i))     /* Dsc feched via AHB-Lite Interface i */
  86
  87/* Bitfields in CTRLA */
  88#define ATC_BTSIZE_MAX          0xFFFFUL        /* Maximum Buffer Transfer Size */
  89#define ATC_BTSIZE(x)           (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
  90/* Chunck Tranfer size definitions are in at_hdmac.h */
  91#define ATC_SRC_WIDTH_MASK      (0x3 << 24)     /* Source Single Transfer Size */
  92#define         ATC_SRC_WIDTH(x)        ((x) << 24)
  93#define         ATC_SRC_WIDTH_BYTE      (0x0 << 24)
  94#define         ATC_SRC_WIDTH_HALFWORD  (0x1 << 24)
  95#define         ATC_SRC_WIDTH_WORD      (0x2 << 24)
  96#define ATC_DST_WIDTH_MASK      (0x3 << 28)     /* Destination Single Transfer Size */
  97#define         ATC_DST_WIDTH(x)        ((x) << 28)
  98#define         ATC_DST_WIDTH_BYTE      (0x0 << 28)
  99#define         ATC_DST_WIDTH_HALFWORD  (0x1 << 28)
 100#define         ATC_DST_WIDTH_WORD      (0x2 << 28)
 101#define ATC_DONE                (0x1 << 31)     /* Tx Done (only written back in descriptor) */
 102
 103/* Bitfields in CTRLB */
 104#define ATC_SIF(i)              (0x3 & (i))     /* Src tx done via AHB-Lite Interface i */
 105#define ATC_DIF(i)              ((0x3 & (i)) <<  4)     /* Dst tx done via AHB-Lite Interface i */
 106#define ATC_SRC_PIP             (0x1 <<  8)     /* Source Picture-in-Picture enabled */
 107#define ATC_DST_PIP             (0x1 << 12)     /* Destination Picture-in-Picture enabled */
 108#define ATC_SRC_DSCR_DIS        (0x1 << 16)     /* Src Descriptor fetch disable */
 109#define ATC_DST_DSCR_DIS        (0x1 << 20)     /* Dst Descriptor fetch disable */
 110#define ATC_FC_MASK             (0x7 << 21)     /* Choose Flow Controller */
 111#define         ATC_FC_MEM2MEM          (0x0 << 21)     /* Mem-to-Mem (DMA) */
 112#define         ATC_FC_MEM2PER          (0x1 << 21)     /* Mem-to-Periph (DMA) */
 113#define         ATC_FC_PER2MEM          (0x2 << 21)     /* Periph-to-Mem (DMA) */
 114#define         ATC_FC_PER2PER          (0x3 << 21)     /* Periph-to-Periph (DMA) */
 115#define         ATC_FC_PER2MEM_PER      (0x4 << 21)     /* Periph-to-Mem (Peripheral) */
 116#define         ATC_FC_MEM2PER_PER      (0x5 << 21)     /* Mem-to-Periph (Peripheral) */
 117#define         ATC_FC_PER2PER_SRCPER   (0x6 << 21)     /* Periph-to-Periph (Src Peripheral) */
 118#define         ATC_FC_PER2PER_DSTPER   (0x7 << 21)     /* Periph-to-Periph (Dst Peripheral) */
 119#define ATC_SRC_ADDR_MODE_MASK  (0x3 << 24)
 120#define         ATC_SRC_ADDR_MODE_INCR  (0x0 << 24)     /* Incrementing Mode */
 121#define         ATC_SRC_ADDR_MODE_DECR  (0x1 << 24)     /* Decrementing Mode */
 122#define         ATC_SRC_ADDR_MODE_FIXED (0x2 << 24)     /* Fixed Mode */
 123#define ATC_DST_ADDR_MODE_MASK  (0x3 << 28)
 124#define         ATC_DST_ADDR_MODE_INCR  (0x0 << 28)     /* Incrementing Mode */
 125#define         ATC_DST_ADDR_MODE_DECR  (0x1 << 28)     /* Decrementing Mode */
 126#define         ATC_DST_ADDR_MODE_FIXED (0x2 << 28)     /* Fixed Mode */
 127#define ATC_IEN                 (0x1 << 30)     /* BTC interrupt enable (active low) */
 128#define ATC_AUTO                (0x1 << 31)     /* Auto multiple buffer tx enable */
 129
 130/* Bitfields in CFG */
 131/* are in at_hdmac.h */
 132
 133/* Bitfields in SPIP */
 134#define ATC_SPIP_HOLE(x)        (0xFFFFU & (x))
 135#define ATC_SPIP_BOUNDARY(x)    ((0x3FF & (x)) << 16)
 136
 137/* Bitfields in DPIP */
 138#define ATC_DPIP_HOLE(x)        (0xFFFFU & (x))
 139#define ATC_DPIP_BOUNDARY(x)    ((0x3FF & (x)) << 16)
 140
 141
 142/*--  descriptors  -----------------------------------------------------*/
 143
 144/* LLI == Linked List Item; aka DMA buffer descriptor */
 145struct at_lli {
 146        /* values that are not changed by hardware */
 147        dma_addr_t      saddr;
 148        dma_addr_t      daddr;
 149        /* value that may get written back: */
 150        u32             ctrla;
 151        /* more values that are not changed by hardware */
 152        u32             ctrlb;
 153        dma_addr_t      dscr;   /* chain to next lli */
 154};
 155
 156/**
 157 * struct at_desc - software descriptor
 158 * @at_lli: hardware lli structure
 159 * @txd: support for the async_tx api
 160 * @desc_node: node on the channed descriptors list
 161 * @len: total transaction bytecount
 162 */
 163struct at_desc {
 164        /* FIRST values the hardware uses */
 165        struct at_lli                   lli;
 166
 167        /* THEN values for driver housekeeping */
 168        struct list_head                tx_list;
 169        struct dma_async_tx_descriptor  txd;
 170        struct list_head                desc_node;
 171        size_t                          len;
 172};
 173
 174static inline struct at_desc *
 175txd_to_at_desc(struct dma_async_tx_descriptor *txd)
 176{
 177        return container_of(txd, struct at_desc, txd);
 178}
 179
 180
 181/*--  Channels  --------------------------------------------------------*/
 182
 183/**
 184 * struct at_dma_chan - internal representation of an Atmel HDMAC channel
 185 * @chan_common: common dmaengine channel object members
 186 * @device: parent device
 187 * @ch_regs: memory mapped register base
 188 * @mask: channel index in a mask
 189 * @error_status: transmit error status information from irq handler
 190 *                to tasklet (use atomic operations)
 191 * @tasklet: bottom half to finish transaction work
 192 * @lock: serializes enqueue/dequeue operations to descriptors lists
 193 * @completed_cookie: identifier for the most recently completed operation
 194 * @active_list: list of descriptors dmaengine is being running on
 195 * @queue: list of descriptors ready to be submitted to engine
 196 * @free_list: list of descriptors usable by the channel
 197 * @descs_allocated: records the actual size of the descriptor pool
 198 */
 199struct at_dma_chan {
 200        struct dma_chan         chan_common;
 201        struct at_dma           *device;
 202        void __iomem            *ch_regs;
 203        u8                      mask;
 204        unsigned long           error_status;
 205        struct tasklet_struct   tasklet;
 206
 207        spinlock_t              lock;
 208
 209        /* these other elements are all protected by lock */
 210        dma_cookie_t            completed_cookie;
 211        struct list_head        active_list;
 212        struct list_head        queue;
 213        struct list_head        free_list;
 214        unsigned int            descs_allocated;
 215};
 216
 217#define channel_readl(atchan, name) \
 218        __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
 219
 220#define channel_writel(atchan, name, val) \
 221        __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
 222
 223static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
 224{
 225        return container_of(dchan, struct at_dma_chan, chan_common);
 226}
 227
 228
 229/*--  Controller  ------------------------------------------------------*/
 230
 231/**
 232 * struct at_dma - internal representation of an Atmel HDMA Controller
 233 * @chan_common: common dmaengine dma_device object members
 234 * @ch_regs: memory mapped register base
 235 * @clk: dma controller clock
 236 * @all_chan_mask: all channels availlable in a mask
 237 * @dma_desc_pool: base of DMA descriptor region (DMA address)
 238 * @chan: channels table to store at_dma_chan structures
 239 */
 240struct at_dma {
 241        struct dma_device       dma_common;
 242        void __iomem            *regs;
 243        struct clk              *clk;
 244
 245        u8                      all_chan_mask;
 246
 247        struct dma_pool         *dma_desc_pool;
 248        /* AT THE END channels table */
 249        struct at_dma_chan      chan[0];
 250};
 251
 252#define dma_readl(atdma, name) \
 253        __raw_readl((atdma)->regs + AT_DMA_##name)
 254#define dma_writel(atdma, name, val) \
 255        __raw_writel((val), (atdma)->regs + AT_DMA_##name)
 256
 257static inline struct at_dma *to_at_dma(struct dma_device *ddev)
 258{
 259        return container_of(ddev, struct at_dma, dma_common);
 260}
 261
 262
 263/*--  Helper functions  ------------------------------------------------*/
 264
 265static struct device *chan2dev(struct dma_chan *chan)
 266{
 267        return &chan->dev->device;
 268}
 269static struct device *chan2parent(struct dma_chan *chan)
 270{
 271        return chan->dev->device.parent;
 272}
 273
 274#if defined(VERBOSE_DEBUG)
 275static void vdbg_dump_regs(struct at_dma_chan *atchan)
 276{
 277        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
 278
 279        dev_err(chan2dev(&atchan->chan_common),
 280                "  channel %d : imr = 0x%x, chsr = 0x%x\n",
 281                atchan->chan_common.chan_id,
 282                dma_readl(atdma, EBCIMR),
 283                dma_readl(atdma, CHSR));
 284
 285        dev_err(chan2dev(&atchan->chan_common),
 286                "  channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
 287                channel_readl(atchan, SADDR),
 288                channel_readl(atchan, DADDR),
 289                channel_readl(atchan, CTRLA),
 290                channel_readl(atchan, CTRLB),
 291                channel_readl(atchan, CFG),
 292                channel_readl(atchan, DSCR));
 293}
 294#else
 295static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
 296#endif
 297
 298static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
 299{
 300        dev_printk(KERN_CRIT, chan2dev(&atchan->chan_common),
 301                        "  desc: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
 302                        lli->saddr, lli->daddr,
 303                        lli->ctrla, lli->ctrlb, lli->dscr);
 304}
 305
 306
 307static void atc_setup_irq(struct at_dma_chan *atchan, int on)
 308{
 309        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
 310        u32             ebci;
 311
 312        /* enable interrupts on buffer chain completion & error */
 313        ebci =    AT_DMA_CBTC(atchan->chan_common.chan_id)
 314                | AT_DMA_ERR(atchan->chan_common.chan_id);
 315        if (on)
 316                dma_writel(atdma, EBCIER, ebci);
 317        else
 318                dma_writel(atdma, EBCIDR, ebci);
 319}
 320
 321static inline void atc_enable_irq(struct at_dma_chan *atchan)
 322{
 323        atc_setup_irq(atchan, 1);
 324}
 325
 326static inline void atc_disable_irq(struct at_dma_chan *atchan)
 327{
 328        atc_setup_irq(atchan, 0);
 329}
 330
 331
 332/**
 333 * atc_chan_is_enabled - test if given channel is enabled
 334 * @atchan: channel we want to test status
 335 */
 336static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
 337{
 338        struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
 339
 340        return !!(dma_readl(atdma, CHSR) & atchan->mask);
 341}
 342
 343
 344/**
 345 * set_desc_eol - set end-of-link to descriptor so it will end transfer
 346 * @desc: descriptor, signle or at the end of a chain, to end chain on
 347 */
 348static void set_desc_eol(struct at_desc *desc)
 349{
 350        desc->lli.ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
 351        desc->lli.dscr = 0;
 352}
 353
 354#endif /* AT_HDMAC_REGS_H */
 355