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17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/pci_ids.h>
21#include <linux/slab.h>
22#include <linux/edac.h>
23#include <asm/mmzone.h>
24
25#include "edac_core.h"
26
27
28
29
30#define I5000_REVISION " Ver: 2.0.12 " __DATE__
31#define EDAC_MOD_STR "i5000_edac"
32
33#define i5000_printk(level, fmt, arg...) \
34 edac_printk(level, "i5000", fmt, ##arg)
35
36#define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
38
39#ifndef PCI_DEVICE_ID_INTEL_FBD_0
40#define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
41#endif
42#ifndef PCI_DEVICE_ID_INTEL_FBD_1
43#define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
44#endif
45
46
47
48
49
50
51
52
53#define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
54
55
56
57
58#define AMBASE 0x48
59#define MAXCH 0x56
60#define MAXDIMMPERCH 0x57
61#define TOLM 0x6C
62#define REDMEMB 0x7C
63#define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
64#define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
66#define MIR0 0x80
67#define MIR1 0x84
68#define MIR2 0x88
69#define AMIR0 0x8C
70#define AMIR1 0x90
71#define AMIR2 0x94
72
73#define FERR_FAT_FBD 0x98
74#define NERR_FAT_FBD 0x9C
75#define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76#define FERR_FAT_FBDCHAN 0x30000000
77#define FERR_FAT_M3ERR 0x00000004
78#define FERR_FAT_M2ERR 0x00000002
79#define FERR_FAT_M1ERR 0x00000001
80#define FERR_FAT_MASK (FERR_FAT_M1ERR | \
81 FERR_FAT_M2ERR | \
82 FERR_FAT_M3ERR)
83
84#define FERR_NF_FBD 0xA0
85
86
87#define FERR_NF_M28ERR 0x01000000
88#define FERR_NF_M27ERR 0x00800000
89#define FERR_NF_M26ERR 0x00400000
90#define FERR_NF_M25ERR 0x00200000
91#define FERR_NF_M24ERR 0x00100000
92#define FERR_NF_M23ERR 0x00080000
93#define FERR_NF_M22ERR 0x00040000
94#define FERR_NF_M21ERR 0x00020000
95
96
97#define FERR_NF_M20ERR 0x00010000
98#define FERR_NF_M19ERR 0x00008000
99#define FERR_NF_M18ERR 0x00004000
100#define FERR_NF_M17ERR 0x00002000
101
102
103#define FERR_NF_M16ERR 0x00001000
104#define FERR_NF_M15ERR 0x00000800
105#define FERR_NF_M14ERR 0x00000400
106#define FERR_NF_M13ERR 0x00000200
107
108
109#define FERR_NF_M12ERR 0x00000100
110#define FERR_NF_M11ERR 0x00000080
111#define FERR_NF_M10ERR 0x00000040
112#define FERR_NF_M9ERR 0x00000020
113#define FERR_NF_M8ERR 0x00000010
114#define FERR_NF_M7ERR 0x00000008
115#define FERR_NF_M6ERR 0x00000004
116#define FERR_NF_M5ERR 0x00000002
117#define FERR_NF_M4ERR 0x00000001
118
119#define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
120 FERR_NF_M11ERR | \
121 FERR_NF_M10ERR | \
122 FERR_NF_M9ERR | \
123 FERR_NF_M8ERR | \
124 FERR_NF_M7ERR | \
125 FERR_NF_M6ERR | \
126 FERR_NF_M5ERR | \
127 FERR_NF_M4ERR)
128#define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
129 FERR_NF_M19ERR | \
130 FERR_NF_M18ERR | \
131 FERR_NF_M17ERR)
132#define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
133 FERR_NF_M28ERR)
134#define FERR_NF_THERMAL (FERR_NF_M26ERR | \
135 FERR_NF_M25ERR | \
136 FERR_NF_M24ERR | \
137 FERR_NF_M23ERR)
138#define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
139#define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
140#define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
141 FERR_NF_M14ERR | \
142 FERR_NF_M15ERR)
143
144#define NERR_NF_FBD 0xA4
145#define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
146 FERR_NF_CORRECTABLE | \
147 FERR_NF_DIMM_SPARE | \
148 FERR_NF_THERMAL | \
149 FERR_NF_SPD_PROTOCOL | \
150 FERR_NF_NORTH_CRC | \
151 FERR_NF_NON_RETRY)
152
153#define EMASK_FBD 0xA8
154#define EMASK_FBD_M28ERR 0x08000000
155#define EMASK_FBD_M27ERR 0x04000000
156#define EMASK_FBD_M26ERR 0x02000000
157#define EMASK_FBD_M25ERR 0x01000000
158#define EMASK_FBD_M24ERR 0x00800000
159#define EMASK_FBD_M23ERR 0x00400000
160#define EMASK_FBD_M22ERR 0x00200000
161#define EMASK_FBD_M21ERR 0x00100000
162#define EMASK_FBD_M20ERR 0x00080000
163#define EMASK_FBD_M19ERR 0x00040000
164#define EMASK_FBD_M18ERR 0x00020000
165#define EMASK_FBD_M17ERR 0x00010000
166
167#define EMASK_FBD_M15ERR 0x00004000
168#define EMASK_FBD_M14ERR 0x00002000
169#define EMASK_FBD_M13ERR 0x00001000
170#define EMASK_FBD_M12ERR 0x00000800
171#define EMASK_FBD_M11ERR 0x00000400
172#define EMASK_FBD_M10ERR 0x00000200
173#define EMASK_FBD_M9ERR 0x00000100
174#define EMASK_FBD_M8ERR 0x00000080
175#define EMASK_FBD_M7ERR 0x00000040
176#define EMASK_FBD_M6ERR 0x00000020
177#define EMASK_FBD_M5ERR 0x00000010
178#define EMASK_FBD_M4ERR 0x00000008
179#define EMASK_FBD_M3ERR 0x00000004
180#define EMASK_FBD_M2ERR 0x00000002
181#define EMASK_FBD_M1ERR 0x00000001
182
183#define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
184 EMASK_FBD_M2ERR | \
185 EMASK_FBD_M3ERR)
186
187#define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
188 EMASK_FBD_M5ERR | \
189 EMASK_FBD_M6ERR | \
190 EMASK_FBD_M7ERR | \
191 EMASK_FBD_M8ERR | \
192 EMASK_FBD_M9ERR | \
193 EMASK_FBD_M10ERR | \
194 EMASK_FBD_M11ERR | \
195 EMASK_FBD_M12ERR)
196#define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
197 EMASK_FBD_M18ERR | \
198 EMASK_FBD_M19ERR | \
199 EMASK_FBD_M20ERR)
200#define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
201 EMASK_FBD_M28ERR)
202#define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
203 EMASK_FBD_M25ERR | \
204 EMASK_FBD_M24ERR | \
205 EMASK_FBD_M23ERR)
206#define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
207#define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
208#define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
209 EMASK_FBD_M14ERR | \
210 EMASK_FBD_M13ERR)
211
212#define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
213 ENABLE_EMASK_FBD_NORTH_CRC | \
214 ENABLE_EMASK_FBD_SPD_PROTOCOL | \
215 ENABLE_EMASK_FBD_THERMALS | \
216 ENABLE_EMASK_FBD_DIMM_SPARE | \
217 ENABLE_EMASK_FBD_FATAL_ERRORS | \
218 ENABLE_EMASK_FBD_CORRECTABLE | \
219 ENABLE_EMASK_FBD_UNCORRECTABLE)
220
221#define ERR0_FBD 0xAC
222#define ERR1_FBD 0xB0
223#define ERR2_FBD 0xB4
224#define MCERR_FBD 0xB8
225#define NRECMEMA 0xBE
226#define NREC_BANK(x) (((x)>>12) & 0x7)
227#define NREC_RDWR(x) (((x)>>11) & 1)
228#define NREC_RANK(x) (((x)>>8) & 0x7)
229#define NRECMEMB 0xC0
230#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF)
231#define NREC_RAS(x) ((x) & 0x7FFF)
232#define NRECFGLOG 0xC4
233#define NREEECFBDA 0xC8
234#define NREEECFBDB 0xCC
235#define NREEECFBDC 0xD0
236#define NREEECFBDD 0xD4
237#define NREEECFBDE 0xD8
238#define REDMEMA 0xDC
239#define RECMEMA 0xE2
240#define REC_BANK(x) (((x)>>12) & 0x7)
241#define REC_RDWR(x) (((x)>>11) & 1)
242#define REC_RANK(x) (((x)>>8) & 0x7)
243#define RECMEMB 0xE4
244#define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
245#define REC_RAS(x) ((x) & 0x7FFF)
246#define RECFGLOG 0xE8
247#define RECFBDA 0xEC
248#define RECFBDB 0xF0
249#define RECFBDC 0xF4
250#define RECFBDD 0xF8
251#define RECFBDE 0xFC
252
253
254
255
256
257
258
259
260
261
262#define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
263#define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
264
265#define AMB_PRESENT_0 0x64
266#define AMB_PRESENT_1 0x66
267#define MTR0 0x80
268#define MTR1 0x84
269#define MTR2 0x88
270#define MTR3 0x8C
271
272#define NUM_MTRS 4
273#define CHANNELS_PER_BRANCH (2)
274
275
276
277
278#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
279#define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
280#define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
281#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
282#define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
283#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
284#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
285#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
286#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
287#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
288
289#ifdef CONFIG_EDAC_DEBUG
290static char *numrow_toString[] = {
291 "8,192 - 13 rows",
292 "16,384 - 14 rows",
293 "32,768 - 15 rows",
294 "reserved"
295};
296
297static char *numcol_toString[] = {
298 "1,024 - 10 columns",
299 "2,048 - 11 columns",
300 "4,096 - 12 columns",
301 "reserved"
302};
303#endif
304
305
306static int misc_messages;
307
308
309enum i5000_chips {
310 I5000P = 0,
311 I5000V = 1,
312 I5000X = 2
313};
314
315
316struct i5000_dev_info {
317 const char *ctl_name;
318 u16 fsb_mapping_errors;
319};
320
321
322static const struct i5000_dev_info i5000_devs[] = {
323 [I5000P] = {
324 .ctl_name = "I5000",
325 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
326 },
327};
328
329struct i5000_dimm_info {
330 int megabytes;
331 int dual_rank;
332};
333
334#define MAX_CHANNELS 6
335#define MAX_CSROWS (8*2)
336
337
338struct i5000_pvt {
339 struct pci_dev *system_address;
340 struct pci_dev *branchmap_werrors;
341 struct pci_dev *fsb_error_regs;
342 struct pci_dev *branch_0;
343 struct pci_dev *branch_1;
344
345 u16 tolm;
346 u64 ambase;
347
348 u16 mir0, mir1, mir2;
349
350 u16 b0_mtr[NUM_MTRS];
351 u16 b0_ambpresent0;
352 u16 b0_ambpresent1;
353
354 u16 b1_mtr[NUM_MTRS];
355 u16 b1_ambpresent0;
356 u16 b1_ambpresent1;
357
358
359 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
360
361
362 int maxch;
363 int maxdimmperch;
364};
365
366
367struct i5000_error_info {
368
369
370 u32 ferr_fat_fbd;
371 u32 nerr_fat_fbd;
372 u32 ferr_nf_fbd;
373 u32 nerr_nf_fbd;
374
375
376 u32 redmemb;
377 u16 recmema;
378 u32 recmemb;
379
380
381
382 u16 nrecmema;
383 u16 nrecmemb;
384
385};
386
387static struct edac_pci_ctl_info *i5000_pci;
388
389
390
391
392
393
394static void i5000_get_error_info(struct mem_ctl_info *mci,
395 struct i5000_error_info *info)
396{
397 struct i5000_pvt *pvt;
398 u32 value;
399
400 pvt = mci->pvt_info;
401
402
403 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
404
405
406
407 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
408
409
410
411 if (value & FERR_FAT_MASK) {
412 info->ferr_fat_fbd = value;
413
414
415 pci_read_config_dword(pvt->branchmap_werrors,
416 NERR_FAT_FBD, &info->nerr_fat_fbd);
417 pci_read_config_word(pvt->branchmap_werrors,
418 NRECMEMA, &info->nrecmema);
419 pci_read_config_word(pvt->branchmap_werrors,
420 NRECMEMB, &info->nrecmemb);
421
422
423 pci_write_config_dword(pvt->branchmap_werrors,
424 FERR_FAT_FBD, value);
425 } else {
426 info->ferr_fat_fbd = 0;
427 info->nerr_fat_fbd = 0;
428 info->nrecmema = 0;
429 info->nrecmemb = 0;
430 }
431
432
433 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
434
435
436
437 if (value & FERR_NF_MASK) {
438 info->ferr_nf_fbd = value;
439
440
441 pci_read_config_dword(pvt->branchmap_werrors,
442 NERR_NF_FBD, &info->nerr_nf_fbd);
443 pci_read_config_word(pvt->branchmap_werrors,
444 RECMEMA, &info->recmema);
445 pci_read_config_dword(pvt->branchmap_werrors,
446 RECMEMB, &info->recmemb);
447 pci_read_config_dword(pvt->branchmap_werrors,
448 REDMEMB, &info->redmemb);
449
450
451 pci_write_config_dword(pvt->branchmap_werrors,
452 FERR_NF_FBD, value);
453 } else {
454 info->ferr_nf_fbd = 0;
455 info->nerr_nf_fbd = 0;
456 info->recmema = 0;
457 info->recmemb = 0;
458 info->redmemb = 0;
459 }
460}
461
462
463
464
465
466
467
468
469static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
470 struct i5000_error_info *info,
471 int handle_errors)
472{
473 char msg[EDAC_MC_LABEL_LEN + 1 + 160];
474 char *specific = NULL;
475 u32 allErrors;
476 int branch;
477 int channel;
478 int bank;
479 int rank;
480 int rdwr;
481 int ras, cas;
482
483
484 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
485 if (!allErrors)
486 return;
487
488 branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
489 channel = branch;
490
491
492 bank = NREC_BANK(info->nrecmema);
493 rank = NREC_RANK(info->nrecmema);
494 rdwr = NREC_RDWR(info->nrecmema);
495 ras = NREC_RAS(info->nrecmemb);
496 cas = NREC_CAS(info->nrecmemb);
497
498 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
499 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
500 rank, channel, channel + 1, branch >> 1, bank,
501 rdwr ? "Write" : "Read", ras, cas);
502
503
504 switch (allErrors) {
505 case FERR_FAT_M1ERR:
506 specific = "Alert on non-redundant retry or fast "
507 "reset timeout";
508 break;
509 case FERR_FAT_M2ERR:
510 specific = "Northbound CRC error on non-redundant "
511 "retry";
512 break;
513 case FERR_FAT_M3ERR:
514 {
515 static int done;
516
517
518
519
520
521
522
523
524 if (done)
525 return;
526 done++;
527
528 specific = ">Tmid Thermal event with intelligent "
529 "throttling disabled";
530 }
531 break;
532 }
533
534
535 snprintf(msg, sizeof(msg),
536 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d "
537 "FATAL Err=0x%x (%s))",
538 branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
539 allErrors, specific);
540
541
542 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
543}
544
545
546
547
548
549
550
551
552static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
553 struct i5000_error_info *info,
554 int handle_errors)
555{
556 char msg[EDAC_MC_LABEL_LEN + 1 + 170];
557 char *specific = NULL;
558 u32 allErrors;
559 u32 ue_errors;
560 u32 ce_errors;
561 u32 misc_errors;
562 int branch;
563 int channel;
564 int bank;
565 int rank;
566 int rdwr;
567 int ras, cas;
568
569
570 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
571 if (!allErrors)
572 return;
573
574
575 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
576 if (ue_errors) {
577 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
578
579 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
580 channel = branch;
581 bank = NREC_BANK(info->nrecmema);
582 rank = NREC_RANK(info->nrecmema);
583 rdwr = NREC_RDWR(info->nrecmema);
584 ras = NREC_RAS(info->nrecmemb);
585 cas = NREC_CAS(info->nrecmemb);
586
587 debugf0
588 ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
589 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
590 rank, channel, channel + 1, branch >> 1, bank,
591 rdwr ? "Write" : "Read", ras, cas);
592
593 switch (ue_errors) {
594 case FERR_NF_M12ERR:
595 specific = "Non-Aliased Uncorrectable Patrol Data ECC";
596 break;
597 case FERR_NF_M11ERR:
598 specific = "Non-Aliased Uncorrectable Spare-Copy "
599 "Data ECC";
600 break;
601 case FERR_NF_M10ERR:
602 specific = "Non-Aliased Uncorrectable Mirrored Demand "
603 "Data ECC";
604 break;
605 case FERR_NF_M9ERR:
606 specific = "Non-Aliased Uncorrectable Non-Mirrored "
607 "Demand Data ECC";
608 break;
609 case FERR_NF_M8ERR:
610 specific = "Aliased Uncorrectable Patrol Data ECC";
611 break;
612 case FERR_NF_M7ERR:
613 specific = "Aliased Uncorrectable Spare-Copy Data ECC";
614 break;
615 case FERR_NF_M6ERR:
616 specific = "Aliased Uncorrectable Mirrored Demand "
617 "Data ECC";
618 break;
619 case FERR_NF_M5ERR:
620 specific = "Aliased Uncorrectable Non-Mirrored Demand "
621 "Data ECC";
622 break;
623 case FERR_NF_M4ERR:
624 specific = "Uncorrectable Data ECC on Replay";
625 break;
626 }
627
628
629 snprintf(msg, sizeof(msg),
630 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
631 "CAS=%d, UE Err=0x%x (%s))",
632 branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
633 ue_errors, specific);
634
635
636 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
637 }
638
639
640 ce_errors = allErrors & FERR_NF_CORRECTABLE;
641 if (ce_errors) {
642 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
643
644 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
645
646 channel = 0;
647 if (REC_ECC_LOCATOR_ODD(info->redmemb))
648 channel = 1;
649
650
651
652 channel += branch;
653
654 bank = REC_BANK(info->recmema);
655 rank = REC_RANK(info->recmema);
656 rdwr = REC_RDWR(info->recmema);
657 ras = REC_RAS(info->recmemb);
658 cas = REC_CAS(info->recmemb);
659
660 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
661 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
662 rank, channel, branch >> 1, bank,
663 rdwr ? "Write" : "Read", ras, cas);
664
665 switch (ce_errors) {
666 case FERR_NF_M17ERR:
667 specific = "Correctable Non-Mirrored Demand Data ECC";
668 break;
669 case FERR_NF_M18ERR:
670 specific = "Correctable Mirrored Demand Data ECC";
671 break;
672 case FERR_NF_M19ERR:
673 specific = "Correctable Spare-Copy Data ECC";
674 break;
675 case FERR_NF_M20ERR:
676 specific = "Correctable Patrol Data ECC";
677 break;
678 }
679
680
681 snprintf(msg, sizeof(msg),
682 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
683 "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
684 rdwr ? "Write" : "Read", ras, cas, ce_errors,
685 specific);
686
687
688 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
689 }
690
691 if (!misc_messages)
692 return;
693
694 misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
695 FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
696 if (misc_errors) {
697 switch (misc_errors) {
698 case FERR_NF_M13ERR:
699 specific = "Non-Retry or Redundant Retry FBD Memory "
700 "Alert or Redundant Fast Reset Timeout";
701 break;
702 case FERR_NF_M14ERR:
703 specific = "Non-Retry or Redundant Retry FBD "
704 "Configuration Alert";
705 break;
706 case FERR_NF_M15ERR:
707 specific = "Non-Retry or Redundant Retry FBD "
708 "Northbound CRC error on read data";
709 break;
710 case FERR_NF_M21ERR:
711 specific = "FBD Northbound CRC error on "
712 "FBD Sync Status";
713 break;
714 case FERR_NF_M22ERR:
715 specific = "SPD protocol error";
716 break;
717 case FERR_NF_M27ERR:
718 specific = "DIMM-spare copy started";
719 break;
720 case FERR_NF_M28ERR:
721 specific = "DIMM-spare copy completed";
722 break;
723 }
724 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
725
726
727 snprintf(msg, sizeof(msg),
728 "(Branch=%d Err=%#x (%s))", branch >> 1,
729 misc_errors, specific);
730
731
732 edac_mc_handle_fbd_ce(mci, 0, 0, msg);
733 }
734}
735
736
737
738
739
740static void i5000_process_error_info(struct mem_ctl_info *mci,
741 struct i5000_error_info *info,
742 int handle_errors)
743{
744
745 i5000_process_fatal_error_info(mci, info, handle_errors);
746
747
748 i5000_process_nonfatal_error_info(mci, info, handle_errors);
749}
750
751
752
753
754
755
756
757static void i5000_clear_error(struct mem_ctl_info *mci)
758{
759 struct i5000_error_info info;
760
761 i5000_get_error_info(mci, &info);
762}
763
764
765
766
767
768static void i5000_check_error(struct mem_ctl_info *mci)
769{
770 struct i5000_error_info info;
771 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
772 i5000_get_error_info(mci, &info);
773 i5000_process_error_info(mci, &info, 1);
774}
775
776
777
778
779
780
781
782static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
783{
784
785 struct i5000_pvt *pvt;
786 struct pci_dev *pdev;
787
788 pvt = mci->pvt_info;
789
790
791 pdev = NULL;
792 while (1) {
793 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
794 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
795
796
797 if (pdev == NULL) {
798 i5000_printk(KERN_ERR,
799 "'system address,Process Bus' "
800 "device not found:"
801 "vendor 0x%x device 0x%x FUNC 1 "
802 "(broken BIOS?)\n",
803 PCI_VENDOR_ID_INTEL,
804 PCI_DEVICE_ID_INTEL_I5000_DEV16);
805
806 return 1;
807 }
808
809
810 if (PCI_FUNC(pdev->devfn) == 1)
811 break;
812 }
813
814 pvt->branchmap_werrors = pdev;
815
816
817 pdev = NULL;
818 while (1) {
819 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
820 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
821
822 if (pdev == NULL) {
823 i5000_printk(KERN_ERR,
824 "MC: 'branchmap,control,errors' "
825 "device not found:"
826 "vendor 0x%x device 0x%x Func 2 "
827 "(broken BIOS?)\n",
828 PCI_VENDOR_ID_INTEL,
829 PCI_DEVICE_ID_INTEL_I5000_DEV16);
830
831 pci_dev_put(pvt->branchmap_werrors);
832 return 1;
833 }
834
835
836 if (PCI_FUNC(pdev->devfn) == 2)
837 break;
838 }
839
840 pvt->fsb_error_regs = pdev;
841
842 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
843 pci_name(pvt->system_address),
844 pvt->system_address->vendor, pvt->system_address->device);
845 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
846 pci_name(pvt->branchmap_werrors),
847 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
848 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
849 pci_name(pvt->fsb_error_regs),
850 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
851
852 pdev = NULL;
853 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
854 PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
855
856 if (pdev == NULL) {
857 i5000_printk(KERN_ERR,
858 "MC: 'BRANCH 0' device not found:"
859 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
860 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
861
862 pci_dev_put(pvt->branchmap_werrors);
863 pci_dev_put(pvt->fsb_error_regs);
864 return 1;
865 }
866
867 pvt->branch_0 = pdev;
868
869
870
871
872 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
873 pdev = NULL;
874 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
875 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
876
877 if (pdev == NULL) {
878 i5000_printk(KERN_ERR,
879 "MC: 'BRANCH 1' device not found:"
880 "vendor 0x%x device 0x%x Func 0 "
881 "(broken BIOS?)\n",
882 PCI_VENDOR_ID_INTEL,
883 PCI_DEVICE_ID_I5000_BRANCH_1);
884
885 pci_dev_put(pvt->branchmap_werrors);
886 pci_dev_put(pvt->fsb_error_regs);
887 pci_dev_put(pvt->branch_0);
888 return 1;
889 }
890
891 pvt->branch_1 = pdev;
892 }
893
894 return 0;
895}
896
897
898
899
900
901static void i5000_put_devices(struct mem_ctl_info *mci)
902{
903 struct i5000_pvt *pvt;
904
905 pvt = mci->pvt_info;
906
907 pci_dev_put(pvt->branchmap_werrors);
908 pci_dev_put(pvt->fsb_error_regs);
909 pci_dev_put(pvt->branch_0);
910
911
912 if (pvt->maxch >= CHANNELS_PER_BRANCH)
913 pci_dev_put(pvt->branch_1);
914}
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
930{
931 int amb_present;
932
933 if (channel < CHANNELS_PER_BRANCH) {
934 if (channel & 0x1)
935 amb_present = pvt->b0_ambpresent1;
936 else
937 amb_present = pvt->b0_ambpresent0;
938 } else {
939 if (channel & 0x1)
940 amb_present = pvt->b1_ambpresent1;
941 else
942 amb_present = pvt->b1_ambpresent0;
943 }
944
945 return amb_present;
946}
947
948
949
950
951
952
953static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
954{
955 int mtr;
956
957 if (channel < CHANNELS_PER_BRANCH)
958 mtr = pvt->b0_mtr[csrow >> 1];
959 else
960 mtr = pvt->b1_mtr[csrow >> 1];
961
962 return mtr;
963}
964
965
966
967static void decode_mtr(int slot_row, u16 mtr)
968{
969 int ans;
970
971 ans = MTR_DIMMS_PRESENT(mtr);
972
973 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
974 ans ? "Present" : "NOT Present");
975 if (!ans)
976 return;
977
978 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
979 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
980 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
981 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
982 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
983}
984
985static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
986 struct i5000_dimm_info *dinfo)
987{
988 int mtr;
989 int amb_present_reg;
990 int addrBits;
991
992 mtr = determine_mtr(pvt, csrow, channel);
993 if (MTR_DIMMS_PRESENT(mtr)) {
994 amb_present_reg = determine_amb_present_reg(pvt, channel);
995
996
997 if (amb_present_reg & (1 << (csrow >> 1))) {
998 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
999
1000 if (!((dinfo->dual_rank == 0) &&
1001 ((csrow & 0x1) == 0x1))) {
1002
1003
1004 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1005
1006 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1007
1008 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1009
1010 addrBits += 6;
1011 addrBits -= 20;
1012 addrBits -= 3;
1013
1014 dinfo->megabytes = 1 << addrBits;
1015 }
1016 }
1017 }
1018}
1019
1020
1021
1022
1023
1024
1025
1026static void calculate_dimm_size(struct i5000_pvt *pvt)
1027{
1028 struct i5000_dimm_info *dinfo;
1029 int csrow, max_csrows;
1030 char *p, *mem_buffer;
1031 int space, n;
1032 int channel;
1033
1034
1035 space = PAGE_SIZE;
1036 mem_buffer = p = kmalloc(space, GFP_KERNEL);
1037 if (p == NULL) {
1038 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
1039 __FILE__, __func__);
1040 return;
1041 }
1042
1043 n = snprintf(p, space, "\n");
1044 p += n;
1045 space -= n;
1046
1047
1048
1049
1050
1051
1052 max_csrows = pvt->maxdimmperch * 2;
1053 for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
1054
1055
1056
1057 if (csrow & 0x1) {
1058 n = snprintf(p, space, "---------------------------"
1059 "--------------------------------");
1060 p += n;
1061 space -= n;
1062 debugf2("%s\n", mem_buffer);
1063 p = mem_buffer;
1064 space = PAGE_SIZE;
1065 }
1066 n = snprintf(p, space, "csrow %2d ", csrow);
1067 p += n;
1068 space -= n;
1069
1070 for (channel = 0; channel < pvt->maxch; channel++) {
1071 dinfo = &pvt->dimm_info[csrow][channel];
1072 handle_channel(pvt, csrow, channel, dinfo);
1073 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
1074 p += n;
1075 space -= n;
1076 }
1077 n = snprintf(p, space, "\n");
1078 p += n;
1079 space -= n;
1080 }
1081
1082
1083 n = snprintf(p, space, "---------------------------"
1084 "--------------------------------\n");
1085 p += n;
1086 space -= n;
1087
1088
1089 n = snprintf(p, space, " ");
1090 p += n;
1091 space -= n;
1092 for (channel = 0; channel < pvt->maxch; channel++) {
1093 n = snprintf(p, space, "channel %d | ", channel);
1094 p += n;
1095 space -= n;
1096 }
1097 n = snprintf(p, space, "\n");
1098 p += n;
1099 space -= n;
1100
1101
1102 debugf2("%s\n", mem_buffer);
1103 kfree(mem_buffer);
1104}
1105
1106
1107
1108
1109
1110
1111
1112static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1113{
1114 struct i5000_pvt *pvt;
1115 u32 actual_tolm;
1116 u16 limit;
1117 int slot_row;
1118 int maxch;
1119 int maxdimmperch;
1120 int way0, way1;
1121
1122 pvt = mci->pvt_info;
1123
1124 pci_read_config_dword(pvt->system_address, AMBASE,
1125 (u32 *) & pvt->ambase);
1126 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1127 ((u32 *) & pvt->ambase) + sizeof(u32));
1128
1129 maxdimmperch = pvt->maxdimmperch;
1130 maxch = pvt->maxch;
1131
1132 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1133 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1134
1135
1136 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1137 pvt->tolm >>= 12;
1138 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1139 pvt->tolm);
1140
1141 actual_tolm = pvt->tolm << 28;
1142 debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1143
1144 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1145 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1146 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1147
1148
1149 limit = (pvt->mir0 >> 4) & 0x0FFF;
1150 way0 = pvt->mir0 & 0x1;
1151 way1 = pvt->mir0 & 0x2;
1152 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1153 limit = (pvt->mir1 >> 4) & 0x0FFF;
1154 way0 = pvt->mir1 & 0x1;
1155 way1 = pvt->mir1 & 0x2;
1156 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1157 limit = (pvt->mir2 >> 4) & 0x0FFF;
1158 way0 = pvt->mir2 & 0x1;
1159 way1 = pvt->mir2 & 0x2;
1160 debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1161
1162
1163 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1164 int where = MTR0 + (slot_row * sizeof(u32));
1165
1166 pci_read_config_word(pvt->branch_0, where,
1167 &pvt->b0_mtr[slot_row]);
1168
1169 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1170 pvt->b0_mtr[slot_row]);
1171
1172 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1173 pci_read_config_word(pvt->branch_1, where,
1174 &pvt->b1_mtr[slot_row]);
1175 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1176 where, pvt->b1_mtr[slot_row]);
1177 } else {
1178 pvt->b1_mtr[slot_row] = 0;
1179 }
1180 }
1181
1182
1183 debugf2("\nMemory Technology Registers:\n");
1184 debugf2(" Branch 0:\n");
1185 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1186 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1187 }
1188 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1189 &pvt->b0_ambpresent0);
1190 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1191 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1192 &pvt->b0_ambpresent1);
1193 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1194
1195
1196 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1197 pvt->b1_ambpresent0 = 0;
1198 pvt->b1_ambpresent1 = 0;
1199 } else {
1200
1201 debugf2(" Branch 1:\n");
1202 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1203 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1204 }
1205 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1206 &pvt->b1_ambpresent0);
1207 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1208 pvt->b1_ambpresent0);
1209 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1210 &pvt->b1_ambpresent1);
1211 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1212 pvt->b1_ambpresent1);
1213 }
1214
1215
1216
1217 calculate_dimm_size(pvt);
1218}
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229static int i5000_init_csrows(struct mem_ctl_info *mci)
1230{
1231 struct i5000_pvt *pvt;
1232 struct csrow_info *p_csrow;
1233 int empty, channel_count;
1234 int max_csrows;
1235 int mtr, mtr1;
1236 int csrow_megs;
1237 int channel;
1238 int csrow;
1239
1240 pvt = mci->pvt_info;
1241
1242 channel_count = pvt->maxch;
1243 max_csrows = pvt->maxdimmperch * 2;
1244
1245 empty = 1;
1246
1247 for (csrow = 0; csrow < max_csrows; csrow++) {
1248 p_csrow = &mci->csrows[csrow];
1249
1250 p_csrow->csrow_idx = csrow;
1251
1252
1253 mtr = pvt->b0_mtr[csrow >> 1];
1254 mtr1 = pvt->b1_mtr[csrow >> 1];
1255
1256
1257 if (!MTR_DIMMS_PRESENT(mtr) && !MTR_DIMMS_PRESENT(mtr1))
1258 continue;
1259
1260
1261 p_csrow->first_page = 0 + csrow * 20;
1262 p_csrow->last_page = 9 + csrow * 20;
1263 p_csrow->page_mask = 0xFFF;
1264
1265 p_csrow->grain = 8;
1266
1267 csrow_megs = 0;
1268 for (channel = 0; channel < pvt->maxch; channel++) {
1269 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1270 }
1271
1272 p_csrow->nr_pages = csrow_megs << 8;
1273
1274
1275 p_csrow->mtype = MEM_FB_DDR2;
1276
1277
1278 if (MTR_DRAM_WIDTH(mtr))
1279 p_csrow->dtype = DEV_X8;
1280 else
1281 p_csrow->dtype = DEV_X4;
1282
1283 p_csrow->edac_mode = EDAC_S8ECD8ED;
1284
1285 empty = 0;
1286 }
1287
1288 return empty;
1289}
1290
1291
1292
1293
1294
1295static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1296{
1297 struct i5000_pvt *pvt;
1298 u32 fbd_error_mask;
1299
1300 pvt = mci->pvt_info;
1301
1302
1303 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1304 &fbd_error_mask);
1305
1306
1307 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1308
1309 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1310 fbd_error_mask);
1311}
1312
1313
1314
1315
1316
1317
1318
1319static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1320 int *num_dimms_per_channel,
1321 int *num_channels)
1322{
1323 u8 value;
1324
1325
1326
1327
1328 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1329 *num_dimms_per_channel = (int)value *2;
1330
1331 pci_read_config_byte(pdev, MAXCH, &value);
1332 *num_channels = (int)value;
1333}
1334
1335
1336
1337
1338
1339
1340
1341
1342static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1343{
1344 struct mem_ctl_info *mci;
1345 struct i5000_pvt *pvt;
1346 int num_channels;
1347 int num_dimms_per_channel;
1348 int num_csrows;
1349
1350 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1351 __func__,
1352 pdev->bus->number,
1353 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1354
1355
1356 if (PCI_FUNC(pdev->devfn) != 0)
1357 return -ENODEV;
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1373 &num_channels);
1374 num_csrows = num_dimms_per_channel * 2;
1375
1376 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1377 __func__, num_channels, num_dimms_per_channel, num_csrows);
1378
1379
1380 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1381
1382 if (mci == NULL)
1383 return -ENOMEM;
1384
1385 kobject_get(&mci->edac_mci_kobj);
1386 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1387
1388 mci->dev = &pdev->dev;
1389
1390 pvt = mci->pvt_info;
1391 pvt->system_address = pdev;
1392 pvt->maxch = num_channels;
1393 pvt->maxdimmperch = num_dimms_per_channel;
1394
1395
1396 if (i5000_get_devices(mci, dev_idx))
1397 goto fail0;
1398
1399
1400 i5000_get_mc_regs(mci);
1401
1402 mci->mc_idx = 0;
1403 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1404 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1405 mci->edac_cap = EDAC_FLAG_NONE;
1406 mci->mod_name = "i5000_edac.c";
1407 mci->mod_ver = I5000_REVISION;
1408 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1409 mci->dev_name = pci_name(pdev);
1410 mci->ctl_page_to_phys = NULL;
1411
1412
1413 mci->edac_check = i5000_check_error;
1414
1415
1416
1417 if (i5000_init_csrows(mci)) {
1418 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1419 " because i5000_init_csrows() returned nonzero "
1420 "value\n");
1421 mci->edac_cap = EDAC_FLAG_NONE;
1422 } else {
1423 debugf1("MC: Enable error reporting now\n");
1424 i5000_enable_error_reporting(mci);
1425 }
1426
1427
1428 if (edac_mc_add_mc(mci)) {
1429 debugf0("MC: " __FILE__
1430 ": %s(): failed edac_mc_add_mc()\n", __func__);
1431
1432
1433
1434 goto fail1;
1435 }
1436
1437 i5000_clear_error(mci);
1438
1439
1440 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1441 if (!i5000_pci) {
1442 printk(KERN_WARNING
1443 "%s(): Unable to create PCI control\n",
1444 __func__);
1445 printk(KERN_WARNING
1446 "%s(): PCI error report via EDAC not setup\n",
1447 __func__);
1448 }
1449
1450 return 0;
1451
1452
1453fail1:
1454
1455 i5000_put_devices(mci);
1456
1457fail0:
1458 kobject_put(&mci->edac_mci_kobj);
1459 edac_mc_free(mci);
1460 return -ENODEV;
1461}
1462
1463
1464
1465
1466
1467
1468
1469
1470static int __devinit i5000_init_one(struct pci_dev *pdev,
1471 const struct pci_device_id *id)
1472{
1473 int rc;
1474
1475 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1476
1477
1478 rc = pci_enable_device(pdev);
1479 if (rc == -EIO)
1480 return rc;
1481
1482
1483 return i5000_probe1(pdev, id->driver_data);
1484}
1485
1486
1487
1488
1489
1490static void __devexit i5000_remove_one(struct pci_dev *pdev)
1491{
1492 struct mem_ctl_info *mci;
1493
1494 debugf0(__FILE__ ": %s()\n", __func__);
1495
1496 if (i5000_pci)
1497 edac_pci_release_generic_ctl(i5000_pci);
1498
1499 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1500 return;
1501
1502
1503 i5000_put_devices(mci);
1504 kobject_put(&mci->edac_mci_kobj);
1505 edac_mc_free(mci);
1506}
1507
1508
1509
1510
1511
1512
1513static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
1514 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1515 .driver_data = I5000P},
1516
1517 {0,}
1518};
1519
1520MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1521
1522
1523
1524
1525
1526static struct pci_driver i5000_driver = {
1527 .name = KBUILD_BASENAME,
1528 .probe = i5000_init_one,
1529 .remove = __devexit_p(i5000_remove_one),
1530 .id_table = i5000_pci_tbl,
1531};
1532
1533
1534
1535
1536
1537static int __init i5000_init(void)
1538{
1539 int pci_rc;
1540
1541 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1542
1543
1544 opstate_init();
1545
1546 pci_rc = pci_register_driver(&i5000_driver);
1547
1548 return (pci_rc < 0) ? pci_rc : 0;
1549}
1550
1551
1552
1553
1554
1555static void __exit i5000_exit(void)
1556{
1557 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1558 pci_unregister_driver(&i5000_driver);
1559}
1560
1561module_init(i5000_init);
1562module_exit(i5000_exit);
1563
1564MODULE_LICENSE("GPL");
1565MODULE_AUTHOR
1566 ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1567MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1568 I5000_REVISION);
1569
1570module_param(edac_op_state, int, 0444);
1571MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1572module_param(misc_messages, int, 0444);
1573MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1574
1575
