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16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/pci_ids.h>
20#include <linux/slab.h>
21#include <linux/edac.h>
22#include "edac_core.h"
23
24#define I82875P_REVISION " Ver: 2.0.2 " __DATE__
25#define EDAC_MOD_STR "i82875p_edac"
26
27#define i82875p_printk(level, fmt, arg...) \
28 edac_printk(level, "i82875p", fmt, ##arg)
29
30#define i82875p_mc_printk(mci, level, fmt, arg...) \
31 edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
32
33#ifndef PCI_DEVICE_ID_INTEL_82875_0
34#define PCI_DEVICE_ID_INTEL_82875_0 0x2578
35#endif
36
37#ifndef PCI_DEVICE_ID_INTEL_82875_6
38#define PCI_DEVICE_ID_INTEL_82875_6 0x257e
39#endif
40
41
42#define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
43
44
45#define I82875P_EAP 0x58
46
47
48
49
50
51#define I82875P_DERRSYN 0x5c
52
53
54
55
56#define I82875P_DES 0x5d
57
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61
62#define I82875P_ERRSTS 0xc8
63
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76
77#define I82875P_ERRCMD 0xca
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92
93#define I82875P_PCICMD6 0x04
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107
108#define I82875P_BAR6 0x10
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118
119#define I82875P_DRB_SHIFT 26
120#define I82875P_DRB 0x00
121
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124
125
126#define I82875P_DRA 0x10
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138
139#define I82875P_DRC 0x68
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153
154
155enum i82875p_chips {
156 I82875P = 0,
157};
158
159struct i82875p_pvt {
160 struct pci_dev *ovrfl_pdev;
161 void __iomem *ovrfl_window;
162};
163
164struct i82875p_dev_info {
165 const char *ctl_name;
166};
167
168struct i82875p_error_info {
169 u16 errsts;
170 u32 eap;
171 u8 des;
172 u8 derrsyn;
173 u16 errsts2;
174};
175
176static const struct i82875p_dev_info i82875p_devs[] = {
177 [I82875P] = {
178 .ctl_name = "i82875p"},
179};
180
181static struct pci_dev *mci_pdev;
182
183
184
185static struct edac_pci_ctl_info *i82875p_pci;
186
187static void i82875p_get_error_info(struct mem_ctl_info *mci,
188 struct i82875p_error_info *info)
189{
190 struct pci_dev *pdev;
191
192 pdev = to_pci_dev(mci->dev);
193
194
195
196
197
198
199 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
200
201 if (!(info->errsts & 0x0081))
202 return;
203
204 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
205 pci_read_config_byte(pdev, I82875P_DES, &info->des);
206 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
207 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
208
209
210
211
212
213
214
215 if ((info->errsts ^ info->errsts2) & 0x0081) {
216 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
217 pci_read_config_byte(pdev, I82875P_DES, &info->des);
218 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
219 }
220
221 pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
222}
223
224static int i82875p_process_error_info(struct mem_ctl_info *mci,
225 struct i82875p_error_info *info,
226 int handle_errors)
227{
228 int row, multi_chan;
229
230 multi_chan = mci->csrows[0].nr_channels - 1;
231
232 if (!(info->errsts & 0x0081))
233 return 0;
234
235 if (!handle_errors)
236 return 1;
237
238 if ((info->errsts ^ info->errsts2) & 0x0081) {
239 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
240 info->errsts = info->errsts2;
241 }
242
243 info->eap >>= PAGE_SHIFT;
244 row = edac_mc_find_csrow_by_page(mci, info->eap);
245
246 if (info->errsts & 0x0080)
247 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
248 else
249 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
250 multi_chan ? (info->des & 0x1) : 0,
251 "i82875p CE");
252
253 return 1;
254}
255
256static void i82875p_check(struct mem_ctl_info *mci)
257{
258 struct i82875p_error_info info;
259
260 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
261 i82875p_get_error_info(mci, &info);
262 i82875p_process_error_info(mci, &info, 1);
263}
264
265
266static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
267 struct pci_dev **ovrfl_pdev,
268 void __iomem **ovrfl_window)
269{
270 struct pci_dev *dev;
271 void __iomem *window;
272 int err;
273
274 *ovrfl_pdev = NULL;
275 *ovrfl_window = NULL;
276 dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
277
278 if (dev == NULL) {
279
280
281
282
283
284 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
285 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
286
287 if (dev == NULL)
288 return 1;
289
290 err = pci_bus_add_device(dev);
291 if (err) {
292 i82875p_printk(KERN_ERR,
293 "%s(): pci_bus_add_device() Failed\n",
294 __func__);
295 }
296 pci_bus_assign_resources(dev->bus);
297 }
298
299 *ovrfl_pdev = dev;
300
301 if (pci_enable_device(dev)) {
302 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
303 "device\n", __func__);
304 return 1;
305 }
306
307 if (pci_request_regions(dev, pci_name(dev))) {
308#ifdef CORRECT_BIOS
309 goto fail0;
310#endif
311 }
312
313
314 window = pci_ioremap_bar(dev, 0);
315 if (window == NULL) {
316 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
317 __func__);
318 goto fail1;
319 }
320
321 *ovrfl_window = window;
322 return 0;
323
324fail1:
325 pci_release_regions(dev);
326
327#ifdef CORRECT_BIOS
328fail0:
329 pci_disable_device(dev);
330#endif
331
332 return 1;
333}
334
335
336static inline int dual_channel_active(u32 drc)
337{
338 return (drc >> 21) & 0x1;
339}
340
341static void i82875p_init_csrows(struct mem_ctl_info *mci,
342 struct pci_dev *pdev,
343 void __iomem * ovrfl_window, u32 drc)
344{
345 struct csrow_info *csrow;
346 unsigned long last_cumul_size;
347 u8 value;
348 u32 drc_ddim;
349 u32 cumul_size;
350 int index;
351
352 drc_ddim = (drc >> 18) & 0x1;
353 last_cumul_size = 0;
354
355
356
357
358
359
360
361 for (index = 0; index < mci->nr_csrows; index++) {
362 csrow = &mci->csrows[index];
363
364 value = readb(ovrfl_window + I82875P_DRB + index);
365 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
366 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
367 cumul_size);
368 if (cumul_size == last_cumul_size)
369 continue;
370
371 csrow->first_page = last_cumul_size;
372 csrow->last_page = cumul_size - 1;
373 csrow->nr_pages = cumul_size - last_cumul_size;
374 last_cumul_size = cumul_size;
375 csrow->grain = 1 << 12;
376 csrow->mtype = MEM_DDR;
377 csrow->dtype = DEV_UNKNOWN;
378 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
379 }
380}
381
382static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
383{
384 int rc = -ENODEV;
385 struct mem_ctl_info *mci;
386 struct i82875p_pvt *pvt;
387 struct pci_dev *ovrfl_pdev;
388 void __iomem *ovrfl_window;
389 u32 drc;
390 u32 nr_chans;
391 struct i82875p_error_info discard;
392
393 debugf0("%s()\n", __func__);
394
395 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
396
397 if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
398 return -ENODEV;
399 drc = readl(ovrfl_window + I82875P_DRC);
400 nr_chans = dual_channel_active(drc) + 1;
401 mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
402 nr_chans, 0);
403
404 if (!mci) {
405 rc = -ENOMEM;
406 goto fail0;
407 }
408
409
410 kobject_get(&mci->edac_mci_kobj);
411
412 debugf3("%s(): init mci\n", __func__);
413 mci->dev = &pdev->dev;
414 mci->mtype_cap = MEM_FLAG_DDR;
415 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
416 mci->edac_cap = EDAC_FLAG_UNKNOWN;
417 mci->mod_name = EDAC_MOD_STR;
418 mci->mod_ver = I82875P_REVISION;
419 mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
420 mci->dev_name = pci_name(pdev);
421 mci->edac_check = i82875p_check;
422 mci->ctl_page_to_phys = NULL;
423 debugf3("%s(): init pvt\n", __func__);
424 pvt = (struct i82875p_pvt *)mci->pvt_info;
425 pvt->ovrfl_pdev = ovrfl_pdev;
426 pvt->ovrfl_window = ovrfl_window;
427 i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
428 i82875p_get_error_info(mci, &discard);
429
430
431
432
433 if (edac_mc_add_mc(mci)) {
434 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
435 goto fail1;
436 }
437
438
439 i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
440 if (!i82875p_pci) {
441 printk(KERN_WARNING
442 "%s(): Unable to create PCI control\n",
443 __func__);
444 printk(KERN_WARNING
445 "%s(): PCI error report via EDAC not setup\n",
446 __func__);
447 }
448
449
450 debugf3("%s(): success\n", __func__);
451 return 0;
452
453fail1:
454 kobject_put(&mci->edac_mci_kobj);
455 edac_mc_free(mci);
456
457fail0:
458 iounmap(ovrfl_window);
459 pci_release_regions(ovrfl_pdev);
460
461 pci_disable_device(ovrfl_pdev);
462
463 return rc;
464}
465
466
467static int __devinit i82875p_init_one(struct pci_dev *pdev,
468 const struct pci_device_id *ent)
469{
470 int rc;
471
472 debugf0("%s()\n", __func__);
473 i82875p_printk(KERN_INFO, "i82875p init one\n");
474
475 if (pci_enable_device(pdev) < 0)
476 return -EIO;
477
478 rc = i82875p_probe1(pdev, ent->driver_data);
479
480 if (mci_pdev == NULL)
481 mci_pdev = pci_dev_get(pdev);
482
483 return rc;
484}
485
486static void __devexit i82875p_remove_one(struct pci_dev *pdev)
487{
488 struct mem_ctl_info *mci;
489 struct i82875p_pvt *pvt = NULL;
490
491 debugf0("%s()\n", __func__);
492
493 if (i82875p_pci)
494 edac_pci_release_generic_ctl(i82875p_pci);
495
496 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
497 return;
498
499 pvt = (struct i82875p_pvt *)mci->pvt_info;
500
501 if (pvt->ovrfl_window)
502 iounmap(pvt->ovrfl_window);
503
504 if (pvt->ovrfl_pdev) {
505#ifdef CORRECT_BIOS
506 pci_release_regions(pvt->ovrfl_pdev);
507#endif
508 pci_disable_device(pvt->ovrfl_pdev);
509 pci_dev_put(pvt->ovrfl_pdev);
510 }
511
512 edac_mc_free(mci);
513}
514
515static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
516 {
517 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
518 I82875P},
519 {
520 0,
521 }
522};
523
524MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
525
526static struct pci_driver i82875p_driver = {
527 .name = EDAC_MOD_STR,
528 .probe = i82875p_init_one,
529 .remove = __devexit_p(i82875p_remove_one),
530 .id_table = i82875p_pci_tbl,
531};
532
533static int __init i82875p_init(void)
534{
535 int pci_rc;
536
537 debugf3("%s()\n", __func__);
538
539
540 opstate_init();
541
542 pci_rc = pci_register_driver(&i82875p_driver);
543
544 if (pci_rc < 0)
545 goto fail0;
546
547 if (mci_pdev == NULL) {
548 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
549 PCI_DEVICE_ID_INTEL_82875_0, NULL);
550
551 if (!mci_pdev) {
552 debugf0("875p pci_get_device fail\n");
553 pci_rc = -ENODEV;
554 goto fail1;
555 }
556
557 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
558
559 if (pci_rc < 0) {
560 debugf0("875p init fail\n");
561 pci_rc = -ENODEV;
562 goto fail1;
563 }
564 }
565
566 return 0;
567
568fail1:
569 pci_unregister_driver(&i82875p_driver);
570
571fail0:
572 if (mci_pdev != NULL)
573 pci_dev_put(mci_pdev);
574
575 return pci_rc;
576}
577
578static void __exit i82875p_exit(void)
579{
580 debugf3("%s()\n", __func__);
581
582 i82875p_remove_one(mci_pdev);
583 pci_dev_put(mci_pdev);
584
585 pci_unregister_driver(&i82875p_driver);
586
587}
588
589module_init(i82875p_init);
590module_exit(i82875p_exit);
591
592MODULE_LICENSE("GPL");
593MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
594MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
595
596module_param(edac_op_state, int, 0444);
597MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
598