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21#include <linux/compiler.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/firewire.h>
26#include <linux/firewire-constants.h>
27#include <linux/gfp.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/mm.h>
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/pci.h>
37#include <linux/pci_ids.h>
38#include <linux/spinlock.h>
39#include <linux/string.h>
40
41#include <asm/atomic.h>
42#include <asm/byteorder.h>
43#include <asm/page.h>
44#include <asm/system.h>
45
46#ifdef CONFIG_PPC_PMAC
47#include <asm/pmac_feature.h>
48#endif
49
50#include "core.h"
51#include "ohci.h"
52
53#define DESCRIPTOR_OUTPUT_MORE 0
54#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55#define DESCRIPTOR_INPUT_MORE (2 << 12)
56#define DESCRIPTOR_INPUT_LAST (3 << 12)
57#define DESCRIPTOR_STATUS (1 << 11)
58#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59#define DESCRIPTOR_PING (1 << 7)
60#define DESCRIPTOR_YY (1 << 6)
61#define DESCRIPTOR_NO_IRQ (0 << 4)
62#define DESCRIPTOR_IRQ_ERROR (1 << 4)
63#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65#define DESCRIPTOR_WAIT (3 << 0)
66
67struct descriptor {
68 __le16 req_count;
69 __le16 control;
70 __le32 data_address;
71 __le32 branch_address;
72 __le16 res_count;
73 __le16 transfer_status;
74} __attribute__((aligned(16)));
75
76struct db_descriptor {
77 __le16 first_size;
78 __le16 control;
79 __le16 second_req_count;
80 __le16 first_req_count;
81 __le32 branch_address;
82 __le16 second_res_count;
83 __le16 first_res_count;
84 __le32 reserved0;
85 __le32 first_buffer;
86 __le32 second_buffer;
87 __le32 reserved1;
88} __attribute__((aligned(16)));
89
90#define CONTROL_SET(regs) (regs)
91#define CONTROL_CLEAR(regs) ((regs) + 4)
92#define COMMAND_PTR(regs) ((regs) + 12)
93#define CONTEXT_MATCH(regs) ((regs) + 16)
94
95struct ar_buffer {
96 struct descriptor descriptor;
97 struct ar_buffer *next;
98 __le32 data[0];
99};
100
101struct ar_context {
102 struct fw_ohci *ohci;
103 struct ar_buffer *current_buffer;
104 struct ar_buffer *last_buffer;
105 void *pointer;
106 u32 regs;
107 struct tasklet_struct tasklet;
108};
109
110struct context;
111
112typedef int (*descriptor_callback_t)(struct context *ctx,
113 struct descriptor *d,
114 struct descriptor *last);
115
116
117
118
119
120struct descriptor_buffer {
121 struct list_head list;
122 dma_addr_t buffer_bus;
123 size_t buffer_size;
124 size_t used;
125 struct descriptor buffer[0];
126};
127
128struct context {
129 struct fw_ohci *ohci;
130 u32 regs;
131 int total_allocation;
132
133
134
135
136
137
138 struct list_head buffer_list;
139
140
141
142
143
144 struct descriptor_buffer *buffer_tail;
145
146
147
148
149
150 struct descriptor *last;
151
152
153
154
155
156 struct descriptor *prev;
157
158 descriptor_callback_t callback;
159
160 struct tasklet_struct tasklet;
161};
162
163#define IT_HEADER_SY(v) ((v) << 0)
164#define IT_HEADER_TCODE(v) ((v) << 4)
165#define IT_HEADER_CHANNEL(v) ((v) << 8)
166#define IT_HEADER_TAG(v) ((v) << 14)
167#define IT_HEADER_SPEED(v) ((v) << 16)
168#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170struct iso_context {
171 struct fw_iso_context base;
172 struct context context;
173 int excess_bytes;
174 void *header;
175 size_t header_length;
176};
177
178#define CONFIG_ROM_SIZE 1024
179
180struct fw_ohci {
181 struct fw_card card;
182
183 __iomem char *registers;
184 dma_addr_t self_id_bus;
185 __le32 *self_id_cpu;
186 struct tasklet_struct bus_reset_tasklet;
187 int node_id;
188 int generation;
189 int request_generation;
190 atomic_t bus_seconds;
191
192 bool use_dualbuffer;
193 bool old_uninorth;
194 bool bus_reset_packet_quirk;
195
196
197
198
199
200 spinlock_t lock;
201 u32 self_id_buffer[512];
202
203
204 __be32 *config_rom;
205 dma_addr_t config_rom_bus;
206 __be32 *next_config_rom;
207 dma_addr_t next_config_rom_bus;
208 u32 next_header;
209
210 struct ar_context ar_request_ctx;
211 struct ar_context ar_response_ctx;
212 struct context at_request_ctx;
213 struct context at_response_ctx;
214
215 u32 it_context_mask;
216 struct iso_context *it_context_list;
217 u64 ir_context_channels;
218 u32 ir_context_mask;
219 struct iso_context *ir_context_list;
220};
221
222static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223{
224 return container_of(card, struct fw_ohci, card);
225}
226
227#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228#define IR_CONTEXT_BUFFER_FILL 0x80000000
229#define IR_CONTEXT_ISOCH_HEADER 0x40000000
230#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
233
234#define CONTEXT_RUN 0x8000
235#define CONTEXT_WAKE 0x1000
236#define CONTEXT_DEAD 0x0800
237#define CONTEXT_ACTIVE 0x0400
238
239#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
242
243#define OHCI1394_REGISTER_SIZE 0x800
244#define OHCI_LOOP_COUNT 500
245#define OHCI1394_PCI_HCI_Control 0x40
246#define SELF_ID_BUF_SIZE 0x800
247#define OHCI_TCODE_PHY_PACKET 0x0e
248#define OHCI_VERSION_1_1 0x010010
249
250static char ohci_driver_name[] = KBUILD_MODNAME;
251
252#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
253
254#define OHCI_PARAM_DEBUG_AT_AR 1
255#define OHCI_PARAM_DEBUG_SELFIDS 2
256#define OHCI_PARAM_DEBUG_IRQS 4
257#define OHCI_PARAM_DEBUG_BUSRESETS 8
258
259static int param_debug;
260module_param_named(debug, param_debug, int, 0644);
261MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
262 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
263 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
264 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
265 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266 ", or a combination, or all = -1)");
267
268static void log_irqs(u32 evt)
269{
270 if (likely(!(param_debug &
271 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
272 return;
273
274 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
275 !(evt & OHCI1394_busReset))
276 return;
277
278 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279 evt & OHCI1394_selfIDComplete ? " selfID" : "",
280 evt & OHCI1394_RQPkt ? " AR_req" : "",
281 evt & OHCI1394_RSPkt ? " AR_resp" : "",
282 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
283 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
284 evt & OHCI1394_isochRx ? " IR" : "",
285 evt & OHCI1394_isochTx ? " IT" : "",
286 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
287 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
288 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
289 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
290 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
291 evt & OHCI1394_busReset ? " busReset" : "",
292 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
293 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
294 OHCI1394_respTxComplete | OHCI1394_isochRx |
295 OHCI1394_isochTx | OHCI1394_postedWriteErr |
296 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
297 OHCI1394_cycleInconsistent |
298 OHCI1394_regAccessFail | OHCI1394_busReset)
299 ? " ?" : "");
300}
301
302static const char *speed[] = {
303 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
304};
305static const char *power[] = {
306 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
307 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
308};
309static const char port[] = { '.', '-', 'p', 'c', };
310
311static char _p(u32 *s, int shift)
312{
313 return port[*s >> shift & 3];
314}
315
316static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
317{
318 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
319 return;
320
321 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
322 self_id_count, generation, node_id);
323
324 for (; self_id_count--; ++s)
325 if ((*s & 1 << 23) == 0)
326 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
327 "%s gc=%d %s %s%s%s\n",
328 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
329 speed[*s >> 14 & 3], *s >> 16 & 63,
330 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
331 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
332 else
333 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
334 *s, *s >> 24 & 63,
335 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
336 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
337}
338
339static const char *evts[] = {
340 [0x00] = "evt_no_status", [0x01] = "-reserved-",
341 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
342 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
343 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
344 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
345 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
346 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
347 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
348 [0x10] = "-reserved-", [0x11] = "ack_complete",
349 [0x12] = "ack_pending ", [0x13] = "-reserved-",
350 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
351 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
352 [0x18] = "-reserved-", [0x19] = "-reserved-",
353 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
354 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
355 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
356 [0x20] = "pending/cancelled",
357};
358static const char *tcodes[] = {
359 [0x0] = "QW req", [0x1] = "BW req",
360 [0x2] = "W resp", [0x3] = "-reserved-",
361 [0x4] = "QR req", [0x5] = "BR req",
362 [0x6] = "QR resp", [0x7] = "BR resp",
363 [0x8] = "cycle start", [0x9] = "Lk req",
364 [0xa] = "async stream packet", [0xb] = "Lk resp",
365 [0xc] = "-reserved-", [0xd] = "-reserved-",
366 [0xe] = "link internal", [0xf] = "-reserved-",
367};
368static const char *phys[] = {
369 [0x0] = "phy config packet", [0x1] = "link-on packet",
370 [0x2] = "self-id packet", [0x3] = "-reserved-",
371};
372
373static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
374{
375 int tcode = header[0] >> 4 & 0xf;
376 char specific[12];
377
378 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
379 return;
380
381 if (unlikely(evt >= ARRAY_SIZE(evts)))
382 evt = 0x1f;
383
384 if (evt == OHCI1394_evt_bus_reset) {
385 fw_notify("A%c evt_bus_reset, generation %d\n",
386 dir, (header[2] >> 16) & 0xff);
387 return;
388 }
389
390 if (header[0] == ~header[1]) {
391 fw_notify("A%c %s, %s, %08x\n",
392 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
393 return;
394 }
395
396 switch (tcode) {
397 case 0x0: case 0x6: case 0x8:
398 snprintf(specific, sizeof(specific), " = %08x",
399 be32_to_cpu((__force __be32)header[3]));
400 break;
401 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
402 snprintf(specific, sizeof(specific), " %x,%x",
403 header[3] >> 16, header[3] & 0xffff);
404 break;
405 default:
406 specific[0] = '\0';
407 }
408
409 switch (tcode) {
410 case 0xe: case 0xa:
411 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
412 break;
413 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
414 fw_notify("A%c spd %x tl %02x, "
415 "%04x -> %04x, %s, "
416 "%s, %04x%08x%s\n",
417 dir, speed, header[0] >> 10 & 0x3f,
418 header[1] >> 16, header[0] >> 16, evts[evt],
419 tcodes[tcode], header[1] & 0xffff, header[2], specific);
420 break;
421 default:
422 fw_notify("A%c spd %x tl %02x, "
423 "%04x -> %04x, %s, "
424 "%s%s\n",
425 dir, speed, header[0] >> 10 & 0x3f,
426 header[1] >> 16, header[0] >> 16, evts[evt],
427 tcodes[tcode], specific);
428 }
429}
430
431#else
432
433#define log_irqs(evt)
434#define log_selfids(node_id, generation, self_id_count, sid)
435#define log_ar_at_event(dir, speed, header, evt)
436
437#endif
438
439static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
440{
441 writel(data, ohci->registers + offset);
442}
443
444static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
445{
446 return readl(ohci->registers + offset);
447}
448
449static inline void flush_writes(const struct fw_ohci *ohci)
450{
451
452 reg_read(ohci, OHCI1394_Version);
453}
454
455static int ohci_update_phy_reg(struct fw_card *card, int addr,
456 int clear_bits, int set_bits)
457{
458 struct fw_ohci *ohci = fw_ohci(card);
459 u32 val, old;
460
461 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
462 flush_writes(ohci);
463 msleep(2);
464 val = reg_read(ohci, OHCI1394_PhyControl);
465 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
466 fw_error("failed to set phy reg bits.\n");
467 return -EBUSY;
468 }
469
470 old = OHCI1394_PhyControl_ReadData(val);
471 old = (old & ~clear_bits) | set_bits;
472 reg_write(ohci, OHCI1394_PhyControl,
473 OHCI1394_PhyControl_Write(addr, old));
474
475 return 0;
476}
477
478static int ar_context_add_page(struct ar_context *ctx)
479{
480 struct device *dev = ctx->ohci->card.device;
481 struct ar_buffer *ab;
482 dma_addr_t uninitialized_var(ab_bus);
483 size_t offset;
484
485 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
486 if (ab == NULL)
487 return -ENOMEM;
488
489 ab->next = NULL;
490 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
491 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
492 DESCRIPTOR_STATUS |
493 DESCRIPTOR_BRANCH_ALWAYS);
494 offset = offsetof(struct ar_buffer, data);
495 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
496 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
497 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
498 ab->descriptor.branch_address = 0;
499
500 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
501 ctx->last_buffer->next = ab;
502 ctx->last_buffer = ab;
503
504 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
505 flush_writes(ctx->ohci);
506
507 return 0;
508}
509
510static void ar_context_release(struct ar_context *ctx)
511{
512 struct ar_buffer *ab, *ab_next;
513 size_t offset;
514 dma_addr_t ab_bus;
515
516 for (ab = ctx->current_buffer; ab; ab = ab_next) {
517 ab_next = ab->next;
518 offset = offsetof(struct ar_buffer, data);
519 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
520 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
521 ab, ab_bus);
522 }
523}
524
525#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
526#define cond_le32_to_cpu(v) \
527 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
528#else
529#define cond_le32_to_cpu(v) le32_to_cpu(v)
530#endif
531
532static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
533{
534 struct fw_ohci *ohci = ctx->ohci;
535 struct fw_packet p;
536 u32 status, length, tcode;
537 int evt;
538
539 p.header[0] = cond_le32_to_cpu(buffer[0]);
540 p.header[1] = cond_le32_to_cpu(buffer[1]);
541 p.header[2] = cond_le32_to_cpu(buffer[2]);
542
543 tcode = (p.header[0] >> 4) & 0x0f;
544 switch (tcode) {
545 case TCODE_WRITE_QUADLET_REQUEST:
546 case TCODE_READ_QUADLET_RESPONSE:
547 p.header[3] = (__force __u32) buffer[3];
548 p.header_length = 16;
549 p.payload_length = 0;
550 break;
551
552 case TCODE_READ_BLOCK_REQUEST :
553 p.header[3] = cond_le32_to_cpu(buffer[3]);
554 p.header_length = 16;
555 p.payload_length = 0;
556 break;
557
558 case TCODE_WRITE_BLOCK_REQUEST:
559 case TCODE_READ_BLOCK_RESPONSE:
560 case TCODE_LOCK_REQUEST:
561 case TCODE_LOCK_RESPONSE:
562 p.header[3] = cond_le32_to_cpu(buffer[3]);
563 p.header_length = 16;
564 p.payload_length = p.header[3] >> 16;
565 break;
566
567 case TCODE_WRITE_RESPONSE:
568 case TCODE_READ_QUADLET_REQUEST:
569 case OHCI_TCODE_PHY_PACKET:
570 p.header_length = 12;
571 p.payload_length = 0;
572 break;
573
574 default:
575
576 p.header_length = 0;
577 p.payload_length = 0;
578 }
579
580 p.payload = (void *) buffer + p.header_length;
581
582
583 length = (p.header_length + p.payload_length + 3) / 4;
584 status = cond_le32_to_cpu(buffer[length]);
585 evt = (status >> 16) & 0x1f;
586
587 p.ack = evt - 16;
588 p.speed = (status >> 21) & 0x7;
589 p.timestamp = status & 0xffff;
590 p.generation = ohci->request_generation;
591
592 log_ar_at_event('R', p.speed, p.header, evt);
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607 if (evt == OHCI1394_evt_bus_reset) {
608 if (!ohci->bus_reset_packet_quirk)
609 ohci->request_generation = (p.header[2] >> 16) & 0xff;
610 } else if (ctx == &ohci->ar_request_ctx) {
611 fw_core_handle_request(&ohci->card, &p);
612 } else {
613 fw_core_handle_response(&ohci->card, &p);
614 }
615
616 return buffer + length + 1;
617}
618
619static void ar_context_tasklet(unsigned long data)
620{
621 struct ar_context *ctx = (struct ar_context *)data;
622 struct fw_ohci *ohci = ctx->ohci;
623 struct ar_buffer *ab;
624 struct descriptor *d;
625 void *buffer, *end;
626
627 ab = ctx->current_buffer;
628 d = &ab->descriptor;
629
630 if (d->res_count == 0) {
631 size_t size, rest, offset;
632 dma_addr_t start_bus;
633 void *start;
634
635
636
637
638
639
640
641 offset = offsetof(struct ar_buffer, data);
642 start = buffer = ab;
643 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
644
645 ab = ab->next;
646 d = &ab->descriptor;
647 size = buffer + PAGE_SIZE - ctx->pointer;
648 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
649 memmove(buffer, ctx->pointer, size);
650 memcpy(buffer + size, ab->data, rest);
651 ctx->current_buffer = ab;
652 ctx->pointer = (void *) ab->data + rest;
653 end = buffer + size + rest;
654
655 while (buffer < end)
656 buffer = handle_ar_packet(ctx, buffer);
657
658 dma_free_coherent(ohci->card.device, PAGE_SIZE,
659 start, start_bus);
660 ar_context_add_page(ctx);
661 } else {
662 buffer = ctx->pointer;
663 ctx->pointer = end =
664 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
665
666 while (buffer < end)
667 buffer = handle_ar_packet(ctx, buffer);
668 }
669}
670
671static int ar_context_init(struct ar_context *ctx,
672 struct fw_ohci *ohci, u32 regs)
673{
674 struct ar_buffer ab;
675
676 ctx->regs = regs;
677 ctx->ohci = ohci;
678 ctx->last_buffer = &ab;
679 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
680
681 ar_context_add_page(ctx);
682 ar_context_add_page(ctx);
683 ctx->current_buffer = ab.next;
684 ctx->pointer = ctx->current_buffer->data;
685
686 return 0;
687}
688
689static void ar_context_run(struct ar_context *ctx)
690{
691 struct ar_buffer *ab = ctx->current_buffer;
692 dma_addr_t ab_bus;
693 size_t offset;
694
695 offset = offsetof(struct ar_buffer, data);
696 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
697
698 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
699 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
700 flush_writes(ctx->ohci);
701}
702
703static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
704{
705 int b, key;
706
707 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
708 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
709
710
711 if (z == 2 && (b == 3 || key == 2))
712 return d;
713 else
714 return d + z - 1;
715}
716
717static void context_tasklet(unsigned long data)
718{
719 struct context *ctx = (struct context *) data;
720 struct descriptor *d, *last;
721 u32 address;
722 int z;
723 struct descriptor_buffer *desc;
724
725 desc = list_entry(ctx->buffer_list.next,
726 struct descriptor_buffer, list);
727 last = ctx->last;
728 while (last->branch_address != 0) {
729 struct descriptor_buffer *old_desc = desc;
730 address = le32_to_cpu(last->branch_address);
731 z = address & 0xf;
732 address &= ~0xf;
733
734
735
736 if (address < desc->buffer_bus ||
737 address >= desc->buffer_bus + desc->used)
738 desc = list_entry(desc->list.next,
739 struct descriptor_buffer, list);
740 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
741 last = find_branch_descriptor(d, z);
742
743 if (!ctx->callback(ctx, d, last))
744 break;
745
746 if (old_desc != desc) {
747
748
749 unsigned long flags;
750 old_desc->used = 0;
751 spin_lock_irqsave(&ctx->ohci->lock, flags);
752 list_move_tail(&old_desc->list, &ctx->buffer_list);
753 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
754 }
755 ctx->last = last;
756 }
757}
758
759
760
761
762
763static int context_add_buffer(struct context *ctx)
764{
765 struct descriptor_buffer *desc;
766 dma_addr_t uninitialized_var(bus_addr);
767 int offset;
768
769
770
771
772
773 if (ctx->total_allocation >= 16*1024*1024)
774 return -ENOMEM;
775
776 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
777 &bus_addr, GFP_ATOMIC);
778 if (!desc)
779 return -ENOMEM;
780
781 offset = (void *)&desc->buffer - (void *)desc;
782 desc->buffer_size = PAGE_SIZE - offset;
783 desc->buffer_bus = bus_addr + offset;
784 desc->used = 0;
785
786 list_add_tail(&desc->list, &ctx->buffer_list);
787 ctx->total_allocation += PAGE_SIZE;
788
789 return 0;
790}
791
792static int context_init(struct context *ctx, struct fw_ohci *ohci,
793 u32 regs, descriptor_callback_t callback)
794{
795 ctx->ohci = ohci;
796 ctx->regs = regs;
797 ctx->total_allocation = 0;
798
799 INIT_LIST_HEAD(&ctx->buffer_list);
800 if (context_add_buffer(ctx) < 0)
801 return -ENOMEM;
802
803 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
804 struct descriptor_buffer, list);
805
806 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
807 ctx->callback = callback;
808
809
810
811
812
813
814 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
815 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
816 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
817 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
818 ctx->last = ctx->buffer_tail->buffer;
819 ctx->prev = ctx->buffer_tail->buffer;
820
821 return 0;
822}
823
824static void context_release(struct context *ctx)
825{
826 struct fw_card *card = &ctx->ohci->card;
827 struct descriptor_buffer *desc, *tmp;
828
829 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
830 dma_free_coherent(card->device, PAGE_SIZE, desc,
831 desc->buffer_bus -
832 ((void *)&desc->buffer - (void *)desc));
833}
834
835
836static struct descriptor *context_get_descriptors(struct context *ctx,
837 int z, dma_addr_t *d_bus)
838{
839 struct descriptor *d = NULL;
840 struct descriptor_buffer *desc = ctx->buffer_tail;
841
842 if (z * sizeof(*d) > desc->buffer_size)
843 return NULL;
844
845 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
846
847
848
849 if (desc->list.next == &ctx->buffer_list) {
850
851
852 if (context_add_buffer(ctx) < 0)
853 return NULL;
854 }
855 desc = list_entry(desc->list.next,
856 struct descriptor_buffer, list);
857 ctx->buffer_tail = desc;
858 }
859
860 d = desc->buffer + desc->used / sizeof(*d);
861 memset(d, 0, z * sizeof(*d));
862 *d_bus = desc->buffer_bus + desc->used;
863
864 return d;
865}
866
867static void context_run(struct context *ctx, u32 extra)
868{
869 struct fw_ohci *ohci = ctx->ohci;
870
871 reg_write(ohci, COMMAND_PTR(ctx->regs),
872 le32_to_cpu(ctx->last->branch_address));
873 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
874 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
875 flush_writes(ohci);
876}
877
878static void context_append(struct context *ctx,
879 struct descriptor *d, int z, int extra)
880{
881 dma_addr_t d_bus;
882 struct descriptor_buffer *desc = ctx->buffer_tail;
883
884 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
885
886 desc->used += (z + extra) * sizeof(*d);
887 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
888 ctx->prev = find_branch_descriptor(d, z);
889
890 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
891 flush_writes(ctx->ohci);
892}
893
894static void context_stop(struct context *ctx)
895{
896 u32 reg;
897 int i;
898
899 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
900 flush_writes(ctx->ohci);
901
902 for (i = 0; i < 10; i++) {
903 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
904 if ((reg & CONTEXT_ACTIVE) == 0)
905 return;
906
907 mdelay(1);
908 }
909 fw_error("Error: DMA context still active (0x%08x)\n", reg);
910}
911
912struct driver_data {
913 struct fw_packet *packet;
914};
915
916
917
918
919
920
921static int at_context_queue_packet(struct context *ctx,
922 struct fw_packet *packet)
923{
924 struct fw_ohci *ohci = ctx->ohci;
925 dma_addr_t d_bus, uninitialized_var(payload_bus);
926 struct driver_data *driver_data;
927 struct descriptor *d, *last;
928 __le32 *header;
929 int z, tcode;
930 u32 reg;
931
932 d = context_get_descriptors(ctx, 4, &d_bus);
933 if (d == NULL) {
934 packet->ack = RCODE_SEND_ERROR;
935 return -1;
936 }
937
938 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
939 d[0].res_count = cpu_to_le16(packet->timestamp);
940
941
942
943
944
945
946
947
948 header = (__le32 *) &d[1];
949 switch (packet->header_length) {
950 case 16:
951 case 12:
952 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
953 (packet->speed << 16));
954 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
955 (packet->header[0] & 0xffff0000));
956 header[2] = cpu_to_le32(packet->header[2]);
957
958 tcode = (packet->header[0] >> 4) & 0x0f;
959 if (TCODE_IS_BLOCK_PACKET(tcode))
960 header[3] = cpu_to_le32(packet->header[3]);
961 else
962 header[3] = (__force __le32) packet->header[3];
963
964 d[0].req_count = cpu_to_le16(packet->header_length);
965 break;
966
967 case 8:
968 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
969 (packet->speed << 16));
970 header[1] = cpu_to_le32(packet->header[0]);
971 header[2] = cpu_to_le32(packet->header[1]);
972 d[0].req_count = cpu_to_le16(12);
973 break;
974
975 case 4:
976 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
977 (packet->speed << 16));
978 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
979 d[0].req_count = cpu_to_le16(8);
980 break;
981
982 default:
983
984 packet->ack = RCODE_SEND_ERROR;
985 return -1;
986 }
987
988 driver_data = (struct driver_data *) &d[3];
989 driver_data->packet = packet;
990 packet->driver_data = driver_data;
991
992 if (packet->payload_length > 0) {
993 payload_bus =
994 dma_map_single(ohci->card.device, packet->payload,
995 packet->payload_length, DMA_TO_DEVICE);
996 if (dma_mapping_error(ohci->card.device, payload_bus)) {
997 packet->ack = RCODE_SEND_ERROR;
998 return -1;
999 }
1000 packet->payload_bus = payload_bus;
1001
1002 d[2].req_count = cpu_to_le16(packet->payload_length);
1003 d[2].data_address = cpu_to_le32(payload_bus);
1004 last = &d[2];
1005 z = 3;
1006 } else {
1007 last = &d[0];
1008 z = 2;
1009 }
1010
1011 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1012 DESCRIPTOR_IRQ_ALWAYS |
1013 DESCRIPTOR_BRANCH_ALWAYS);
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026 if (ohci->generation != packet->generation ||
1027 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1028 if (packet->payload_length > 0)
1029 dma_unmap_single(ohci->card.device, payload_bus,
1030 packet->payload_length, DMA_TO_DEVICE);
1031 packet->ack = RCODE_GENERATION;
1032 return -1;
1033 }
1034
1035 context_append(ctx, d, z, 4 - z);
1036
1037
1038 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1039 if ((reg & CONTEXT_RUN) == 0)
1040 context_run(ctx, 0);
1041
1042 return 0;
1043}
1044
1045static int handle_at_packet(struct context *context,
1046 struct descriptor *d,
1047 struct descriptor *last)
1048{
1049 struct driver_data *driver_data;
1050 struct fw_packet *packet;
1051 struct fw_ohci *ohci = context->ohci;
1052 int evt;
1053
1054 if (last->transfer_status == 0)
1055
1056 return 0;
1057
1058 driver_data = (struct driver_data *) &d[3];
1059 packet = driver_data->packet;
1060 if (packet == NULL)
1061
1062 return 1;
1063
1064 if (packet->payload_bus)
1065 dma_unmap_single(ohci->card.device, packet->payload_bus,
1066 packet->payload_length, DMA_TO_DEVICE);
1067
1068 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1069 packet->timestamp = le16_to_cpu(last->res_count);
1070
1071 log_ar_at_event('T', packet->speed, packet->header, evt);
1072
1073 switch (evt) {
1074 case OHCI1394_evt_timeout:
1075
1076 packet->ack = RCODE_CANCELLED;
1077 break;
1078
1079 case OHCI1394_evt_flushed:
1080
1081
1082
1083
1084 packet->ack = RCODE_GENERATION;
1085 break;
1086
1087 case OHCI1394_evt_missing_ack:
1088
1089
1090
1091
1092 packet->ack = RCODE_NO_ACK;
1093 break;
1094
1095 case ACK_COMPLETE + 0x10:
1096 case ACK_PENDING + 0x10:
1097 case ACK_BUSY_X + 0x10:
1098 case ACK_BUSY_A + 0x10:
1099 case ACK_BUSY_B + 0x10:
1100 case ACK_DATA_ERROR + 0x10:
1101 case ACK_TYPE_ERROR + 0x10:
1102 packet->ack = evt - 0x10;
1103 break;
1104
1105 default:
1106 packet->ack = RCODE_SEND_ERROR;
1107 break;
1108 }
1109
1110 packet->callback(packet, &ohci->card, packet->ack);
1111
1112 return 1;
1113}
1114
1115#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1116#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1117#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1118#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1119#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1120
1121static void handle_local_rom(struct fw_ohci *ohci,
1122 struct fw_packet *packet, u32 csr)
1123{
1124 struct fw_packet response;
1125 int tcode, length, i;
1126
1127 tcode = HEADER_GET_TCODE(packet->header[0]);
1128 if (TCODE_IS_BLOCK_PACKET(tcode))
1129 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1130 else
1131 length = 4;
1132
1133 i = csr - CSR_CONFIG_ROM;
1134 if (i + length > CONFIG_ROM_SIZE) {
1135 fw_fill_response(&response, packet->header,
1136 RCODE_ADDRESS_ERROR, NULL, 0);
1137 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1138 fw_fill_response(&response, packet->header,
1139 RCODE_TYPE_ERROR, NULL, 0);
1140 } else {
1141 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1142 (void *) ohci->config_rom + i, length);
1143 }
1144
1145 fw_core_handle_response(&ohci->card, &response);
1146}
1147
1148static void handle_local_lock(struct fw_ohci *ohci,
1149 struct fw_packet *packet, u32 csr)
1150{
1151 struct fw_packet response;
1152 int tcode, length, ext_tcode, sel;
1153 __be32 *payload, lock_old;
1154 u32 lock_arg, lock_data;
1155
1156 tcode = HEADER_GET_TCODE(packet->header[0]);
1157 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1158 payload = packet->payload;
1159 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1160
1161 if (tcode == TCODE_LOCK_REQUEST &&
1162 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1163 lock_arg = be32_to_cpu(payload[0]);
1164 lock_data = be32_to_cpu(payload[1]);
1165 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1166 lock_arg = 0;
1167 lock_data = 0;
1168 } else {
1169 fw_fill_response(&response, packet->header,
1170 RCODE_TYPE_ERROR, NULL, 0);
1171 goto out;
1172 }
1173
1174 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1175 reg_write(ohci, OHCI1394_CSRData, lock_data);
1176 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1177 reg_write(ohci, OHCI1394_CSRControl, sel);
1178
1179 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1180 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1181 else
1182 fw_notify("swap not done yet\n");
1183
1184 fw_fill_response(&response, packet->header,
1185 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1186 out:
1187 fw_core_handle_response(&ohci->card, &response);
1188}
1189
1190static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1191{
1192 u64 offset;
1193 u32 csr;
1194
1195 if (ctx == &ctx->ohci->at_request_ctx) {
1196 packet->ack = ACK_PENDING;
1197 packet->callback(packet, &ctx->ohci->card, packet->ack);
1198 }
1199
1200 offset =
1201 ((unsigned long long)
1202 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1203 packet->header[2];
1204 csr = offset - CSR_REGISTER_BASE;
1205
1206
1207 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1208 handle_local_rom(ctx->ohci, packet, csr);
1209 else switch (csr) {
1210 case CSR_BUS_MANAGER_ID:
1211 case CSR_BANDWIDTH_AVAILABLE:
1212 case CSR_CHANNELS_AVAILABLE_HI:
1213 case CSR_CHANNELS_AVAILABLE_LO:
1214 handle_local_lock(ctx->ohci, packet, csr);
1215 break;
1216 default:
1217 if (ctx == &ctx->ohci->at_request_ctx)
1218 fw_core_handle_request(&ctx->ohci->card, packet);
1219 else
1220 fw_core_handle_response(&ctx->ohci->card, packet);
1221 break;
1222 }
1223
1224 if (ctx == &ctx->ohci->at_response_ctx) {
1225 packet->ack = ACK_COMPLETE;
1226 packet->callback(packet, &ctx->ohci->card, packet->ack);
1227 }
1228}
1229
1230static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1231{
1232 unsigned long flags;
1233 int ret;
1234
1235 spin_lock_irqsave(&ctx->ohci->lock, flags);
1236
1237 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1238 ctx->ohci->generation == packet->generation) {
1239 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1240 handle_local_request(ctx, packet);
1241 return;
1242 }
1243
1244 ret = at_context_queue_packet(ctx, packet);
1245 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1246
1247 if (ret < 0)
1248 packet->callback(packet, &ctx->ohci->card, packet->ack);
1249
1250}
1251
1252static void bus_reset_tasklet(unsigned long data)
1253{
1254 struct fw_ohci *ohci = (struct fw_ohci *)data;
1255 int self_id_count, i, j, reg;
1256 int generation, new_generation;
1257 unsigned long flags;
1258 void *free_rom = NULL;
1259 dma_addr_t free_rom_bus = 0;
1260
1261 reg = reg_read(ohci, OHCI1394_NodeID);
1262 if (!(reg & OHCI1394_NodeID_idValid)) {
1263 fw_notify("node ID not valid, new bus reset in progress\n");
1264 return;
1265 }
1266 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1267 fw_notify("malconfigured bus\n");
1268 return;
1269 }
1270 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1271 OHCI1394_NodeID_nodeNumber);
1272
1273 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1274 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1275 fw_notify("inconsistent self IDs\n");
1276 return;
1277 }
1278
1279
1280
1281
1282
1283
1284 self_id_count = (reg >> 3) & 0xff;
1285 if (self_id_count == 0 || self_id_count > 252) {
1286 fw_notify("inconsistent self IDs\n");
1287 return;
1288 }
1289 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1290 rmb();
1291
1292 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1293 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1294 fw_notify("inconsistent self IDs\n");
1295 return;
1296 }
1297 ohci->self_id_buffer[j] =
1298 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1299 }
1300 rmb();
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1317 if (new_generation != generation) {
1318 fw_notify("recursive bus reset detected, "
1319 "discarding self ids\n");
1320 return;
1321 }
1322
1323
1324 spin_lock_irqsave(&ohci->lock, flags);
1325
1326 ohci->generation = generation;
1327 context_stop(&ohci->at_request_ctx);
1328 context_stop(&ohci->at_response_ctx);
1329 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1330
1331 if (ohci->bus_reset_packet_quirk)
1332 ohci->request_generation = generation;
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343 if (ohci->next_config_rom != NULL) {
1344 if (ohci->next_config_rom != ohci->config_rom) {
1345 free_rom = ohci->config_rom;
1346 free_rom_bus = ohci->config_rom_bus;
1347 }
1348 ohci->config_rom = ohci->next_config_rom;
1349 ohci->config_rom_bus = ohci->next_config_rom_bus;
1350 ohci->next_config_rom = NULL;
1351
1352
1353
1354
1355
1356
1357
1358 reg_write(ohci, OHCI1394_BusOptions,
1359 be32_to_cpu(ohci->config_rom[2]));
1360 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1361 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1362 }
1363
1364#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1365 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1366 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1367#endif
1368
1369 spin_unlock_irqrestore(&ohci->lock, flags);
1370
1371 if (free_rom)
1372 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1373 free_rom, free_rom_bus);
1374
1375 log_selfids(ohci->node_id, generation,
1376 self_id_count, ohci->self_id_buffer);
1377
1378 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1379 self_id_count, ohci->self_id_buffer);
1380}
1381
1382static irqreturn_t irq_handler(int irq, void *data)
1383{
1384 struct fw_ohci *ohci = data;
1385 u32 event, iso_event, cycle_time;
1386 int i;
1387
1388 event = reg_read(ohci, OHCI1394_IntEventClear);
1389
1390 if (!event || !~event)
1391 return IRQ_NONE;
1392
1393
1394 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1395 log_irqs(event);
1396
1397 if (event & OHCI1394_selfIDComplete)
1398 tasklet_schedule(&ohci->bus_reset_tasklet);
1399
1400 if (event & OHCI1394_RQPkt)
1401 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1402
1403 if (event & OHCI1394_RSPkt)
1404 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1405
1406 if (event & OHCI1394_reqTxComplete)
1407 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1408
1409 if (event & OHCI1394_respTxComplete)
1410 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1411
1412 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1413 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1414
1415 while (iso_event) {
1416 i = ffs(iso_event) - 1;
1417 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1418 iso_event &= ~(1 << i);
1419 }
1420
1421 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1422 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1423
1424 while (iso_event) {
1425 i = ffs(iso_event) - 1;
1426 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1427 iso_event &= ~(1 << i);
1428 }
1429
1430 if (unlikely(event & OHCI1394_regAccessFail))
1431 fw_error("Register access failure - "
1432 "please notify linux1394-devel@lists.sf.net\n");
1433
1434 if (unlikely(event & OHCI1394_postedWriteErr))
1435 fw_error("PCI posted write error\n");
1436
1437 if (unlikely(event & OHCI1394_cycleTooLong)) {
1438 if (printk_ratelimit())
1439 fw_notify("isochronous cycle too long\n");
1440 reg_write(ohci, OHCI1394_LinkControlSet,
1441 OHCI1394_LinkControl_cycleMaster);
1442 }
1443
1444 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1445
1446
1447
1448
1449
1450
1451 if (printk_ratelimit())
1452 fw_notify("isochronous cycle inconsistent\n");
1453 }
1454
1455 if (event & OHCI1394_cycle64Seconds) {
1456 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1457 if ((cycle_time & 0x80000000) == 0)
1458 atomic_inc(&ohci->bus_seconds);
1459 }
1460
1461 return IRQ_HANDLED;
1462}
1463
1464static int software_reset(struct fw_ohci *ohci)
1465{
1466 int i;
1467
1468 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1469
1470 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1471 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1472 OHCI1394_HCControl_softReset) == 0)
1473 return 0;
1474 msleep(1);
1475 }
1476
1477 return -EBUSY;
1478}
1479
1480static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1481{
1482 struct fw_ohci *ohci = fw_ohci(card);
1483 struct pci_dev *dev = to_pci_dev(card->device);
1484 u32 lps;
1485 int i;
1486
1487 if (software_reset(ohci)) {
1488 fw_error("Failed to reset ohci card.\n");
1489 return -EBUSY;
1490 }
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500 reg_write(ohci, OHCI1394_HCControlSet,
1501 OHCI1394_HCControl_LPS |
1502 OHCI1394_HCControl_postedWriteEnable);
1503 flush_writes(ohci);
1504
1505 for (lps = 0, i = 0; !lps && i < 3; i++) {
1506 msleep(50);
1507 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1508 OHCI1394_HCControl_LPS;
1509 }
1510
1511 if (!lps) {
1512 fw_error("Failed to set Link Power Status\n");
1513 return -EIO;
1514 }
1515
1516 reg_write(ohci, OHCI1394_HCControlClear,
1517 OHCI1394_HCControl_noByteSwapData);
1518
1519 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1520 reg_write(ohci, OHCI1394_LinkControlClear,
1521 OHCI1394_LinkControl_rcvPhyPkt);
1522 reg_write(ohci, OHCI1394_LinkControlSet,
1523 OHCI1394_LinkControl_rcvSelfID |
1524 OHCI1394_LinkControl_cycleTimerEnable |
1525 OHCI1394_LinkControl_cycleMaster);
1526
1527 reg_write(ohci, OHCI1394_ATRetries,
1528 OHCI1394_MAX_AT_REQ_RETRIES |
1529 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1530 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1531
1532 ar_context_run(&ohci->ar_request_ctx);
1533 ar_context_run(&ohci->ar_response_ctx);
1534
1535 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1536 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1537 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1538 reg_write(ohci, OHCI1394_IntMaskSet,
1539 OHCI1394_selfIDComplete |
1540 OHCI1394_RQPkt | OHCI1394_RSPkt |
1541 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1542 OHCI1394_isochRx | OHCI1394_isochTx |
1543 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1544 OHCI1394_cycleInconsistent |
1545 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1546 OHCI1394_masterIntEnable);
1547 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1548 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1549
1550
1551 if (ohci_update_phy_reg(card, 4, 0,
1552 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1553 return -EIO;
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574 if (config_rom) {
1575 ohci->next_config_rom =
1576 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1577 &ohci->next_config_rom_bus,
1578 GFP_KERNEL);
1579 if (ohci->next_config_rom == NULL)
1580 return -ENOMEM;
1581
1582 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1583 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1584 } else {
1585
1586
1587
1588
1589 ohci->next_config_rom = ohci->config_rom;
1590 ohci->next_config_rom_bus = ohci->config_rom_bus;
1591 }
1592
1593 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1594 ohci->next_config_rom[0] = 0;
1595 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1596 reg_write(ohci, OHCI1394_BusOptions,
1597 be32_to_cpu(ohci->next_config_rom[2]));
1598 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1599
1600 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1601
1602 if (request_irq(dev->irq, irq_handler,
1603 IRQF_SHARED, ohci_driver_name, ohci)) {
1604 fw_error("Failed to allocate shared interrupt %d.\n",
1605 dev->irq);
1606 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1607 ohci->config_rom, ohci->config_rom_bus);
1608 return -EIO;
1609 }
1610
1611 reg_write(ohci, OHCI1394_HCControlSet,
1612 OHCI1394_HCControl_linkEnable |
1613 OHCI1394_HCControl_BIBimageValid);
1614 flush_writes(ohci);
1615
1616
1617
1618
1619
1620
1621 fw_core_initiate_bus_reset(&ohci->card, 1);
1622
1623 return 0;
1624}
1625
1626static int ohci_set_config_rom(struct fw_card *card,
1627 u32 *config_rom, size_t length)
1628{
1629 struct fw_ohci *ohci;
1630 unsigned long flags;
1631 int ret = -EBUSY;
1632 __be32 *next_config_rom;
1633 dma_addr_t uninitialized_var(next_config_rom_bus);
1634
1635 ohci = fw_ohci(card);
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664 next_config_rom =
1665 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1666 &next_config_rom_bus, GFP_KERNEL);
1667 if (next_config_rom == NULL)
1668 return -ENOMEM;
1669
1670 spin_lock_irqsave(&ohci->lock, flags);
1671
1672 if (ohci->next_config_rom == NULL) {
1673 ohci->next_config_rom = next_config_rom;
1674 ohci->next_config_rom_bus = next_config_rom_bus;
1675
1676 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1677 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1678 length * 4);
1679
1680 ohci->next_header = config_rom[0];
1681 ohci->next_config_rom[0] = 0;
1682
1683 reg_write(ohci, OHCI1394_ConfigROMmap,
1684 ohci->next_config_rom_bus);
1685 ret = 0;
1686 }
1687
1688 spin_unlock_irqrestore(&ohci->lock, flags);
1689
1690
1691
1692
1693
1694
1695
1696
1697 if (ret == 0)
1698 fw_core_initiate_bus_reset(&ohci->card, 1);
1699 else
1700 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1701 next_config_rom, next_config_rom_bus);
1702
1703 return ret;
1704}
1705
1706static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1707{
1708 struct fw_ohci *ohci = fw_ohci(card);
1709
1710 at_context_transmit(&ohci->at_request_ctx, packet);
1711}
1712
1713static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1714{
1715 struct fw_ohci *ohci = fw_ohci(card);
1716
1717 at_context_transmit(&ohci->at_response_ctx, packet);
1718}
1719
1720static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1721{
1722 struct fw_ohci *ohci = fw_ohci(card);
1723 struct context *ctx = &ohci->at_request_ctx;
1724 struct driver_data *driver_data = packet->driver_data;
1725 int ret = -ENOENT;
1726
1727 tasklet_disable(&ctx->tasklet);
1728
1729 if (packet->ack != 0)
1730 goto out;
1731
1732 if (packet->payload_bus)
1733 dma_unmap_single(ohci->card.device, packet->payload_bus,
1734 packet->payload_length, DMA_TO_DEVICE);
1735
1736 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1737 driver_data->packet = NULL;
1738 packet->ack = RCODE_CANCELLED;
1739 packet->callback(packet, &ohci->card, packet->ack);
1740 ret = 0;
1741 out:
1742 tasklet_enable(&ctx->tasklet);
1743
1744 return ret;
1745}
1746
1747static int ohci_enable_phys_dma(struct fw_card *card,
1748 int node_id, int generation)
1749{
1750#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1751 return 0;
1752#else
1753 struct fw_ohci *ohci = fw_ohci(card);
1754 unsigned long flags;
1755 int n, ret = 0;
1756
1757
1758
1759
1760
1761
1762 spin_lock_irqsave(&ohci->lock, flags);
1763
1764 if (ohci->generation != generation) {
1765 ret = -ESTALE;
1766 goto out;
1767 }
1768
1769
1770
1771
1772
1773
1774 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1775 if (n < 32)
1776 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1777 else
1778 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1779
1780 flush_writes(ohci);
1781 out:
1782 spin_unlock_irqrestore(&ohci->lock, flags);
1783
1784 return ret;
1785#endif
1786}
1787
1788static u64 ohci_get_bus_time(struct fw_card *card)
1789{
1790 struct fw_ohci *ohci = fw_ohci(card);
1791 u32 cycle_time;
1792 u64 bus_time;
1793
1794 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1795 bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1796
1797 return bus_time;
1798}
1799
1800static void copy_iso_headers(struct iso_context *ctx, void *p)
1801{
1802 int i = ctx->header_length;
1803
1804 if (i + ctx->base.header_size > PAGE_SIZE)
1805 return;
1806
1807
1808
1809
1810
1811
1812
1813 if (ctx->base.header_size > 0)
1814 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1815 if (ctx->base.header_size > 4)
1816 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1817 if (ctx->base.header_size > 8)
1818 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1819 ctx->header_length += ctx->base.header_size;
1820}
1821
1822static int handle_ir_dualbuffer_packet(struct context *context,
1823 struct descriptor *d,
1824 struct descriptor *last)
1825{
1826 struct iso_context *ctx =
1827 container_of(context, struct iso_context, context);
1828 struct db_descriptor *db = (struct db_descriptor *) d;
1829 __le32 *ir_header;
1830 size_t header_length;
1831 void *p, *end;
1832
1833 if (db->first_res_count != 0 && db->second_res_count != 0) {
1834 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1835
1836 return 0;
1837 }
1838 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1839 }
1840
1841 header_length = le16_to_cpu(db->first_req_count) -
1842 le16_to_cpu(db->first_res_count);
1843
1844 p = db + 1;
1845 end = p + header_length;
1846 while (p < end) {
1847 copy_iso_headers(ctx, p);
1848 ctx->excess_bytes +=
1849 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1850 p += max(ctx->base.header_size, (size_t)8);
1851 }
1852
1853 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1854 le16_to_cpu(db->second_res_count);
1855
1856 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1857 ir_header = (__le32 *) (db + 1);
1858 ctx->base.callback(&ctx->base,
1859 le32_to_cpu(ir_header[0]) & 0xffff,
1860 ctx->header_length, ctx->header,
1861 ctx->base.callback_data);
1862 ctx->header_length = 0;
1863 }
1864
1865 return 1;
1866}
1867
1868static int handle_ir_packet_per_buffer(struct context *context,
1869 struct descriptor *d,
1870 struct descriptor *last)
1871{
1872 struct iso_context *ctx =
1873 container_of(context, struct iso_context, context);
1874 struct descriptor *pd;
1875 __le32 *ir_header;
1876 void *p;
1877
1878 for (pd = d; pd <= last; pd++) {
1879 if (pd->transfer_status)
1880 break;
1881 }
1882 if (pd > last)
1883
1884 return 0;
1885
1886 p = last + 1;
1887 copy_iso_headers(ctx, p);
1888
1889 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1890 ir_header = (__le32 *) p;
1891 ctx->base.callback(&ctx->base,
1892 le32_to_cpu(ir_header[0]) & 0xffff,
1893 ctx->header_length, ctx->header,
1894 ctx->base.callback_data);
1895 ctx->header_length = 0;
1896 }
1897
1898 return 1;
1899}
1900
1901static int handle_it_packet(struct context *context,
1902 struct descriptor *d,
1903 struct descriptor *last)
1904{
1905 struct iso_context *ctx =
1906 container_of(context, struct iso_context, context);
1907 int i;
1908 struct descriptor *pd;
1909
1910 for (pd = d; pd <= last; pd++)
1911 if (pd->transfer_status)
1912 break;
1913 if (pd > last)
1914
1915 return 0;
1916
1917 i = ctx->header_length;
1918 if (i + 4 < PAGE_SIZE) {
1919
1920 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1921 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1922 le16_to_cpu(pd->res_count));
1923 ctx->header_length += 4;
1924 }
1925 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1926 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1927 ctx->header_length, ctx->header,
1928 ctx->base.callback_data);
1929 ctx->header_length = 0;
1930 }
1931 return 1;
1932}
1933
1934static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1935 int type, int channel, size_t header_size)
1936{
1937 struct fw_ohci *ohci = fw_ohci(card);
1938 struct iso_context *ctx, *list;
1939 descriptor_callback_t callback;
1940 u64 *channels, dont_care = ~0ULL;
1941 u32 *mask, regs;
1942 unsigned long flags;
1943 int index, ret = -ENOMEM;
1944
1945 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1946 channels = &dont_care;
1947 mask = &ohci->it_context_mask;
1948 list = ohci->it_context_list;
1949 callback = handle_it_packet;
1950 } else {
1951 channels = &ohci->ir_context_channels;
1952 mask = &ohci->ir_context_mask;
1953 list = ohci->ir_context_list;
1954 if (ohci->use_dualbuffer)
1955 callback = handle_ir_dualbuffer_packet;
1956 else
1957 callback = handle_ir_packet_per_buffer;
1958 }
1959
1960 spin_lock_irqsave(&ohci->lock, flags);
1961 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1962 if (index >= 0) {
1963 *channels &= ~(1ULL << channel);
1964 *mask &= ~(1 << index);
1965 }
1966 spin_unlock_irqrestore(&ohci->lock, flags);
1967
1968 if (index < 0)
1969 return ERR_PTR(-EBUSY);
1970
1971 if (type == FW_ISO_CONTEXT_TRANSMIT)
1972 regs = OHCI1394_IsoXmitContextBase(index);
1973 else
1974 regs = OHCI1394_IsoRcvContextBase(index);
1975
1976 ctx = &list[index];
1977 memset(ctx, 0, sizeof(*ctx));
1978 ctx->header_length = 0;
1979 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1980 if (ctx->header == NULL)
1981 goto out;
1982
1983 ret = context_init(&ctx->context, ohci, regs, callback);
1984 if (ret < 0)
1985 goto out_with_header;
1986
1987 return &ctx->base;
1988
1989 out_with_header:
1990 free_page((unsigned long)ctx->header);
1991 out:
1992 spin_lock_irqsave(&ohci->lock, flags);
1993 *mask |= 1 << index;
1994 spin_unlock_irqrestore(&ohci->lock, flags);
1995
1996 return ERR_PTR(ret);
1997}
1998
1999static int ohci_start_iso(struct fw_iso_context *base,
2000 s32 cycle, u32 sync, u32 tags)
2001{
2002 struct iso_context *ctx = container_of(base, struct iso_context, base);
2003 struct fw_ohci *ohci = ctx->context.ohci;
2004 u32 control, match;
2005 int index;
2006
2007 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2008 index = ctx - ohci->it_context_list;
2009 match = 0;
2010 if (cycle >= 0)
2011 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2012 (cycle & 0x7fff) << 16;
2013
2014 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2015 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2016 context_run(&ctx->context, match);
2017 } else {
2018 index = ctx - ohci->ir_context_list;
2019 control = IR_CONTEXT_ISOCH_HEADER;
2020 if (ohci->use_dualbuffer)
2021 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2022 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2023 if (cycle >= 0) {
2024 match |= (cycle & 0x07fff) << 12;
2025 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2026 }
2027
2028 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2029 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2030 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2031 context_run(&ctx->context, control);
2032 }
2033
2034 return 0;
2035}
2036
2037static int ohci_stop_iso(struct fw_iso_context *base)
2038{
2039 struct fw_ohci *ohci = fw_ohci(base->card);
2040 struct iso_context *ctx = container_of(base, struct iso_context, base);
2041 int index;
2042
2043 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2044 index = ctx - ohci->it_context_list;
2045 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2046 } else {
2047 index = ctx - ohci->ir_context_list;
2048 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2049 }
2050 flush_writes(ohci);
2051 context_stop(&ctx->context);
2052
2053 return 0;
2054}
2055
2056static void ohci_free_iso_context(struct fw_iso_context *base)
2057{
2058 struct fw_ohci *ohci = fw_ohci(base->card);
2059 struct iso_context *ctx = container_of(base, struct iso_context, base);
2060 unsigned long flags;
2061 int index;
2062
2063 ohci_stop_iso(base);
2064 context_release(&ctx->context);
2065 free_page((unsigned long)ctx->header);
2066
2067 spin_lock_irqsave(&ohci->lock, flags);
2068
2069 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2070 index = ctx - ohci->it_context_list;
2071 ohci->it_context_mask |= 1 << index;
2072 } else {
2073 index = ctx - ohci->ir_context_list;
2074 ohci->ir_context_mask |= 1 << index;
2075 ohci->ir_context_channels |= 1ULL << base->channel;
2076 }
2077
2078 spin_unlock_irqrestore(&ohci->lock, flags);
2079}
2080
2081static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2082 struct fw_iso_packet *packet,
2083 struct fw_iso_buffer *buffer,
2084 unsigned long payload)
2085{
2086 struct iso_context *ctx = container_of(base, struct iso_context, base);
2087 struct descriptor *d, *last, *pd;
2088 struct fw_iso_packet *p;
2089 __le32 *header;
2090 dma_addr_t d_bus, page_bus;
2091 u32 z, header_z, payload_z, irq;
2092 u32 payload_index, payload_end_index, next_page_index;
2093 int page, end_page, i, length, offset;
2094
2095
2096
2097
2098
2099
2100 p = packet;
2101 payload_index = payload;
2102
2103 if (p->skip)
2104 z = 1;
2105 else
2106 z = 2;
2107 if (p->header_length > 0)
2108 z++;
2109
2110
2111 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2112 if (p->payload_length > 0)
2113 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2114 else
2115 payload_z = 0;
2116
2117 z += payload_z;
2118
2119
2120 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2121
2122 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2123 if (d == NULL)
2124 return -ENOMEM;
2125
2126 if (!p->skip) {
2127 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2128 d[0].req_count = cpu_to_le16(8);
2129
2130 header = (__le32 *) &d[1];
2131 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2132 IT_HEADER_TAG(p->tag) |
2133 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2134 IT_HEADER_CHANNEL(ctx->base.channel) |
2135 IT_HEADER_SPEED(ctx->base.speed));
2136 header[1] =
2137 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2138 p->payload_length));
2139 }
2140
2141 if (p->header_length > 0) {
2142 d[2].req_count = cpu_to_le16(p->header_length);
2143 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2144 memcpy(&d[z], p->header, p->header_length);
2145 }
2146
2147 pd = d + z - payload_z;
2148 payload_end_index = payload_index + p->payload_length;
2149 for (i = 0; i < payload_z; i++) {
2150 page = payload_index >> PAGE_SHIFT;
2151 offset = payload_index & ~PAGE_MASK;
2152 next_page_index = (page + 1) << PAGE_SHIFT;
2153 length =
2154 min(next_page_index, payload_end_index) - payload_index;
2155 pd[i].req_count = cpu_to_le16(length);
2156
2157 page_bus = page_private(buffer->pages[page]);
2158 pd[i].data_address = cpu_to_le32(page_bus + offset);
2159
2160 payload_index += length;
2161 }
2162
2163 if (p->interrupt)
2164 irq = DESCRIPTOR_IRQ_ALWAYS;
2165 else
2166 irq = DESCRIPTOR_NO_IRQ;
2167
2168 last = z == 2 ? d : d + z - 1;
2169 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2170 DESCRIPTOR_STATUS |
2171 DESCRIPTOR_BRANCH_ALWAYS |
2172 irq);
2173
2174 context_append(&ctx->context, d, z, header_z);
2175
2176 return 0;
2177}
2178
2179static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2180 struct fw_iso_packet *packet,
2181 struct fw_iso_buffer *buffer,
2182 unsigned long payload)
2183{
2184 struct iso_context *ctx = container_of(base, struct iso_context, base);
2185 struct db_descriptor *db = NULL;
2186 struct descriptor *d;
2187 struct fw_iso_packet *p;
2188 dma_addr_t d_bus, page_bus;
2189 u32 z, header_z, length, rest;
2190 int page, offset, packet_count, header_size;
2191
2192
2193
2194
2195
2196
2197 p = packet;
2198 z = 2;
2199
2200
2201
2202
2203
2204 packet_count = p->header_length / ctx->base.header_size;
2205 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2206
2207
2208 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2209 page = payload >> PAGE_SHIFT;
2210 offset = payload & ~PAGE_MASK;
2211 rest = p->payload_length;
2212
2213
2214 while (rest > 0) {
2215 d = context_get_descriptors(&ctx->context,
2216 z + header_z, &d_bus);
2217 if (d == NULL)
2218 return -ENOMEM;
2219
2220 db = (struct db_descriptor *) d;
2221 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2222 DESCRIPTOR_BRANCH_ALWAYS);
2223 db->first_size =
2224 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2225 if (p->skip && rest == p->payload_length) {
2226 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2227 db->first_req_count = db->first_size;
2228 } else {
2229 db->first_req_count = cpu_to_le16(header_size);
2230 }
2231 db->first_res_count = db->first_req_count;
2232 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2233
2234 if (p->skip && rest == p->payload_length)
2235 length = 4;
2236 else if (offset + rest < PAGE_SIZE)
2237 length = rest;
2238 else
2239 length = PAGE_SIZE - offset;
2240
2241 db->second_req_count = cpu_to_le16(length);
2242 db->second_res_count = db->second_req_count;
2243 page_bus = page_private(buffer->pages[page]);
2244 db->second_buffer = cpu_to_le32(page_bus + offset);
2245
2246 if (p->interrupt && length == rest)
2247 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2248
2249 context_append(&ctx->context, d, z, header_z);
2250 offset = (offset + length) & ~PAGE_MASK;
2251 rest -= length;
2252 if (offset == 0)
2253 page++;
2254 }
2255
2256 return 0;
2257}
2258
2259static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2260 struct fw_iso_packet *packet,
2261 struct fw_iso_buffer *buffer,
2262 unsigned long payload)
2263{
2264 struct iso_context *ctx = container_of(base, struct iso_context, base);
2265 struct descriptor *d = NULL, *pd = NULL;
2266 struct fw_iso_packet *p = packet;
2267 dma_addr_t d_bus, page_bus;
2268 u32 z, header_z, rest;
2269 int i, j, length;
2270 int page, offset, packet_count, header_size, payload_per_buffer;
2271
2272
2273
2274
2275
2276 packet_count = p->header_length / ctx->base.header_size;
2277 header_size = max(ctx->base.header_size, (size_t)8);
2278
2279
2280 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2281 page = payload >> PAGE_SHIFT;
2282 offset = payload & ~PAGE_MASK;
2283 payload_per_buffer = p->payload_length / packet_count;
2284
2285 for (i = 0; i < packet_count; i++) {
2286
2287 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2288 d = context_get_descriptors(&ctx->context,
2289 z + header_z, &d_bus);
2290 if (d == NULL)
2291 return -ENOMEM;
2292
2293 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2294 DESCRIPTOR_INPUT_MORE);
2295 if (p->skip && i == 0)
2296 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2297 d->req_count = cpu_to_le16(header_size);
2298 d->res_count = d->req_count;
2299 d->transfer_status = 0;
2300 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2301
2302 rest = payload_per_buffer;
2303 for (j = 1; j < z; j++) {
2304 pd = d + j;
2305 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2306 DESCRIPTOR_INPUT_MORE);
2307
2308 if (offset + rest < PAGE_SIZE)
2309 length = rest;
2310 else
2311 length = PAGE_SIZE - offset;
2312 pd->req_count = cpu_to_le16(length);
2313 pd->res_count = pd->req_count;
2314 pd->transfer_status = 0;
2315
2316 page_bus = page_private(buffer->pages[page]);
2317 pd->data_address = cpu_to_le32(page_bus + offset);
2318
2319 offset = (offset + length) & ~PAGE_MASK;
2320 rest -= length;
2321 if (offset == 0)
2322 page++;
2323 }
2324 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2325 DESCRIPTOR_INPUT_LAST |
2326 DESCRIPTOR_BRANCH_ALWAYS);
2327 if (p->interrupt && i == packet_count - 1)
2328 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2329
2330 context_append(&ctx->context, d, z, header_z);
2331 }
2332
2333 return 0;
2334}
2335
2336static int ohci_queue_iso(struct fw_iso_context *base,
2337 struct fw_iso_packet *packet,
2338 struct fw_iso_buffer *buffer,
2339 unsigned long payload)
2340{
2341 struct iso_context *ctx = container_of(base, struct iso_context, base);
2342 unsigned long flags;
2343 int ret;
2344
2345 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2346 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2347 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2348 else if (ctx->context.ohci->use_dualbuffer)
2349 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2350 buffer, payload);
2351 else
2352 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2353 buffer, payload);
2354 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2355
2356 return ret;
2357}
2358
2359static const struct fw_card_driver ohci_driver = {
2360 .enable = ohci_enable,
2361 .update_phy_reg = ohci_update_phy_reg,
2362 .set_config_rom = ohci_set_config_rom,
2363 .send_request = ohci_send_request,
2364 .send_response = ohci_send_response,
2365 .cancel_packet = ohci_cancel_packet,
2366 .enable_phys_dma = ohci_enable_phys_dma,
2367 .get_bus_time = ohci_get_bus_time,
2368
2369 .allocate_iso_context = ohci_allocate_iso_context,
2370 .free_iso_context = ohci_free_iso_context,
2371 .queue_iso = ohci_queue_iso,
2372 .start_iso = ohci_start_iso,
2373 .stop_iso = ohci_stop_iso,
2374};
2375
2376#ifdef CONFIG_PPC_PMAC
2377static void ohci_pmac_on(struct pci_dev *dev)
2378{
2379 if (machine_is(powermac)) {
2380 struct device_node *ofn = pci_device_to_OF_node(dev);
2381
2382 if (ofn) {
2383 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2384 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2385 }
2386 }
2387}
2388
2389static void ohci_pmac_off(struct pci_dev *dev)
2390{
2391 if (machine_is(powermac)) {
2392 struct device_node *ofn = pci_device_to_OF_node(dev);
2393
2394 if (ofn) {
2395 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2396 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2397 }
2398 }
2399}
2400#else
2401#define ohci_pmac_on(dev)
2402#define ohci_pmac_off(dev)
2403#endif
2404
2405#define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2406#define PCI_DEVICE_ID_AGERE_FW643 0x5901
2407
2408static int __devinit pci_probe(struct pci_dev *dev,
2409 const struct pci_device_id *ent)
2410{
2411 struct fw_ohci *ohci;
2412 u32 bus_options, max_receive, link_speed, version;
2413 u64 guid;
2414 int err;
2415 size_t size;
2416
2417 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2418 if (ohci == NULL) {
2419 err = -ENOMEM;
2420 goto fail;
2421 }
2422
2423 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2424
2425 ohci_pmac_on(dev);
2426
2427 err = pci_enable_device(dev);
2428 if (err) {
2429 fw_error("Failed to enable OHCI hardware\n");
2430 goto fail_free;
2431 }
2432
2433 pci_set_master(dev);
2434 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2435 pci_set_drvdata(dev, ohci);
2436
2437 spin_lock_init(&ohci->lock);
2438
2439 tasklet_init(&ohci->bus_reset_tasklet,
2440 bus_reset_tasklet, (unsigned long)ohci);
2441
2442 err = pci_request_region(dev, 0, ohci_driver_name);
2443 if (err) {
2444 fw_error("MMIO resource unavailable\n");
2445 goto fail_disable;
2446 }
2447
2448 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2449 if (ohci->registers == NULL) {
2450 fw_error("Failed to remap registers\n");
2451 err = -ENXIO;
2452 goto fail_iomem;
2453 }
2454
2455 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2456 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2457
2458
2459 if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2460 dev->device == PCI_DEVICE_ID_AGERE_FW643)
2461 ohci->use_dualbuffer = false;
2462
2463
2464 if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2465 dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2466 ohci->use_dualbuffer = false;
2467
2468
2469#if !defined(CONFIG_X86_32)
2470
2471 if (dev->vendor == PCI_VENDOR_ID_TI &&
2472 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2473 ohci->use_dualbuffer = false;
2474#endif
2475
2476#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2477 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2478 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2479#endif
2480 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2481
2482 ar_context_init(&ohci->ar_request_ctx, ohci,
2483 OHCI1394_AsReqRcvContextControlSet);
2484
2485 ar_context_init(&ohci->ar_response_ctx, ohci,
2486 OHCI1394_AsRspRcvContextControlSet);
2487
2488 context_init(&ohci->at_request_ctx, ohci,
2489 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2490
2491 context_init(&ohci->at_response_ctx, ohci,
2492 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2493
2494 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2495 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2496 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2497 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2498 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2499
2500 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2501 ohci->ir_context_channels = ~0ULL;
2502 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2503 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2504 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2505 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2506
2507 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2508 err = -ENOMEM;
2509 goto fail_contexts;
2510 }
2511
2512
2513 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2514 SELF_ID_BUF_SIZE,
2515 &ohci->self_id_bus,
2516 GFP_KERNEL);
2517 if (ohci->self_id_cpu == NULL) {
2518 err = -ENOMEM;
2519 goto fail_contexts;
2520 }
2521
2522 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2523 max_receive = (bus_options >> 12) & 0xf;
2524 link_speed = bus_options & 0x7;
2525 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2526 reg_read(ohci, OHCI1394_GUIDLo);
2527
2528 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2529 if (err)
2530 goto fail_self_id;
2531
2532 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2533 dev_name(&dev->dev), version >> 16, version & 0xff);
2534
2535 return 0;
2536
2537 fail_self_id:
2538 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2539 ohci->self_id_cpu, ohci->self_id_bus);
2540 fail_contexts:
2541 kfree(ohci->ir_context_list);
2542 kfree(ohci->it_context_list);
2543 context_release(&ohci->at_response_ctx);
2544 context_release(&ohci->at_request_ctx);
2545 ar_context_release(&ohci->ar_response_ctx);
2546 ar_context_release(&ohci->ar_request_ctx);
2547 pci_iounmap(dev, ohci->registers);
2548 fail_iomem:
2549 pci_release_region(dev, 0);
2550 fail_disable:
2551 pci_disable_device(dev);
2552 fail_free:
2553 kfree(&ohci->card);
2554 ohci_pmac_off(dev);
2555 fail:
2556 if (err == -ENOMEM)
2557 fw_error("Out of memory\n");
2558
2559 return err;
2560}
2561
2562static void pci_remove(struct pci_dev *dev)
2563{
2564 struct fw_ohci *ohci;
2565
2566 ohci = pci_get_drvdata(dev);
2567 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2568 flush_writes(ohci);
2569 fw_core_remove_card(&ohci->card);
2570
2571
2572
2573
2574
2575
2576 software_reset(ohci);
2577 free_irq(dev->irq, ohci);
2578
2579 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2580 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2581 ohci->next_config_rom, ohci->next_config_rom_bus);
2582 if (ohci->config_rom)
2583 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2584 ohci->config_rom, ohci->config_rom_bus);
2585 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2586 ohci->self_id_cpu, ohci->self_id_bus);
2587 ar_context_release(&ohci->ar_request_ctx);
2588 ar_context_release(&ohci->ar_response_ctx);
2589 context_release(&ohci->at_request_ctx);
2590 context_release(&ohci->at_response_ctx);
2591 kfree(ohci->it_context_list);
2592 kfree(ohci->ir_context_list);
2593 pci_iounmap(dev, ohci->registers);
2594 pci_release_region(dev, 0);
2595 pci_disable_device(dev);
2596 kfree(&ohci->card);
2597 ohci_pmac_off(dev);
2598
2599 fw_notify("Removed fw-ohci device.\n");
2600}
2601
2602#ifdef CONFIG_PM
2603static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2604{
2605 struct fw_ohci *ohci = pci_get_drvdata(dev);
2606 int err;
2607
2608 software_reset(ohci);
2609 free_irq(dev->irq, ohci);
2610 err = pci_save_state(dev);
2611 if (err) {
2612 fw_error("pci_save_state failed\n");
2613 return err;
2614 }
2615 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2616 if (err)
2617 fw_error("pci_set_power_state failed with %d\n", err);
2618 ohci_pmac_off(dev);
2619
2620 return 0;
2621}
2622
2623static int pci_resume(struct pci_dev *dev)
2624{
2625 struct fw_ohci *ohci = pci_get_drvdata(dev);
2626 int err;
2627
2628 ohci_pmac_on(dev);
2629 pci_set_power_state(dev, PCI_D0);
2630 pci_restore_state(dev);
2631 err = pci_enable_device(dev);
2632 if (err) {
2633 fw_error("pci_enable_device failed\n");
2634 return err;
2635 }
2636
2637 return ohci_enable(&ohci->card, NULL, 0);
2638}
2639#endif
2640
2641static struct pci_device_id pci_table[] = {
2642 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2643 { }
2644};
2645
2646MODULE_DEVICE_TABLE(pci, pci_table);
2647
2648static struct pci_driver fw_ohci_pci_driver = {
2649 .name = ohci_driver_name,
2650 .id_table = pci_table,
2651 .probe = pci_probe,
2652 .remove = pci_remove,
2653#ifdef CONFIG_PM
2654 .resume = pci_resume,
2655 .suspend = pci_suspend,
2656#endif
2657};
2658
2659MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2660MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2661MODULE_LICENSE("GPL");
2662
2663
2664#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2665MODULE_ALIAS("ohci1394");
2666#endif
2667
2668static int __init fw_ohci_init(void)
2669{
2670 return pci_register_driver(&fw_ohci_pci_driver);
2671}
2672
2673static void __exit fw_ohci_cleanup(void)
2674{
2675 pci_unregister_driver(&fw_ohci_pci_driver);
2676}
2677
2678module_init(fw_ohci_init);
2679module_exit(fw_ohci_cleanup);
2680