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30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include <linux/io-mapping.h>
36
37
38
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
44#define DRIVER_DATE "20080730"
45
46enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
51enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54};
55
56#define I915_NUM_PIPE 2
57
58
59
60
61
62
63
64
65
66
67
68#define DRIVER_MAJOR 1
69#define DRIVER_MINOR 6
70#define DRIVER_PATCHLEVEL 0
71
72#define WATCH_COHERENCY 0
73#define WATCH_BUF 0
74#define WATCH_EXEC 0
75#define WATCH_LRU 0
76#define WATCH_RELOC 0
77#define WATCH_INACTIVE 0
78#define WATCH_PWRITE 0
79
80#define I915_GEM_PHYS_CURSOR_0 1
81#define I915_GEM_PHYS_CURSOR_1 2
82#define I915_GEM_PHYS_OVERLAY_REGS 3
83#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90};
91
92typedef struct _drm_i915_ring_buffer {
93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
99 struct drm_gem_object *ring_obj;
100} drm_i915_ring_buffer_t;
101
102struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
107 struct drm_file *file_priv;
108};
109
110struct opregion_header;
111struct opregion_acpi;
112struct opregion_swsci;
113struct opregion_asle;
114
115struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121};
122
123struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126};
127#define I915_FENCE_REG_NONE -1
128
129struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131};
132
133struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138};
139
140struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154};
155
156struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165
166
167
168
169
170
171};
172
173typedef struct drm_i915_private {
174 struct drm_device *dev;
175
176 int has_gem;
177
178 void __iomem *regs;
179
180 struct pci_dev *bridge_dev;
181 drm_i915_ring_buffer_t ring;
182
183 drm_dma_handle_t *status_page_dmah;
184 void *hw_status_page;
185 dma_addr_t dma_status_page;
186 uint32_t counter;
187 unsigned int status_gfx_addr;
188 drm_local_map_t hws_map;
189 struct drm_gem_object *hws_obj;
190
191 struct resource mch_res;
192
193 unsigned int cpp;
194 int back_offset;
195 int front_offset;
196 int current_page;
197 int page_flipping;
198
199 wait_queue_head_t irq_queue;
200 atomic_t irq_received;
201
202 spinlock_t user_irq_lock;
203
204 int user_irq_refcount;
205 u32 trace_irq_seqno;
206
207 u32 irq_mask_reg;
208 u32 pipestat[2];
209
210
211 u32 gt_irq_mask_reg;
212 u32 gt_irq_enable_reg;
213 u32 de_irq_enable_reg;
214
215 u32 hotplug_supported_mask;
216 struct work_struct hotplug_work;
217
218 int tex_lru_log_granularity;
219 int allow_batchbuffer;
220 struct mem_block *agp_heap;
221 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
222 int vblank_pipe;
223
224
225#define DRM_I915_HANGCHECK_PERIOD 75
226 struct timer_list hangcheck_timer;
227 int hangcheck_count;
228 uint32_t last_acthd;
229
230 bool cursor_needs_physical;
231
232 struct drm_mm vram;
233
234 unsigned long cfb_size;
235 unsigned long cfb_pitch;
236 int cfb_fence;
237 int cfb_plane;
238
239 int irq_enabled;
240
241 struct intel_opregion opregion;
242
243
244 int backlight_duty_cycle;
245 bool panel_wants_dither;
246 struct drm_display_mode *panel_fixed_mode;
247 struct drm_display_mode *lfp_lvds_vbt_mode;
248 struct drm_display_mode *sdvo_lvds_vbt_mode;
249
250
251 unsigned int int_tv_support:1;
252 unsigned int lvds_dither:1;
253 unsigned int lvds_vbt:1;
254 unsigned int int_crt_support:1;
255 unsigned int lvds_use_ssc:1;
256 unsigned int edp_support:1;
257 int lvds_ssc_freq;
258
259 struct notifier_block lid_notifier;
260
261 int crt_ddc_bus;
262 struct drm_i915_fence_reg fence_regs[16];
263 int fence_reg_start;
264 int num_fence_regs;
265
266 unsigned int fsb_freq, mem_freq;
267
268 spinlock_t error_lock;
269 struct drm_i915_error_state *first_error;
270 struct work_struct error_work;
271 struct workqueue_struct *wq;
272
273
274 struct drm_i915_display_funcs display;
275
276
277 bool modeset_on_lid;
278 u8 saveLBB;
279 u32 saveDSPACNTR;
280 u32 saveDSPBCNTR;
281 u32 saveDSPARB;
282 u32 saveRENDERSTANDBY;
283 u32 saveHWS;
284 u32 savePIPEACONF;
285 u32 savePIPEBCONF;
286 u32 savePIPEASRC;
287 u32 savePIPEBSRC;
288 u32 saveFPA0;
289 u32 saveFPA1;
290 u32 saveDPLL_A;
291 u32 saveDPLL_A_MD;
292 u32 saveHTOTAL_A;
293 u32 saveHBLANK_A;
294 u32 saveHSYNC_A;
295 u32 saveVTOTAL_A;
296 u32 saveVBLANK_A;
297 u32 saveVSYNC_A;
298 u32 saveBCLRPAT_A;
299 u32 saveTRANSACONF;
300 u32 saveTRANS_HTOTAL_A;
301 u32 saveTRANS_HBLANK_A;
302 u32 saveTRANS_HSYNC_A;
303 u32 saveTRANS_VTOTAL_A;
304 u32 saveTRANS_VBLANK_A;
305 u32 saveTRANS_VSYNC_A;
306 u32 savePIPEASTAT;
307 u32 saveDSPASTRIDE;
308 u32 saveDSPASIZE;
309 u32 saveDSPAPOS;
310 u32 saveDSPAADDR;
311 u32 saveDSPASURF;
312 u32 saveDSPATILEOFF;
313 u32 savePFIT_PGM_RATIOS;
314 u32 saveBLC_HIST_CTL;
315 u32 saveBLC_PWM_CTL;
316 u32 saveBLC_PWM_CTL2;
317 u32 saveBLC_CPU_PWM_CTL;
318 u32 saveBLC_CPU_PWM_CTL2;
319 u32 saveFPB0;
320 u32 saveFPB1;
321 u32 saveDPLL_B;
322 u32 saveDPLL_B_MD;
323 u32 saveHTOTAL_B;
324 u32 saveHBLANK_B;
325 u32 saveHSYNC_B;
326 u32 saveVTOTAL_B;
327 u32 saveVBLANK_B;
328 u32 saveVSYNC_B;
329 u32 saveBCLRPAT_B;
330 u32 saveTRANSBCONF;
331 u32 saveTRANS_HTOTAL_B;
332 u32 saveTRANS_HBLANK_B;
333 u32 saveTRANS_HSYNC_B;
334 u32 saveTRANS_VTOTAL_B;
335 u32 saveTRANS_VBLANK_B;
336 u32 saveTRANS_VSYNC_B;
337 u32 savePIPEBSTAT;
338 u32 saveDSPBSTRIDE;
339 u32 saveDSPBSIZE;
340 u32 saveDSPBPOS;
341 u32 saveDSPBADDR;
342 u32 saveDSPBSURF;
343 u32 saveDSPBTILEOFF;
344 u32 saveVGA0;
345 u32 saveVGA1;
346 u32 saveVGA_PD;
347 u32 saveVGACNTRL;
348 u32 saveADPA;
349 u32 saveLVDS;
350 u32 savePP_ON_DELAYS;
351 u32 savePP_OFF_DELAYS;
352 u32 saveDVOA;
353 u32 saveDVOB;
354 u32 saveDVOC;
355 u32 savePP_ON;
356 u32 savePP_OFF;
357 u32 savePP_CONTROL;
358 u32 savePP_DIVISOR;
359 u32 savePFIT_CONTROL;
360 u32 save_palette_a[256];
361 u32 save_palette_b[256];
362 u32 saveDPFC_CB_BASE;
363 u32 saveFBC_CFB_BASE;
364 u32 saveFBC_LL_BASE;
365 u32 saveFBC_CONTROL;
366 u32 saveFBC_CONTROL2;
367 u32 saveIER;
368 u32 saveIIR;
369 u32 saveIMR;
370 u32 saveDEIER;
371 u32 saveDEIMR;
372 u32 saveGTIER;
373 u32 saveGTIMR;
374 u32 saveFDI_RXA_IMR;
375 u32 saveFDI_RXB_IMR;
376 u32 saveCACHE_MODE_0;
377 u32 saveD_STATE;
378 u32 saveDSPCLK_GATE_D;
379 u32 saveMI_ARB_STATE;
380 u32 saveSWF0[16];
381 u32 saveSWF1[16];
382 u32 saveSWF2[3];
383 u8 saveMSR;
384 u8 saveSR[8];
385 u8 saveGR[25];
386 u8 saveAR_INDEX;
387 u8 saveAR[21];
388 u8 saveDACMASK;
389 u8 saveCR[37];
390 uint64_t saveFENCE[16];
391 u32 saveCURACNTR;
392 u32 saveCURAPOS;
393 u32 saveCURABASE;
394 u32 saveCURBCNTR;
395 u32 saveCURBPOS;
396 u32 saveCURBBASE;
397 u32 saveCURSIZE;
398 u32 saveDP_B;
399 u32 saveDP_C;
400 u32 saveDP_D;
401 u32 savePIPEA_GMCH_DATA_M;
402 u32 savePIPEB_GMCH_DATA_M;
403 u32 savePIPEA_GMCH_DATA_N;
404 u32 savePIPEB_GMCH_DATA_N;
405 u32 savePIPEA_DP_LINK_M;
406 u32 savePIPEB_DP_LINK_M;
407 u32 savePIPEA_DP_LINK_N;
408 u32 savePIPEB_DP_LINK_N;
409 u32 saveFDI_RXA_CTL;
410 u32 saveFDI_TXA_CTL;
411 u32 saveFDI_RXB_CTL;
412 u32 saveFDI_TXB_CTL;
413 u32 savePFA_CTL_1;
414 u32 savePFB_CTL_1;
415 u32 savePFA_WIN_SZ;
416 u32 savePFB_WIN_SZ;
417 u32 savePFA_WIN_POS;
418 u32 savePFB_WIN_POS;
419 u32 savePCH_DREF_CONTROL;
420 u32 saveDISP_ARB_CTL;
421 u32 savePIPEA_DATA_M1;
422 u32 savePIPEA_DATA_N1;
423 u32 savePIPEA_LINK_M1;
424 u32 savePIPEA_LINK_N1;
425 u32 savePIPEB_DATA_M1;
426 u32 savePIPEB_DATA_N1;
427 u32 savePIPEB_LINK_M1;
428 u32 savePIPEB_LINK_N1;
429
430 struct {
431 struct drm_mm gtt_space;
432
433 struct io_mapping *gtt_mapping;
434 int gtt_mtrr;
435
436
437
438
439
440
441
442
443 struct list_head shrink_list;
444
445
446
447
448
449
450
451
452
453
454
455 spinlock_t active_list_lock;
456 struct list_head active_list;
457
458
459
460
461
462
463
464
465
466
467 struct list_head flushing_list;
468
469
470
471
472
473
474
475
476
477
478
479 struct list_head inactive_list;
480
481
482 struct list_head fence_list;
483
484
485
486
487
488 struct list_head request_list;
489
490
491
492
493
494
495
496
497 struct delayed_work retire_work;
498
499 uint32_t next_gem_seqno;
500
501
502
503
504 uint32_t waiting_gem_seqno;
505
506
507
508
509 uint32_t irq_gem_seqno;
510
511
512
513
514
515
516
517
518
519 int suspended;
520
521
522
523
524
525
526
527
528 atomic_t wedged;
529
530
531 uint32_t bit_6_swizzle_x;
532
533 uint32_t bit_6_swizzle_y;
534
535
536 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
537 } mm;
538 struct sdvo_device_mapping sdvo_mappings[2];
539
540 unsigned int lvds_border_bits;
541
542
543 bool render_reclock_avail;
544 bool lvds_downclock_avail;
545 struct work_struct idle_work;
546 struct timer_list idle_timer;
547 bool busy;
548 u16 orig_clock;
549} drm_i915_private_t;
550
551
552struct drm_i915_gem_object {
553 struct drm_gem_object *obj;
554
555
556 struct drm_mm_node *gtt_space;
557
558
559 struct list_head list;
560
561
562 struct list_head fence_list;
563
564
565
566
567
568
569 int active;
570
571
572
573
574
575 int dirty;
576
577
578 DRM_AGP_MEM *agp_mem;
579
580 struct page **pages;
581 int pages_refcount;
582
583
584
585
586
587
588 uint32_t gtt_offset;
589
590
591
592
593 uint64_t mmap_offset;
594
595
596
597
598
599
600 int fence_reg;
601
602
603 int pin_count;
604
605
606 uint32_t last_rendering_seqno;
607
608
609 uint32_t tiling_mode;
610 uint32_t stride;
611
612
613 long *bit_17;
614
615
616 uint32_t agp_type;
617
618
619
620
621
622 uint8_t *page_cpu_valid;
623
624
625 uint32_t user_pin_count;
626 struct drm_file *pin_filp;
627
628
629 struct drm_i915_gem_phys_object *phys_obj;
630
631
632
633
634
635 int in_execbuffer;
636
637
638
639
640 int madv;
641};
642
643
644
645
646
647
648
649
650
651
652
653struct drm_i915_gem_request {
654
655 uint32_t seqno;
656
657
658 unsigned long emitted_jiffies;
659
660
661 struct list_head list;
662
663
664 struct list_head client_list;
665};
666
667struct drm_i915_file_private {
668 struct {
669 struct list_head request_list;
670 } mm;
671};
672
673enum intel_chip_family {
674 CHIP_I8XX = 0x01,
675 CHIP_I9XX = 0x02,
676 CHIP_I915 = 0x04,
677 CHIP_I965 = 0x08,
678};
679
680extern struct drm_ioctl_desc i915_ioctls[];
681extern int i915_max_ioctl;
682extern unsigned int i915_fbpercrtc;
683extern unsigned int i915_powersave;
684
685extern void i915_save_display(struct drm_device *dev);
686extern void i915_restore_display(struct drm_device *dev);
687extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
688extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
689
690
691extern void i915_kernel_lost_context(struct drm_device * dev);
692extern int i915_driver_load(struct drm_device *, unsigned long flags);
693extern int i915_driver_unload(struct drm_device *);
694extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
695extern void i915_driver_lastclose(struct drm_device * dev);
696extern void i915_driver_preclose(struct drm_device *dev,
697 struct drm_file *file_priv);
698extern void i915_driver_postclose(struct drm_device *dev,
699 struct drm_file *file_priv);
700extern int i915_driver_device_is_agp(struct drm_device * dev);
701extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
702 unsigned long arg);
703extern int i915_emit_box(struct drm_device *dev,
704 struct drm_clip_rect *boxes,
705 int i, int DR1, int DR4);
706extern int i965_reset(struct drm_device *dev, u8 flags);
707
708
709void i915_hangcheck_elapsed(unsigned long data);
710extern int i915_irq_emit(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
712extern int i915_irq_wait(struct drm_device *dev, void *data,
713 struct drm_file *file_priv);
714void i915_user_irq_get(struct drm_device *dev);
715void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
716void i915_user_irq_put(struct drm_device *dev);
717extern void i915_enable_interrupt (struct drm_device *dev);
718
719extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
720extern void i915_driver_irq_preinstall(struct drm_device * dev);
721extern int i915_driver_irq_postinstall(struct drm_device *dev);
722extern void i915_driver_irq_uninstall(struct drm_device * dev);
723extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
724 struct drm_file *file_priv);
725extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
726 struct drm_file *file_priv);
727extern int i915_enable_vblank(struct drm_device *dev, int crtc);
728extern void i915_disable_vblank(struct drm_device *dev, int crtc);
729extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
730extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
731extern int i915_vblank_swap(struct drm_device *dev, void *data,
732 struct drm_file *file_priv);
733extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
734
735void
736i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
737
738void
739i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
740
741
742
743extern int i915_mem_alloc(struct drm_device *dev, void *data,
744 struct drm_file *file_priv);
745extern int i915_mem_free(struct drm_device *dev, void *data,
746 struct drm_file *file_priv);
747extern int i915_mem_init_heap(struct drm_device *dev, void *data,
748 struct drm_file *file_priv);
749extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
750 struct drm_file *file_priv);
751extern void i915_mem_takedown(struct mem_block **heap);
752extern void i915_mem_release(struct drm_device * dev,
753 struct drm_file *file_priv, struct mem_block *heap);
754
755int i915_gem_init_ioctl(struct drm_device *dev, void *data,
756 struct drm_file *file_priv);
757int i915_gem_create_ioctl(struct drm_device *dev, void *data,
758 struct drm_file *file_priv);
759int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
760 struct drm_file *file_priv);
761int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
762 struct drm_file *file_priv);
763int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
764 struct drm_file *file_priv);
765int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
766 struct drm_file *file_priv);
767int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
768 struct drm_file *file_priv);
769int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
770 struct drm_file *file_priv);
771int i915_gem_execbuffer(struct drm_device *dev, void *data,
772 struct drm_file *file_priv);
773int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
774 struct drm_file *file_priv);
775int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
776 struct drm_file *file_priv);
777int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
778 struct drm_file *file_priv);
779int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
780 struct drm_file *file_priv);
781int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
782 struct drm_file *file_priv);
783int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
784 struct drm_file *file_priv);
785int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
786 struct drm_file *file_priv);
787int i915_gem_set_tiling(struct drm_device *dev, void *data,
788 struct drm_file *file_priv);
789int i915_gem_get_tiling(struct drm_device *dev, void *data,
790 struct drm_file *file_priv);
791int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
792 struct drm_file *file_priv);
793void i915_gem_load(struct drm_device *dev);
794int i915_gem_init_object(struct drm_gem_object *obj);
795void i915_gem_free_object(struct drm_gem_object *obj);
796int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
797void i915_gem_object_unpin(struct drm_gem_object *obj);
798int i915_gem_object_unbind(struct drm_gem_object *obj);
799void i915_gem_release_mmap(struct drm_gem_object *obj);
800void i915_gem_lastclose(struct drm_device *dev);
801uint32_t i915_get_gem_seqno(struct drm_device *dev);
802bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
803int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
804int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
805void i915_gem_retire_requests(struct drm_device *dev);
806void i915_gem_retire_work_handler(struct work_struct *work);
807void i915_gem_clflush_object(struct drm_gem_object *obj);
808int i915_gem_object_set_domain(struct drm_gem_object *obj,
809 uint32_t read_domains,
810 uint32_t write_domain);
811int i915_gem_init_ringbuffer(struct drm_device *dev);
812void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
813int i915_gem_do_init(struct drm_device *dev, unsigned long start,
814 unsigned long end);
815int i915_gem_idle(struct drm_device *dev);
816int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
817int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
818 int write);
819int i915_gem_attach_phys_object(struct drm_device *dev,
820 struct drm_gem_object *obj, int id);
821void i915_gem_detach_phys_object(struct drm_device *dev,
822 struct drm_gem_object *obj);
823void i915_gem_free_all_phys_object(struct drm_device *dev);
824int i915_gem_object_get_pages(struct drm_gem_object *obj);
825void i915_gem_object_put_pages(struct drm_gem_object *obj);
826void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
827
828void i915_gem_shrinker_init(void);
829void i915_gem_shrinker_exit(void);
830
831
832void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
833void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
834void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
835
836
837void i915_gem_dump_object(struct drm_gem_object *obj, int len,
838 const char *where, uint32_t mark);
839#if WATCH_INACTIVE
840void i915_verify_inactive(struct drm_device *dev, char *file, int line);
841#else
842#define i915_verify_inactive(dev, file, line)
843#endif
844void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
845void i915_gem_dump_object(struct drm_gem_object *obj, int len,
846 const char *where, uint32_t mark);
847void i915_dump_lru(struct drm_device *dev, const char *where);
848
849
850int i915_debugfs_init(struct drm_minor *minor);
851void i915_debugfs_cleanup(struct drm_minor *minor);
852
853
854extern int i915_save_state(struct drm_device *dev);
855extern int i915_restore_state(struct drm_device *dev);
856
857
858extern int i915_save_state(struct drm_device *dev);
859extern int i915_restore_state(struct drm_device *dev);
860
861#ifdef CONFIG_ACPI
862
863extern int intel_opregion_init(struct drm_device *dev, int resume);
864extern void intel_opregion_free(struct drm_device *dev, int suspend);
865extern void opregion_asle_intr(struct drm_device *dev);
866extern void opregion_enable_asle(struct drm_device *dev);
867#else
868static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
869static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
870static inline void opregion_asle_intr(struct drm_device *dev) { return; }
871static inline void opregion_enable_asle(struct drm_device *dev) { return; }
872#endif
873
874
875extern void intel_modeset_init(struct drm_device *dev);
876extern void intel_modeset_cleanup(struct drm_device *dev);
877extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
878extern void i8xx_disable_fbc(struct drm_device *dev);
879extern void g4x_disable_fbc(struct drm_device *dev);
880
881
882
883
884
885
886
887#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
888 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
889 LOCK_TEST_WITH_RETURN(dev, file_priv); \
890} while (0)
891
892#define I915_READ(reg) readl(dev_priv->regs + (reg))
893#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
894#define I915_READ16(reg) readw(dev_priv->regs + (reg))
895#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
896#define I915_READ8(reg) readb(dev_priv->regs + (reg))
897#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
898#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
899#define I915_READ64(reg) readq(dev_priv->regs + (reg))
900#define POSTING_READ(reg) (void)I915_READ(reg)
901
902#define I915_VERBOSE 0
903
904#define RING_LOCALS volatile unsigned int *ring_virt__;
905
906#define BEGIN_LP_RING(n) do { \
907 int bytes__ = 4*(n); \
908 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
909 \
910 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
911 i915_wrap_ring(dev); \
912 if (unlikely (dev_priv->ring.space < bytes__)) \
913 i915_wait_ring(dev, bytes__, __func__); \
914 ring_virt__ = (unsigned int *) \
915 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
916 dev_priv->ring.tail += bytes__; \
917 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
918 dev_priv->ring.space -= bytes__; \
919} while (0)
920
921#define OUT_RING(n) do { \
922 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
923 *ring_virt__++ = (n); \
924} while (0)
925
926#define ADVANCE_LP_RING() do { \
927 if (I915_VERBOSE) \
928 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
929 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
930} while(0)
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
948#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
949#define I915_GEM_HWS_INDEX 0x20
950#define I915_BREADCRUMB_INDEX 0x21
951
952extern int i915_wrap_ring(struct drm_device * dev);
953extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
954
955#define IS_I830(dev) ((dev)->pci_device == 0x3577)
956#define IS_845G(dev) ((dev)->pci_device == 0x2562)
957#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
958#define IS_I855(dev) ((dev)->pci_device == 0x3582)
959#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
960
961#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
962#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
963#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
964#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
965 (dev)->pci_device == 0x27AE)
966#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
967 (dev)->pci_device == 0x2982 || \
968 (dev)->pci_device == 0x2992 || \
969 (dev)->pci_device == 0x29A2 || \
970 (dev)->pci_device == 0x2A02 || \
971 (dev)->pci_device == 0x2A12 || \
972 (dev)->pci_device == 0x2A42 || \
973 (dev)->pci_device == 0x2E02 || \
974 (dev)->pci_device == 0x2E12 || \
975 (dev)->pci_device == 0x2E22 || \
976 (dev)->pci_device == 0x2E32 || \
977 (dev)->pci_device == 0x2E42 || \
978 (dev)->pci_device == 0x0042 || \
979 (dev)->pci_device == 0x0046)
980
981#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
982 (dev)->pci_device == 0x2A12)
983
984#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
985
986#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
987 (dev)->pci_device == 0x2E12 || \
988 (dev)->pci_device == 0x2E22 || \
989 (dev)->pci_device == 0x2E32 || \
990 (dev)->pci_device == 0x2E42 || \
991 IS_GM45(dev))
992
993#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
994#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
995#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
996
997#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
998 (dev)->pci_device == 0x29B2 || \
999 (dev)->pci_device == 0x29D2 || \
1000 (IS_IGD(dev)))
1001
1002#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
1003#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
1004#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
1005
1006#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1007 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1008 IS_IGDNG(dev))
1009
1010#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1011 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1012 IS_IGD(dev) || IS_IGDNG_M(dev))
1013
1014#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1015 IS_IGDNG(dev))
1016
1017
1018
1019#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1020 IS_I915GM(dev)))
1021#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1022#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1023#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
1024#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1025
1026#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1027
1028#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
1029#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1030#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1031 (IS_I9XX(dev) || IS_GM45(dev)) && \
1032 !IS_IGD(dev) && \
1033 !IS_IGDNG(dev))
1034
1035#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1036
1037#endif
1038