1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include <linux/module.h>
28#include <linux/input.h>
29#include <linux/i2c.h>
30#include <linux/kernel.h>
31#include "drmP.h"
32#include "intel_drv.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35#include "intel_dp.h"
36
37#include "drm_crtc_helper.h"
38
39#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
41bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42static void intel_update_watermarks(struct drm_device *dev);
43static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
44
45typedef struct {
46
47 int n;
48 int m1, m2;
49 int p1, p2;
50
51 int dot;
52 int vco;
53 int m;
54 int p;
55} intel_clock_t;
56
57typedef struct {
58 int min, max;
59} intel_range_t;
60
61typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64} intel_p2_t;
65
66#define INTEL_P2_NUM 2
67typedef struct intel_limit intel_limit_t;
68struct intel_limit {
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75};
76
77#define I8XX_DOT_MIN 25000
78#define I8XX_DOT_MAX 350000
79#define I8XX_VCO_MIN 930000
80#define I8XX_VCO_MAX 1400000
81#define I8XX_N_MIN 3
82#define I8XX_N_MAX 16
83#define I8XX_M_MIN 96
84#define I8XX_M_MAX 140
85#define I8XX_M1_MIN 18
86#define I8XX_M1_MAX 26
87#define I8XX_M2_MIN 6
88#define I8XX_M2_MAX 16
89#define I8XX_P_MIN 4
90#define I8XX_P_MAX 128
91#define I8XX_P1_MIN 2
92#define I8XX_P1_MAX 33
93#define I8XX_P1_LVDS_MIN 1
94#define I8XX_P1_LVDS_MAX 6
95#define I8XX_P2_SLOW 4
96#define I8XX_P2_FAST 2
97#define I8XX_P2_LVDS_SLOW 14
98#define I8XX_P2_LVDS_FAST 7
99#define I8XX_P2_SLOW_LIMIT 165000
100
101#define I9XX_DOT_MIN 20000
102#define I9XX_DOT_MAX 400000
103#define I9XX_VCO_MIN 1400000
104#define I9XX_VCO_MAX 2800000
105#define IGD_VCO_MIN 1700000
106#define IGD_VCO_MAX 3500000
107#define I9XX_N_MIN 1
108#define I9XX_N_MAX 6
109
110#define IGD_N_MIN 3
111#define IGD_N_MAX 6
112#define I9XX_M_MIN 70
113#define I9XX_M_MAX 120
114#define IGD_M_MIN 2
115#define IGD_M_MAX 256
116#define I9XX_M1_MIN 10
117#define I9XX_M1_MAX 22
118#define I9XX_M2_MIN 5
119#define I9XX_M2_MAX 9
120
121#define IGD_M1_MIN 0
122#define IGD_M1_MAX 0
123#define IGD_M2_MIN 0
124#define IGD_M2_MAX 254
125#define I9XX_P_SDVO_DAC_MIN 5
126#define I9XX_P_SDVO_DAC_MAX 80
127#define I9XX_P_LVDS_MIN 7
128#define I9XX_P_LVDS_MAX 98
129#define IGD_P_LVDS_MIN 7
130#define IGD_P_LVDS_MAX 112
131#define I9XX_P1_MIN 1
132#define I9XX_P1_MAX 8
133#define I9XX_P2_SDVO_DAC_SLOW 10
134#define I9XX_P2_SDVO_DAC_FAST 5
135#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
136#define I9XX_P2_LVDS_SLOW 14
137#define I9XX_P2_LVDS_FAST 7
138#define I9XX_P2_LVDS_SLOW_LIMIT 112000
139
140
141#define G4X_DOT_SDVO_MIN 25000
142#define G4X_DOT_SDVO_MAX 270000
143#define G4X_VCO_MIN 1750000
144#define G4X_VCO_MAX 3500000
145#define G4X_N_SDVO_MIN 1
146#define G4X_N_SDVO_MAX 4
147#define G4X_M_SDVO_MIN 104
148#define G4X_M_SDVO_MAX 138
149#define G4X_M1_SDVO_MIN 17
150#define G4X_M1_SDVO_MAX 23
151#define G4X_M2_SDVO_MIN 5
152#define G4X_M2_SDVO_MAX 11
153#define G4X_P_SDVO_MIN 10
154#define G4X_P_SDVO_MAX 30
155#define G4X_P1_SDVO_MIN 1
156#define G4X_P1_SDVO_MAX 3
157#define G4X_P2_SDVO_SLOW 10
158#define G4X_P2_SDVO_FAST 10
159#define G4X_P2_SDVO_LIMIT 270000
160
161
162#define G4X_DOT_HDMI_DAC_MIN 22000
163#define G4X_DOT_HDMI_DAC_MAX 400000
164#define G4X_N_HDMI_DAC_MIN 1
165#define G4X_N_HDMI_DAC_MAX 4
166#define G4X_M_HDMI_DAC_MIN 104
167#define G4X_M_HDMI_DAC_MAX 138
168#define G4X_M1_HDMI_DAC_MIN 16
169#define G4X_M1_HDMI_DAC_MAX 23
170#define G4X_M2_HDMI_DAC_MIN 5
171#define G4X_M2_HDMI_DAC_MAX 11
172#define G4X_P_HDMI_DAC_MIN 5
173#define G4X_P_HDMI_DAC_MAX 80
174#define G4X_P1_HDMI_DAC_MIN 1
175#define G4X_P1_HDMI_DAC_MAX 8
176#define G4X_P2_HDMI_DAC_SLOW 10
177#define G4X_P2_HDMI_DAC_FAST 5
178#define G4X_P2_HDMI_DAC_LIMIT 165000
179
180
181#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
182#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
183#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
184#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
185#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
186#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
187#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
188#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
189#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
190#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
191#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
192#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
193#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
194#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
195#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
196#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
197#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198
199
200#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
201#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
202#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
203#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
204#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
205#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
206#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
207#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
208#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
209#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
210#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
211#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
212#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
213#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
214#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
215#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
216#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217
218
219#define G4X_DOT_DISPLAY_PORT_MIN 161670
220#define G4X_DOT_DISPLAY_PORT_MAX 227000
221#define G4X_N_DISPLAY_PORT_MIN 1
222#define G4X_N_DISPLAY_PORT_MAX 2
223#define G4X_M_DISPLAY_PORT_MIN 97
224#define G4X_M_DISPLAY_PORT_MAX 108
225#define G4X_M1_DISPLAY_PORT_MIN 0x10
226#define G4X_M1_DISPLAY_PORT_MAX 0x12
227#define G4X_M2_DISPLAY_PORT_MIN 0x05
228#define G4X_M2_DISPLAY_PORT_MAX 0x06
229#define G4X_P_DISPLAY_PORT_MIN 10
230#define G4X_P_DISPLAY_PORT_MAX 20
231#define G4X_P1_DISPLAY_PORT_MIN 1
232#define G4X_P1_DISPLAY_PORT_MAX 2
233#define G4X_P2_DISPLAY_PORT_SLOW 10
234#define G4X_P2_DISPLAY_PORT_FAST 10
235#define G4X_P2_DISPLAY_PORT_LIMIT 0
236
237
238
239
240
241#define IGDNG_DOT_MIN 25000
242#define IGDNG_DOT_MAX 350000
243#define IGDNG_VCO_MIN 1760000
244#define IGDNG_VCO_MAX 3510000
245#define IGDNG_N_MIN 1
246#define IGDNG_N_MAX 5
247#define IGDNG_M_MIN 79
248#define IGDNG_M_MAX 118
249#define IGDNG_M1_MIN 12
250#define IGDNG_M1_MAX 23
251#define IGDNG_M2_MIN 5
252#define IGDNG_M2_MAX 9
253#define IGDNG_P_SDVO_DAC_MIN 5
254#define IGDNG_P_SDVO_DAC_MAX 80
255#define IGDNG_P_LVDS_MIN 28
256#define IGDNG_P_LVDS_MAX 112
257#define IGDNG_P1_MIN 1
258#define IGDNG_P1_MAX 8
259#define IGDNG_P2_SDVO_DAC_SLOW 10
260#define IGDNG_P2_SDVO_DAC_FAST 5
261#define IGDNG_P2_LVDS_SLOW 14
262#define IGDNG_P2_LVDS_FAST 7
263#define IGDNG_P2_DOT_LIMIT 225000
264
265static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock);
268static bool
269intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271static bool
272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock);
274static bool
275intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277
278static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock);
281static bool
282intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock);
284
285static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
287 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
288 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
289 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
290 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
291 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
292 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
293 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
298};
299
300static const intel_limit_t intel_limits_i8xx_lvds = {
301 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
302 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
303 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
304 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
305 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
306 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
307 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
308 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
313};
314
315static const intel_limit_t intel_limits_i9xx_sdvo = {
316 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
317 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
318 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
319 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
320 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
321 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
322 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
323 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
328};
329
330static const intel_limit_t intel_limits_i9xx_lvds = {
331 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
332 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
333 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
334 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
335 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
336 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
337 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
338 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
339
340
341
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
346};
347
348
349static const intel_limit_t intel_limits_g4x_sdvo = {
350 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
351 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
352 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
353 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
354 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
355 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
356 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
357 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
358 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
359 .p2_slow = G4X_P2_SDVO_SLOW,
360 .p2_fast = G4X_P2_SDVO_FAST
361 },
362 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
364};
365
366static const intel_limit_t intel_limits_g4x_hdmi = {
367 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
368 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
369 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
370 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
371 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
372 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
373 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
374 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
375 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
376 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
377 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 },
379 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
381};
382
383static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
384 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
385 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
386 .vco = { .min = G4X_VCO_MIN,
387 .max = G4X_VCO_MAX },
388 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
390 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
392 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
394 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
395 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
396 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
397 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
398 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
399 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
400 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
401 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 },
404 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
406};
407
408static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
409 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
410 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
411 .vco = { .min = G4X_VCO_MIN,
412 .max = G4X_VCO_MAX },
413 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
414 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
415 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
416 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
417 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
418 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
419 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
420 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
421 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
422 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
423 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
424 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
425 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
426 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 },
429 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
431};
432
433static const intel_limit_t intel_limits_g4x_display_port = {
434 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
435 .max = G4X_DOT_DISPLAY_PORT_MAX },
436 .vco = { .min = G4X_VCO_MIN,
437 .max = G4X_VCO_MAX},
438 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
439 .max = G4X_N_DISPLAY_PORT_MAX },
440 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
441 .max = G4X_M_DISPLAY_PORT_MAX },
442 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
443 .max = G4X_M1_DISPLAY_PORT_MAX },
444 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
445 .max = G4X_M2_DISPLAY_PORT_MAX },
446 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
447 .max = G4X_P_DISPLAY_PORT_MAX },
448 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
449 .max = G4X_P1_DISPLAY_PORT_MAX},
450 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
451 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
452 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
453 .find_pll = intel_find_pll_g4x_dp,
454};
455
456static const intel_limit_t intel_limits_igd_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
469};
470
471static const intel_limit_t intel_limits_igd_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
485};
486
487static const intel_limit_t intel_limits_igdng_sdvo = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL,
500};
501
502static const intel_limit_t intel_limits_igdng_lvds = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL,
515};
516
517static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
518{
519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_igdng_lvds;
522 else
523 limit = &intel_limits_igdng_sdvo;
524
525 return limit;
526}
527
528static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
529{
530 struct drm_device *dev = crtc->dev;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 const intel_limit_t *limit;
533
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
535 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 LVDS_CLKB_POWER_UP)
537
538 limit = &intel_limits_g4x_dual_channel_lvds;
539 else
540
541 limit = &intel_limits_g4x_single_channel_lvds;
542 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
543 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
544 limit = &intel_limits_g4x_hdmi;
545 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
546 limit = &intel_limits_g4x_sdvo;
547 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
548 limit = &intel_limits_g4x_display_port;
549 } else
550 limit = &intel_limits_i9xx_sdvo;
551
552 return limit;
553}
554
555static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
556{
557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit;
559
560 if (IS_IGDNG(dev))
561 limit = intel_igdng_limit(crtc);
562 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds;
567 else
568 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds;
572 else
573 limit = &intel_limits_igd_sdvo;
574 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds;
577 else
578 limit = &intel_limits_i8xx_dvo;
579 }
580 return limit;
581}
582
583
584static void igd_clock(int refclk, intel_clock_t *clock)
585{
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 clock->vco = refclk * clock->m / clock->n;
589 clock->dot = clock->vco / clock->p;
590}
591
592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593{
594 if (IS_IGD(dev)) {
595 igd_clock(refclk, clock);
596 return;
597 }
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
599 clock->p = clock->p1 * clock->p2;
600 clock->vco = refclk * clock->m / (clock->n + 2);
601 clock->dot = clock->vco / clock->p;
602}
603
604
605
606
607bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
608{
609 struct drm_device *dev = crtc->dev;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *l_entry;
612
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) {
616 struct intel_output *intel_output = to_intel_output(l_entry);
617 if (intel_output->type == type)
618 return true;
619 }
620 }
621 return false;
622}
623
624struct drm_connector *
625intel_pipe_get_output (struct drm_crtc *crtc)
626{
627 struct drm_device *dev = crtc->dev;
628 struct drm_mode_config *mode_config = &dev->mode_config;
629 struct drm_connector *l_entry, *ret = NULL;
630
631 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
632 if (l_entry->encoder &&
633 l_entry->encoder->crtc == crtc) {
634 ret = l_entry;
635 break;
636 }
637 }
638 return ret;
639}
640
641#define INTELPllInvalid(s) do { return false; } while (0)
642
643
644
645
646
647static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
648{
649 const intel_limit_t *limit = intel_limit (crtc);
650 struct drm_device *dev = crtc->dev;
651
652 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
653 INTELPllInvalid ("p1 out of range\n");
654 if (clock->p < limit->p.min || limit->p.max < clock->p)
655 INTELPllInvalid ("p out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n");
664 if (clock->n < limit->n.min || limit->n.max < clock->n)
665 INTELPllInvalid ("n out of range\n");
666 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
667 INTELPllInvalid ("vco out of range\n");
668
669
670
671 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
672 INTELPllInvalid ("dot out of range\n");
673
674 return true;
675}
676
677static bool
678intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *best_clock)
680
681{
682 struct drm_device *dev = crtc->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 intel_clock_t clock;
685 int err = target;
686
687 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
688 (I915_READ(LVDS)) != 0) {
689
690
691
692
693
694
695 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
696 LVDS_CLKB_POWER_UP)
697 clock.p2 = limit->p2.p2_fast;
698 else
699 clock.p2 = limit->p2.p2_slow;
700 } else {
701 if (target < limit->p2.dot_limit)
702 clock.p2 = limit->p2.p2_slow;
703 else
704 clock.p2 = limit->p2.p2_fast;
705 }
706
707 memset (best_clock, 0, sizeof (*best_clock));
708
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
711 clock.m1++) {
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
716 break;
717 for (clock.n = limit->n.min;
718 clock.n <= limit->n.max; clock.n++) {
719 int this_err;
720
721 intel_clock(dev, refclk, &clock);
722
723 if (!intel_PLL_is_valid(crtc, &clock))
724 continue;
725
726 this_err = abs(clock.dot - target);
727 if (this_err < err) {
728 *best_clock = clock;
729 err = this_err;
730 }
731 }
732 }
733 }
734 }
735
736 return (err != target);
737}
738
739
740static bool
741intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *best_clock)
743
744{
745 struct drm_device *dev = crtc->dev;
746 intel_clock_t clock;
747 int err = target;
748 bool found = false;
749
750 memcpy(&clock, best_clock, sizeof(intel_clock_t));
751
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
756 break;
757 for (clock.n = limit->n.min; clock.n <= limit->n.max;
758 clock.n++) {
759 int this_err;
760
761 intel_clock(dev, refclk, &clock);
762
763 if (!intel_PLL_is_valid(crtc, &clock))
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 found = true;
771 }
772 }
773 }
774 }
775
776 return found;
777}
778
779static bool
780intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
781 int target, int refclk, intel_clock_t *best_clock)
782{
783 struct drm_device *dev = crtc->dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 intel_clock_t clock;
786 int max_n;
787 bool found;
788
789 int err_most = (target >> 8) + (target >> 10);
790 found = false;
791
792 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
793 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
794 LVDS_CLKB_POWER_UP)
795 clock.p2 = limit->p2.p2_fast;
796 else
797 clock.p2 = limit->p2.p2_slow;
798 } else {
799 if (target < limit->p2.dot_limit)
800 clock.p2 = limit->p2.p2_slow;
801 else
802 clock.p2 = limit->p2.p2_fast;
803 }
804
805 memset(best_clock, 0, sizeof(*best_clock));
806 max_n = limit->n.max;
807
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 intel_clock(dev, refclk, &clock);
819 if (!intel_PLL_is_valid(crtc, &clock))
820 continue;
821 this_err = abs(clock.dot - target) ;
822 if (this_err < err_most) {
823 *best_clock = clock;
824 err_most = this_err;
825 max_n = clock.n;
826 found = true;
827 }
828 }
829 }
830 }
831 }
832 return found;
833}
834
835static bool
836intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock)
838{
839 struct drm_device *dev = crtc->dev;
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.n = 1;
843 clock.p1 = 2;
844 clock.p2 = 10;
845 clock.m1 = 12;
846 clock.m2 = 9;
847 } else {
848 clock.n = 2;
849 clock.p1 = 1;
850 clock.p2 = 10;
851 clock.m1 = 14;
852 clock.m2 = 8;
853 }
854 intel_clock(dev, refclk, &clock);
855 memcpy(best_clock, &clock, sizeof(intel_clock_t));
856 return true;
857}
858
859static bool
860intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862{
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int err_most = 47;
867 int err_min = 10000;
868
869
870 if (HAS_eDP)
871 return true;
872
873 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
874 return intel_find_pll_igdng_dp(limit, crtc, target,
875 refclk, best_clock);
876
877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
878 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
879 LVDS_CLKB_POWER_UP)
880 clock.p2 = limit->p2.p2_fast;
881 else
882 clock.p2 = limit->p2.p2_slow;
883 } else {
884 if (target < limit->p2.dot_limit)
885 clock.p2 = limit->p2.p2_slow;
886 else
887 clock.p2 = limit->p2.p2_fast;
888 }
889
890 memset(best_clock, 0, sizeof(*best_clock));
891 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
892
893 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
894
895 for (clock.m1 = limit->m1.max;
896 clock.m1 >= limit->m1.min; clock.m1--) {
897 for (clock.m2 = limit->m2.max;
898 clock.m2 >= limit->m2.min; clock.m2--) {
899 int this_err;
900
901 intel_clock(dev, refclk, &clock);
902 if (!intel_PLL_is_valid(crtc, &clock))
903 continue;
904 this_err = abs((10000 - (target*10000/clock.dot)));
905 if (this_err < err_most) {
906 *best_clock = clock;
907
908 goto out;
909 } else if (this_err < err_min) {
910 *best_clock = clock;
911 err_min = this_err;
912 }
913 }
914 }
915 }
916 }
917out:
918 return true;
919}
920
921
922static bool
923intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
924 int target, int refclk, intel_clock_t *best_clock)
925{
926 intel_clock_t clock;
927 if (target < 200000) {
928 clock.p1 = 2;
929 clock.p2 = 10;
930 clock.n = 2;
931 clock.m1 = 23;
932 clock.m2 = 8;
933 } else {
934 clock.p1 = 1;
935 clock.p2 = 10;
936 clock.n = 1;
937 clock.m1 = 14;
938 clock.m2 = 2;
939 }
940 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
941 clock.p = (clock.p1 * clock.p2);
942 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
943 clock.vco = 0;
944 memcpy(best_clock, &clock, sizeof(intel_clock_t));
945 return true;
946}
947
948void
949intel_wait_for_vblank(struct drm_device *dev)
950{
951
952 mdelay(20);
953}
954
955
956static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
957{
958 struct drm_device *dev = crtc->dev;
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 struct drm_framebuffer *fb = crtc->fb;
961 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
962 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
964 int plane, i;
965 u32 fbc_ctl, fbc_ctl2;
966
967 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
968
969 if (fb->pitch < dev_priv->cfb_pitch)
970 dev_priv->cfb_pitch = fb->pitch;
971
972
973 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
974 dev_priv->cfb_fence = obj_priv->fence_reg;
975 dev_priv->cfb_plane = intel_crtc->plane;
976 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
977
978
979 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
980 I915_WRITE(FBC_TAG + (i * 4), 0);
981
982
983 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
984 if (obj_priv->tiling_mode != I915_TILING_NONE)
985 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
986 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
987 I915_WRITE(FBC_FENCE_OFF, crtc->y);
988
989
990 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
991 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
992 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
993 if (obj_priv->tiling_mode != I915_TILING_NONE)
994 fbc_ctl |= dev_priv->cfb_fence;
995 I915_WRITE(FBC_CONTROL, fbc_ctl);
996
997 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
998 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
999}
1000
1001void i8xx_disable_fbc(struct drm_device *dev)
1002{
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 u32 fbc_ctl;
1005
1006 if (!I915_HAS_FBC(dev))
1007 return;
1008
1009
1010 fbc_ctl = I915_READ(FBC_CONTROL);
1011 fbc_ctl &= ~FBC_CTL_EN;
1012 I915_WRITE(FBC_CONTROL, fbc_ctl);
1013
1014
1015 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1016 ;
1017
1018 intel_wait_for_vblank(dev);
1019
1020 DRM_DEBUG("disabled FBC\n");
1021}
1022
1023static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1024{
1025 struct drm_device *dev = crtc->dev;
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027
1028 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1029}
1030
1031static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1032{
1033 struct drm_device *dev = crtc->dev;
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 struct drm_framebuffer *fb = crtc->fb;
1036 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1040 DPFC_CTL_PLANEB);
1041 unsigned long stall_watermark = 200;
1042 u32 dpfc_ctl;
1043
1044 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1045 dev_priv->cfb_fence = obj_priv->fence_reg;
1046 dev_priv->cfb_plane = intel_crtc->plane;
1047
1048 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1049 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1050 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1051 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1052 } else {
1053 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1054 }
1055
1056 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1057 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1058 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1059 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1060 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1061
1062
1063 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1064
1065 DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1066}
1067
1068void g4x_disable_fbc(struct drm_device *dev)
1069{
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 u32 dpfc_ctl;
1072
1073
1074 dpfc_ctl = I915_READ(DPFC_CONTROL);
1075 dpfc_ctl &= ~DPFC_CTL_EN;
1076 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1077 intel_wait_for_vblank(dev);
1078
1079 DRM_DEBUG("disabled FBC\n");
1080}
1081
1082static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1083{
1084 struct drm_device *dev = crtc->dev;
1085 struct drm_i915_private *dev_priv = dev->dev_private;
1086
1087 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1088}
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110static void intel_update_fbc(struct drm_crtc *crtc,
1111 struct drm_display_mode *mode)
1112{
1113 struct drm_device *dev = crtc->dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 struct drm_framebuffer *fb = crtc->fb;
1116 struct intel_framebuffer *intel_fb;
1117 struct drm_i915_gem_object *obj_priv;
1118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1119 int plane = intel_crtc->plane;
1120
1121 if (!i915_powersave)
1122 return;
1123
1124 if (!dev_priv->display.fbc_enabled ||
1125 !dev_priv->display.enable_fbc ||
1126 !dev_priv->display.disable_fbc)
1127 return;
1128
1129 if (!crtc->fb)
1130 return;
1131
1132 intel_fb = to_intel_framebuffer(fb);
1133 obj_priv = intel_fb->obj->driver_private;
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143 if (intel_fb->obj->size > dev_priv->cfb_size) {
1144 DRM_DEBUG("framebuffer too large, disabling compression\n");
1145 goto out_disable;
1146 }
1147 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1148 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1149 DRM_DEBUG("mode incompatible with compression, disabling\n");
1150 goto out_disable;
1151 }
1152 if ((mode->hdisplay > 2048) ||
1153 (mode->vdisplay > 1536)) {
1154 DRM_DEBUG("mode too large for compression, disabling\n");
1155 goto out_disable;
1156 }
1157 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1158 DRM_DEBUG("plane not 0, disabling compression\n");
1159 goto out_disable;
1160 }
1161 if (obj_priv->tiling_mode != I915_TILING_X) {
1162 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1163 goto out_disable;
1164 }
1165
1166 if (dev_priv->display.fbc_enabled(crtc)) {
1167
1168 if (fb->pitch > dev_priv->cfb_pitch)
1169 dev_priv->display.disable_fbc(dev);
1170 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1171 dev_priv->display.disable_fbc(dev);
1172 if (plane != dev_priv->cfb_plane)
1173 dev_priv->display.disable_fbc(dev);
1174 }
1175
1176 if (!dev_priv->display.fbc_enabled(crtc)) {
1177
1178 dev_priv->display.enable_fbc(crtc, 500);
1179 }
1180
1181 return;
1182
1183out_disable:
1184 DRM_DEBUG("unsupported config, disabling FBC\n");
1185
1186 if (dev_priv->display.fbc_enabled(crtc))
1187 dev_priv->display.disable_fbc(dev);
1188}
1189
1190static int
1191intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1192 struct drm_framebuffer *old_fb)
1193{
1194 struct drm_device *dev = crtc->dev;
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 struct drm_i915_master_private *master_priv;
1197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1198 struct intel_framebuffer *intel_fb;
1199 struct drm_i915_gem_object *obj_priv;
1200 struct drm_gem_object *obj;
1201 int pipe = intel_crtc->pipe;
1202 int plane = intel_crtc->plane;
1203 unsigned long Start, Offset;
1204 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1205 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1206 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1207 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1208 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1209 u32 dspcntr, alignment;
1210 int ret;
1211
1212
1213 if (!crtc->fb) {
1214 DRM_DEBUG("No FB bound\n");
1215 return 0;
1216 }
1217
1218 switch (plane) {
1219 case 0:
1220 case 1:
1221 break;
1222 default:
1223 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1224 return -EINVAL;
1225 }
1226
1227 intel_fb = to_intel_framebuffer(crtc->fb);
1228 obj = intel_fb->obj;
1229 obj_priv = obj->driver_private;
1230
1231 switch (obj_priv->tiling_mode) {
1232 case I915_TILING_NONE:
1233 alignment = 64 * 1024;
1234 break;
1235 case I915_TILING_X:
1236
1237 alignment = 0;
1238 break;
1239 case I915_TILING_Y:
1240
1241 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1242 return -EINVAL;
1243 default:
1244 BUG();
1245 }
1246
1247 mutex_lock(&dev->struct_mutex);
1248 ret = i915_gem_object_pin(obj, alignment);
1249 if (ret != 0) {
1250 mutex_unlock(&dev->struct_mutex);
1251 return ret;
1252 }
1253
1254 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1255 if (ret != 0) {
1256 i915_gem_object_unpin(obj);
1257 mutex_unlock(&dev->struct_mutex);
1258 return ret;
1259 }
1260
1261
1262
1263
1264
1265 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266 obj_priv->tiling_mode != I915_TILING_NONE) {
1267 ret = i915_gem_object_get_fence_reg(obj);
1268 if (ret != 0) {
1269 i915_gem_object_unpin(obj);
1270 mutex_unlock(&dev->struct_mutex);
1271 return ret;
1272 }
1273 }
1274
1275 dspcntr = I915_READ(dspcntr_reg);
1276
1277 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1278 switch (crtc->fb->bits_per_pixel) {
1279 case 8:
1280 dspcntr |= DISPPLANE_8BPP;
1281 break;
1282 case 16:
1283 if (crtc->fb->depth == 15)
1284 dspcntr |= DISPPLANE_15_16BPP;
1285 else
1286 dspcntr |= DISPPLANE_16BPP;
1287 break;
1288 case 24:
1289 case 32:
1290 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291 break;
1292 default:
1293 DRM_ERROR("Unknown color depth\n");
1294 i915_gem_object_unpin(obj);
1295 mutex_unlock(&dev->struct_mutex);
1296 return -EINVAL;
1297 }
1298 if (IS_I965G(dev)) {
1299 if (obj_priv->tiling_mode != I915_TILING_NONE)
1300 dspcntr |= DISPPLANE_TILED;
1301 else
1302 dspcntr &= ~DISPPLANE_TILED;
1303 }
1304
1305 if (IS_IGDNG(dev))
1306
1307 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308
1309 I915_WRITE(dspcntr_reg, dspcntr);
1310
1311 Start = obj_priv->gtt_offset;
1312 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313
1314 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1315 I915_WRITE(dspstride, crtc->fb->pitch);
1316 if (IS_I965G(dev)) {
1317 I915_WRITE(dspbase, Offset);
1318 I915_READ(dspbase);
1319 I915_WRITE(dspsurf, Start);
1320 I915_READ(dspsurf);
1321 I915_WRITE(dsptileoff, (y << 16) | x);
1322 } else {
1323 I915_WRITE(dspbase, Start + Offset);
1324 I915_READ(dspbase);
1325 }
1326
1327 if ((IS_I965G(dev) || plane == 0))
1328 intel_update_fbc(crtc, &crtc->mode);
1329
1330 intel_wait_for_vblank(dev);
1331
1332 if (old_fb) {
1333 intel_fb = to_intel_framebuffer(old_fb);
1334 obj_priv = intel_fb->obj->driver_private;
1335 i915_gem_object_unpin(intel_fb->obj);
1336 }
1337 intel_increase_pllclock(crtc, true);
1338
1339 mutex_unlock(&dev->struct_mutex);
1340
1341 if (!dev->primary->master)
1342 return 0;
1343
1344 master_priv = dev->primary->master->driver_priv;
1345 if (!master_priv->sarea_priv)
1346 return 0;
1347
1348 if (pipe) {
1349 master_priv->sarea_priv->pipeB_x = x;
1350 master_priv->sarea_priv->pipeB_y = y;
1351 } else {
1352 master_priv->sarea_priv->pipeA_x = x;
1353 master_priv->sarea_priv->pipeA_y = y;
1354 }
1355
1356 return 0;
1357}
1358
1359
1360static void i915_disable_vga (struct drm_device *dev)
1361{
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 u8 sr1;
1364 u32 vga_reg;
1365
1366 if (IS_IGDNG(dev))
1367 vga_reg = CPU_VGACNTRL;
1368 else
1369 vga_reg = VGACNTRL;
1370
1371 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1372 return;
1373
1374 I915_WRITE8(VGA_SR_INDEX, 1);
1375 sr1 = I915_READ8(VGA_SR_DATA);
1376 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1377 udelay(100);
1378
1379 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380}
1381
1382static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1383{
1384 struct drm_device *dev = crtc->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 dpa_ctl;
1387
1388 DRM_DEBUG("\n");
1389 dpa_ctl = I915_READ(DP_A);
1390 dpa_ctl &= ~DP_PLL_ENABLE;
1391 I915_WRITE(DP_A, dpa_ctl);
1392}
1393
1394static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1395{
1396 struct drm_device *dev = crtc->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 u32 dpa_ctl;
1399
1400 dpa_ctl = I915_READ(DP_A);
1401 dpa_ctl |= DP_PLL_ENABLE;
1402 I915_WRITE(DP_A, dpa_ctl);
1403 udelay(200);
1404}
1405
1406
1407static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1408{
1409 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl;
1412
1413 DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1414 dpa_ctl = I915_READ(DP_A);
1415 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416
1417 if (clock < 200000) {
1418 u32 temp;
1419 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1420
1421
1422
1423
1424
1425
1426 temp = I915_READ(0x4600c);
1427 temp &= 0xffff0000;
1428 I915_WRITE(0x4600c, temp | 0x8124);
1429
1430 temp = I915_READ(0x46010);
1431 I915_WRITE(0x46010, temp | 1);
1432
1433 temp = I915_READ(0x46034);
1434 I915_WRITE(0x46034, temp | (1 << 24));
1435 } else {
1436 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1437 }
1438 I915_WRITE(DP_A, dpa_ctl);
1439
1440 udelay(500);
1441}
1442
1443static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1444{
1445 struct drm_device *dev = crtc->dev;
1446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448 int pipe = intel_crtc->pipe;
1449 int plane = intel_crtc->plane;
1450 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1451 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1452 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1453 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1454 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1455 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1456 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1457 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1458 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1459 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1460 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1461 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1462 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1463 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1464 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1465 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1466 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1467 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1468 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1469 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1470 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1471 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1472 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1473 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1474 u32 temp;
1475 int tries = 5, j, n;
1476
1477
1478
1479
1480 switch (mode) {
1481 case DRM_MODE_DPMS_ON:
1482 case DRM_MODE_DPMS_STANDBY:
1483 case DRM_MODE_DPMS_SUSPEND:
1484 DRM_DEBUG("crtc %d dpms on\n", pipe);
1485 if (HAS_eDP) {
1486
1487 igdng_enable_pll_edp(crtc);
1488 } else {
1489
1490 temp = I915_READ(pch_dpll_reg);
1491 if ((temp & DPLL_VCO_ENABLE) == 0) {
1492 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1493 I915_READ(pch_dpll_reg);
1494 }
1495
1496
1497 temp = I915_READ(fdi_rx_reg);
1498 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1499 FDI_SEL_PCDCLK |
1500 FDI_DP_PORT_WIDTH_X4);
1501 I915_READ(fdi_rx_reg);
1502 udelay(200);
1503
1504
1505 temp = I915_READ(fdi_tx_reg);
1506 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1507 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1508 I915_READ(fdi_tx_reg);
1509 udelay(100);
1510 }
1511 }
1512
1513
1514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1515 temp = I915_READ(pf_ctl_reg);
1516 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1517
1518
1519 I915_WRITE(pf_win_pos, 0);
1520
1521 I915_WRITE(pf_win_size,
1522 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1523 (dev_priv->panel_fixed_mode->vdisplay));
1524 }
1525
1526
1527 temp = I915_READ(pipeconf_reg);
1528 if ((temp & PIPEACONF_ENABLE) == 0) {
1529 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1530 I915_READ(pipeconf_reg);
1531 udelay(100);
1532 }
1533
1534
1535 temp = I915_READ(dspcntr_reg);
1536 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1537 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1538
1539 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1540 }
1541
1542 if (!HAS_eDP) {
1543
1544 temp = I915_READ(fdi_tx_reg);
1545 temp |= FDI_TX_ENABLE;
1546 temp |= FDI_DP_PORT_WIDTH_X4;
1547 temp &= ~FDI_LINK_TRAIN_NONE;
1548 temp |= FDI_LINK_TRAIN_PATTERN_1;
1549 I915_WRITE(fdi_tx_reg, temp);
1550 I915_READ(fdi_tx_reg);
1551
1552 temp = I915_READ(fdi_rx_reg);
1553 temp &= ~FDI_LINK_TRAIN_NONE;
1554 temp |= FDI_LINK_TRAIN_PATTERN_1;
1555 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1556 I915_READ(fdi_rx_reg);
1557
1558 udelay(150);
1559
1560
1561
1562
1563 temp = I915_READ(fdi_rx_imr_reg);
1564 temp &= ~FDI_RX_SYMBOL_LOCK;
1565 temp &= ~FDI_RX_BIT_LOCK;
1566 I915_WRITE(fdi_rx_imr_reg, temp);
1567 I915_READ(fdi_rx_imr_reg);
1568 udelay(150);
1569
1570 temp = I915_READ(fdi_rx_iir_reg);
1571 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1572
1573 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1574 for (j = 0; j < tries; j++) {
1575 temp = I915_READ(fdi_rx_iir_reg);
1576 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1577 if (temp & FDI_RX_BIT_LOCK)
1578 break;
1579 udelay(200);
1580 }
1581 if (j != tries)
1582 I915_WRITE(fdi_rx_iir_reg,
1583 temp | FDI_RX_BIT_LOCK);
1584 else
1585 DRM_DEBUG("train 1 fail\n");
1586 } else {
1587 I915_WRITE(fdi_rx_iir_reg,
1588 temp | FDI_RX_BIT_LOCK);
1589 DRM_DEBUG("train 1 ok 2!\n");
1590 }
1591 temp = I915_READ(fdi_tx_reg);
1592 temp &= ~FDI_LINK_TRAIN_NONE;
1593 temp |= FDI_LINK_TRAIN_PATTERN_2;
1594 I915_WRITE(fdi_tx_reg, temp);
1595
1596 temp = I915_READ(fdi_rx_reg);
1597 temp &= ~FDI_LINK_TRAIN_NONE;
1598 temp |= FDI_LINK_TRAIN_PATTERN_2;
1599 I915_WRITE(fdi_rx_reg, temp);
1600
1601 udelay(150);
1602
1603 temp = I915_READ(fdi_rx_iir_reg);
1604 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1605
1606 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1607 for (j = 0; j < tries; j++) {
1608 temp = I915_READ(fdi_rx_iir_reg);
1609 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1610 if (temp & FDI_RX_SYMBOL_LOCK)
1611 break;
1612 udelay(200);
1613 }
1614 if (j != tries) {
1615 I915_WRITE(fdi_rx_iir_reg,
1616 temp | FDI_RX_SYMBOL_LOCK);
1617 DRM_DEBUG("train 2 ok 1!\n");
1618 } else
1619 DRM_DEBUG("train 2 fail\n");
1620 } else {
1621 I915_WRITE(fdi_rx_iir_reg,
1622 temp | FDI_RX_SYMBOL_LOCK);
1623 DRM_DEBUG("train 2 ok 2!\n");
1624 }
1625 DRM_DEBUG("train done\n");
1626
1627
1628 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1629 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1630 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1631
1632 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1633 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1634 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1635
1636
1637 temp = I915_READ(transconf_reg);
1638 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1639 I915_READ(transconf_reg);
1640
1641 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1642 ;
1643
1644
1645
1646 temp = I915_READ(fdi_tx_reg);
1647 temp &= ~FDI_LINK_TRAIN_NONE;
1648 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1649 FDI_TX_ENHANCE_FRAME_ENABLE);
1650 I915_READ(fdi_tx_reg);
1651
1652 temp = I915_READ(fdi_rx_reg);
1653 temp &= ~FDI_LINK_TRAIN_NONE;
1654 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1655 FDI_RX_ENHANCE_FRAME_ENABLE);
1656 I915_READ(fdi_rx_reg);
1657
1658
1659 udelay(100);
1660
1661 }
1662
1663 intel_crtc_load_lut(crtc);
1664
1665 break;
1666 case DRM_MODE_DPMS_OFF:
1667 DRM_DEBUG("crtc %d dpms off\n", pipe);
1668
1669 i915_disable_vga(dev);
1670
1671
1672 temp = I915_READ(dspcntr_reg);
1673 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1674 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1675
1676 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1677 I915_READ(dspbase_reg);
1678 }
1679
1680
1681 temp = I915_READ(pipeconf_reg);
1682 if ((temp & PIPEACONF_ENABLE) != 0) {
1683 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1684 I915_READ(pipeconf_reg);
1685 n = 0;
1686
1687 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1688 n++;
1689 if (n < 60) {
1690 udelay(500);
1691 continue;
1692 } else {
1693 DRM_DEBUG("pipe %d off delay\n", pipe);
1694 break;
1695 }
1696 }
1697 } else
1698 DRM_DEBUG("crtc %d is disabled\n", pipe);
1699
1700 if (HAS_eDP) {
1701 igdng_disable_pll_edp(crtc);
1702 }
1703
1704
1705 temp = I915_READ(fdi_tx_reg);
1706 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1707 I915_READ(fdi_tx_reg);
1708
1709 temp = I915_READ(fdi_rx_reg);
1710 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1711 I915_READ(fdi_rx_reg);
1712
1713 udelay(100);
1714
1715
1716 temp = I915_READ(fdi_tx_reg);
1717 temp &= ~FDI_LINK_TRAIN_NONE;
1718 temp |= FDI_LINK_TRAIN_PATTERN_1;
1719 I915_WRITE(fdi_tx_reg, temp);
1720
1721 temp = I915_READ(fdi_rx_reg);
1722 temp &= ~FDI_LINK_TRAIN_NONE;
1723 temp |= FDI_LINK_TRAIN_PATTERN_1;
1724 I915_WRITE(fdi_rx_reg, temp);
1725
1726 udelay(100);
1727
1728
1729 temp = I915_READ(transconf_reg);
1730 if ((temp & TRANS_ENABLE) != 0) {
1731 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1732 I915_READ(transconf_reg);
1733 n = 0;
1734
1735 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1736 n++;
1737 if (n < 60) {
1738 udelay(500);
1739 continue;
1740 } else {
1741 DRM_DEBUG("transcoder %d off delay\n", pipe);
1742 break;
1743 }
1744 }
1745 }
1746
1747
1748 temp = I915_READ(pch_dpll_reg);
1749 if ((temp & DPLL_VCO_ENABLE) != 0) {
1750 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1751 I915_READ(pch_dpll_reg);
1752 }
1753
1754 temp = I915_READ(fdi_rx_reg);
1755 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1756 temp &= ~FDI_SEL_PCDCLK;
1757 temp &= ~FDI_RX_PLL_ENABLE;
1758 I915_WRITE(fdi_rx_reg, temp);
1759 I915_READ(fdi_rx_reg);
1760 }
1761
1762
1763 temp = I915_READ(fdi_tx_reg);
1764 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1765 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1766 I915_READ(fdi_tx_reg);
1767 udelay(100);
1768 }
1769
1770
1771 temp = I915_READ(pf_ctl_reg);
1772 if ((temp & PF_ENABLE) != 0) {
1773 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1774 I915_READ(pf_ctl_reg);
1775 }
1776 I915_WRITE(pf_win_size, 0);
1777
1778
1779 udelay(150);
1780 break;
1781 }
1782}
1783
1784static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1785{
1786 struct drm_device *dev = crtc->dev;
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1789 int pipe = intel_crtc->pipe;
1790 int plane = intel_crtc->plane;
1791 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1792 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1793 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1794 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1795 u32 temp;
1796
1797
1798
1799
1800 switch (mode) {
1801 case DRM_MODE_DPMS_ON:
1802 case DRM_MODE_DPMS_STANDBY:
1803 case DRM_MODE_DPMS_SUSPEND:
1804 intel_update_watermarks(dev);
1805
1806
1807 temp = I915_READ(dpll_reg);
1808 if ((temp & DPLL_VCO_ENABLE) == 0) {
1809 I915_WRITE(dpll_reg, temp);
1810 I915_READ(dpll_reg);
1811
1812 udelay(150);
1813 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1814 I915_READ(dpll_reg);
1815
1816 udelay(150);
1817 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1818 I915_READ(dpll_reg);
1819
1820 udelay(150);
1821 }
1822
1823
1824 temp = I915_READ(pipeconf_reg);
1825 if ((temp & PIPEACONF_ENABLE) == 0)
1826 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1827
1828
1829 temp = I915_READ(dspcntr_reg);
1830 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1831 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1832
1833 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1834 }
1835
1836 intel_crtc_load_lut(crtc);
1837
1838 if ((IS_I965G(dev) || plane == 0))
1839 intel_update_fbc(crtc, &crtc->mode);
1840
1841
1842
1843 break;
1844 case DRM_MODE_DPMS_OFF:
1845 intel_update_watermarks(dev);
1846
1847
1848
1849 if (dev_priv->cfb_plane == plane &&
1850 dev_priv->display.disable_fbc)
1851 dev_priv->display.disable_fbc(dev);
1852
1853
1854 i915_disable_vga(dev);
1855
1856
1857 temp = I915_READ(dspcntr_reg);
1858 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1859 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1860
1861 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1862 I915_READ(dspbase_reg);
1863 }
1864
1865 if (!IS_I9XX(dev)) {
1866
1867 intel_wait_for_vblank(dev);
1868 }
1869
1870
1871 temp = I915_READ(pipeconf_reg);
1872 if ((temp & PIPEACONF_ENABLE) != 0) {
1873 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1874 I915_READ(pipeconf_reg);
1875 }
1876
1877
1878 intel_wait_for_vblank(dev);
1879
1880 temp = I915_READ(dpll_reg);
1881 if ((temp & DPLL_VCO_ENABLE) != 0) {
1882 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1883 I915_READ(dpll_reg);
1884 }
1885
1886
1887 udelay(150);
1888 break;
1889 }
1890}
1891
1892
1893
1894
1895
1896
1897
1898static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1899{
1900 struct drm_device *dev = crtc->dev;
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902 struct drm_i915_master_private *master_priv;
1903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1904 int pipe = intel_crtc->pipe;
1905 bool enabled;
1906
1907 dev_priv->display.dpms(crtc, mode);
1908
1909 intel_crtc->dpms_mode = mode;
1910
1911 if (!dev->primary->master)
1912 return;
1913
1914 master_priv = dev->primary->master->driver_priv;
1915 if (!master_priv->sarea_priv)
1916 return;
1917
1918 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1919
1920 switch (pipe) {
1921 case 0:
1922 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1923 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1924 break;
1925 case 1:
1926 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1927 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1928 break;
1929 default:
1930 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1931 break;
1932 }
1933}
1934
1935static void intel_crtc_prepare (struct drm_crtc *crtc)
1936{
1937 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1938 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1939}
1940
1941static void intel_crtc_commit (struct drm_crtc *crtc)
1942{
1943 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1944 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1945}
1946
1947void intel_encoder_prepare (struct drm_encoder *encoder)
1948{
1949 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1950
1951 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1952}
1953
1954void intel_encoder_commit (struct drm_encoder *encoder)
1955{
1956 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1957
1958 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1959}
1960
1961static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1962 struct drm_display_mode *mode,
1963 struct drm_display_mode *adjusted_mode)
1964{
1965 struct drm_device *dev = crtc->dev;
1966 if (IS_IGDNG(dev)) {
1967
1968 if (mode->clock * 3 > 27000 * 4)
1969 return MODE_CLOCK_HIGH;
1970 }
1971 return true;
1972}
1973
1974static int i945_get_display_clock_speed(struct drm_device *dev)
1975{
1976 return 400000;
1977}
1978
1979static int i915_get_display_clock_speed(struct drm_device *dev)
1980{
1981 return 333000;
1982}
1983
1984static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1985{
1986 return 200000;
1987}
1988
1989static int i915gm_get_display_clock_speed(struct drm_device *dev)
1990{
1991 u16 gcfgc = 0;
1992
1993 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1994
1995 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1996 return 133000;
1997 else {
1998 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1999 case GC_DISPLAY_CLOCK_333_MHZ:
2000 return 333000;
2001 default:
2002 case GC_DISPLAY_CLOCK_190_200_MHZ:
2003 return 190000;
2004 }
2005 }
2006}
2007
2008static int i865_get_display_clock_speed(struct drm_device *dev)
2009{
2010 return 266000;
2011}
2012
2013static int i855_get_display_clock_speed(struct drm_device *dev)
2014{
2015 u16 hpllcc = 0;
2016
2017
2018
2019 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2020 case GC_CLOCK_133_200:
2021 case GC_CLOCK_100_200:
2022 return 200000;
2023 case GC_CLOCK_166_250:
2024 return 250000;
2025 case GC_CLOCK_100_133:
2026 return 133000;
2027 }
2028
2029
2030 return 0;
2031}
2032
2033static int i830_get_display_clock_speed(struct drm_device *dev)
2034{
2035 return 133000;
2036}
2037
2038
2039
2040
2041
2042static int intel_panel_fitter_pipe (struct drm_device *dev)
2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 u32 pfit_control;
2046
2047
2048 if (IS_I830(dev))
2049 return -1;
2050
2051 pfit_control = I915_READ(PFIT_CONTROL);
2052
2053
2054 if ((pfit_control & PFIT_ENABLE) == 0)
2055 return -1;
2056
2057
2058 if (IS_I965G(dev))
2059 return (pfit_control >> 29) & 0x3;
2060
2061
2062 return 1;
2063}
2064
2065struct fdi_m_n {
2066 u32 tu;
2067 u32 gmch_m;
2068 u32 gmch_n;
2069 u32 link_m;
2070 u32 link_n;
2071};
2072
2073static void
2074fdi_reduce_ratio(u32 *num, u32 *den)
2075{
2076 while (*num > 0xffffff || *den > 0xffffff) {
2077 *num >>= 1;
2078 *den >>= 1;
2079 }
2080}
2081
2082#define DATA_N 0x800000
2083#define LINK_N 0x80000
2084
2085static void
2086igdng_compute_m_n(int bits_per_pixel, int nlanes,
2087 int pixel_clock, int link_clock,
2088 struct fdi_m_n *m_n)
2089{
2090 u64 temp;
2091
2092 m_n->tu = 64;
2093
2094 temp = (u64) DATA_N * pixel_clock;
2095 temp = div_u64(temp, link_clock);
2096 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2097 m_n->gmch_m >>= 3;
2098 m_n->gmch_n = DATA_N;
2099 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2100
2101 temp = (u64) LINK_N * pixel_clock;
2102 m_n->link_m = div_u64(temp, link_clock);
2103 m_n->link_n = LINK_N;
2104 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2105}
2106
2107
2108struct intel_watermark_params {
2109 unsigned long fifo_size;
2110 unsigned long max_wm;
2111 unsigned long default_wm;
2112 unsigned long guard_size;
2113 unsigned long cacheline_size;
2114};
2115
2116
2117static struct intel_watermark_params igd_display_wm = {
2118 IGD_DISPLAY_FIFO,
2119 IGD_MAX_WM,
2120 IGD_DFT_WM,
2121 IGD_GUARD_WM,
2122 IGD_FIFO_LINE_SIZE
2123};
2124static struct intel_watermark_params igd_display_hplloff_wm = {
2125 IGD_DISPLAY_FIFO,
2126 IGD_MAX_WM,
2127 IGD_DFT_HPLLOFF_WM,
2128 IGD_GUARD_WM,
2129 IGD_FIFO_LINE_SIZE
2130};
2131static struct intel_watermark_params igd_cursor_wm = {
2132 IGD_CURSOR_FIFO,
2133 IGD_CURSOR_MAX_WM,
2134 IGD_CURSOR_DFT_WM,
2135 IGD_CURSOR_GUARD_WM,
2136 IGD_FIFO_LINE_SIZE,
2137};
2138static struct intel_watermark_params igd_cursor_hplloff_wm = {
2139 IGD_CURSOR_FIFO,
2140 IGD_CURSOR_MAX_WM,
2141 IGD_CURSOR_DFT_WM,
2142 IGD_CURSOR_GUARD_WM,
2143 IGD_FIFO_LINE_SIZE
2144};
2145static struct intel_watermark_params g4x_wm_info = {
2146 G4X_FIFO_SIZE,
2147 G4X_MAX_WM,
2148 G4X_MAX_WM,
2149 2,
2150 G4X_FIFO_LINE_SIZE,
2151};
2152static struct intel_watermark_params i945_wm_info = {
2153 I945_FIFO_SIZE,
2154 I915_MAX_WM,
2155 1,
2156 2,
2157 I915_FIFO_LINE_SIZE
2158};
2159static struct intel_watermark_params i915_wm_info = {
2160 I915_FIFO_SIZE,
2161 I915_MAX_WM,
2162 1,
2163 2,
2164 I915_FIFO_LINE_SIZE
2165};
2166static struct intel_watermark_params i855_wm_info = {
2167 I855GM_FIFO_SIZE,
2168 I915_MAX_WM,
2169 1,
2170 2,
2171 I830_FIFO_LINE_SIZE
2172};
2173static struct intel_watermark_params i830_wm_info = {
2174 I830_FIFO_SIZE,
2175 I915_MAX_WM,
2176 1,
2177 2,
2178 I830_FIFO_LINE_SIZE
2179};
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2200 struct intel_watermark_params *wm,
2201 int pixel_size,
2202 unsigned long latency_ns)
2203{
2204 long entries_required, wm_size;
2205
2206
2207
2208
2209
2210
2211
2212 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2213 1000;
2214 entries_required /= wm->cacheline_size;
2215
2216 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2217
2218 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2219
2220 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2221
2222
2223 if (wm_size > (long)wm->max_wm)
2224 wm_size = wm->max_wm;
2225 if (wm_size <= 0)
2226 wm_size = wm->default_wm;
2227 return wm_size;
2228}
2229
2230struct cxsr_latency {
2231 int is_desktop;
2232 unsigned long fsb_freq;
2233 unsigned long mem_freq;
2234 unsigned long display_sr;
2235 unsigned long display_hpll_disable;
2236 unsigned long cursor_sr;
2237 unsigned long cursor_hpll_disable;
2238};
2239
2240static struct cxsr_latency cxsr_latency_table[] = {
2241 {1, 800, 400, 3382, 33382, 3983, 33983},
2242 {1, 800, 667, 3354, 33354, 3807, 33807},
2243 {1, 800, 800, 3347, 33347, 3763, 33763},
2244
2245 {1, 667, 400, 3400, 33400, 4021, 34021},
2246 {1, 667, 667, 3372, 33372, 3845, 33845},
2247 {1, 667, 800, 3386, 33386, 3822, 33822},
2248
2249 {1, 400, 400, 3472, 33472, 4173, 34173},
2250 {1, 400, 667, 3443, 33443, 3996, 33996},
2251 {1, 400, 800, 3430, 33430, 3946, 33946},
2252
2253 {0, 800, 400, 3438, 33438, 4065, 34065},
2254 {0, 800, 667, 3410, 33410, 3889, 33889},
2255 {0, 800, 800, 3403, 33403, 3845, 33845},
2256
2257 {0, 667, 400, 3456, 33456, 4103, 34106},
2258 {0, 667, 667, 3428, 33428, 3927, 33927},
2259 {0, 667, 800, 3443, 33443, 3905, 33905},
2260
2261 {0, 400, 400, 3528, 33528, 4255, 34255},
2262 {0, 400, 667, 3500, 33500, 4079, 34079},
2263 {0, 400, 800, 3487, 33487, 4029, 34029},
2264};
2265
2266static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2267 int mem)
2268{
2269 int i;
2270 struct cxsr_latency *latency;
2271
2272 if (fsb == 0 || mem == 0)
2273 return NULL;
2274
2275 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2276 latency = &cxsr_latency_table[i];
2277 if (is_desktop == latency->is_desktop &&
2278 fsb == latency->fsb_freq && mem == latency->mem_freq)
2279 return latency;
2280 }
2281
2282 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2283
2284 return NULL;
2285}
2286
2287static void igd_disable_cxsr(struct drm_device *dev)
2288{
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 u32 reg;
2291
2292
2293 reg = I915_READ(DSPFW3);
2294 reg &= ~(IGD_SELF_REFRESH_EN);
2295 I915_WRITE(DSPFW3, reg);
2296 DRM_INFO("Big FIFO is disabled\n");
2297}
2298
2299static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2300 int pixel_size)
2301{
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 u32 reg;
2304 unsigned long wm;
2305 struct cxsr_latency *latency;
2306
2307 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2308 dev_priv->mem_freq);
2309 if (!latency) {
2310 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2311 igd_disable_cxsr(dev);
2312 return;
2313 }
2314
2315
2316 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2317 latency->display_sr);
2318 reg = I915_READ(DSPFW1);
2319 reg &= 0x7fffff;
2320 reg |= wm << 23;
2321 I915_WRITE(DSPFW1, reg);
2322 DRM_DEBUG("DSPFW1 register is %x\n", reg);
2323
2324
2325 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2326 latency->cursor_sr);
2327 reg = I915_READ(DSPFW3);
2328 reg &= ~(0x3f << 24);
2329 reg |= (wm & 0x3f) << 24;
2330 I915_WRITE(DSPFW3, reg);
2331
2332
2333 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2334 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2335 reg = I915_READ(DSPFW3);
2336 reg &= 0xfffffe00;
2337 reg |= wm & 0x1ff;
2338 I915_WRITE(DSPFW3, reg);
2339
2340
2341 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2342 latency->cursor_hpll_disable);
2343 reg = I915_READ(DSPFW3);
2344 reg &= ~(0x3f << 16);
2345 reg |= (wm & 0x3f) << 16;
2346 I915_WRITE(DSPFW3, reg);
2347 DRM_DEBUG("DSPFW3 register is %x\n", reg);
2348
2349
2350 reg = I915_READ(DSPFW3);
2351 reg |= IGD_SELF_REFRESH_EN;
2352 I915_WRITE(DSPFW3, reg);
2353
2354 DRM_INFO("Big FIFO is enabled\n");
2355
2356 return;
2357}
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373const static int latency_ns = 5000;
2374
2375static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2376{
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 uint32_t dsparb = I915_READ(DSPARB);
2379 int size;
2380
2381 if (plane == 0)
2382 size = dsparb & 0x7f;
2383 else
2384 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2385 (dsparb & 0x7f);
2386
2387 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2388 size);
2389
2390 return size;
2391}
2392
2393static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2394{
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396 uint32_t dsparb = I915_READ(DSPARB);
2397 int size;
2398
2399 if (plane == 0)
2400 size = dsparb & 0x1ff;
2401 else
2402 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2403 (dsparb & 0x1ff);
2404 size >>= 1;
2405
2406 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2407 size);
2408
2409 return size;
2410}
2411
2412static int i845_get_fifo_size(struct drm_device *dev, int plane)
2413{
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415 uint32_t dsparb = I915_READ(DSPARB);
2416 int size;
2417
2418 size = dsparb & 0x7f;
2419 size >>= 2;
2420
2421 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2422 size);
2423
2424 return size;
2425}
2426
2427static int i830_get_fifo_size(struct drm_device *dev, int plane)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 uint32_t dsparb = I915_READ(DSPARB);
2431 int size;
2432
2433 size = dsparb & 0x7f;
2434 size >>= 1;
2435
2436 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2437 size);
2438
2439 return size;
2440}
2441
2442static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2443 int planeb_clock, int sr_hdisplay, int pixel_size)
2444{
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 int total_size, cacheline_size;
2447 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2448 struct intel_watermark_params planea_params, planeb_params;
2449 unsigned long line_time_us;
2450 int sr_clock, sr_entries = 0, entries_required;
2451
2452
2453 planea_params = planeb_params = g4x_wm_info;
2454
2455
2456 total_size = planea_params.fifo_size;
2457 cacheline_size = planea_params.cacheline_size;
2458
2459
2460
2461
2462
2463
2464
2465 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2466 1000;
2467 entries_required /= G4X_FIFO_LINE_SIZE;
2468 planea_wm = entries_required + planea_params.guard_size;
2469
2470 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2471 1000;
2472 entries_required /= G4X_FIFO_LINE_SIZE;
2473 planeb_wm = entries_required + planeb_params.guard_size;
2474
2475 cursora_wm = cursorb_wm = 16;
2476 cursor_sr = 32;
2477
2478 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2479
2480
2481 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2482
2483 const static int sr_latency_ns = 12000;
2484
2485 sr_clock = planea_clock ? planea_clock : planeb_clock;
2486 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2487
2488
2489 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2490 pixel_size * sr_hdisplay) / 1000;
2491 sr_entries = roundup(sr_entries / cacheline_size, 1);
2492 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2493 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2494 }
2495
2496 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2497 planea_wm, planeb_wm, sr_entries);
2498
2499 planea_wm &= 0x3f;
2500 planeb_wm &= 0x3f;
2501
2502 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2503 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2504 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2505 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2506 (cursora_wm << DSPFW_CURSORA_SHIFT));
2507
2508 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2509 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2510}
2511
2512static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2513 int unused3, int unused4)
2514{
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516
2517 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2518
2519
2520 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2521 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2522}
2523
2524static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2525 int planeb_clock, int sr_hdisplay, int pixel_size)
2526{
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528 uint32_t fwater_lo;
2529 uint32_t fwater_hi;
2530 int total_size, cacheline_size, cwm, srwm = 1;
2531 int planea_wm, planeb_wm;
2532 struct intel_watermark_params planea_params, planeb_params;
2533 unsigned long line_time_us;
2534 int sr_clock, sr_entries = 0;
2535
2536
2537 if (IS_I965GM(dev) || IS_I945GM(dev))
2538 planea_params = planeb_params = i945_wm_info;
2539 else if (IS_I9XX(dev))
2540 planea_params = planeb_params = i915_wm_info;
2541 else
2542 planea_params = planeb_params = i855_wm_info;
2543
2544
2545 total_size = planea_params.fifo_size;
2546 cacheline_size = planea_params.cacheline_size;
2547
2548
2549 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2550 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2551
2552 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2553 pixel_size, latency_ns);
2554 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2555 pixel_size, latency_ns);
2556 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2557
2558
2559
2560
2561 cwm = 2;
2562
2563
2564 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2565 (!planea_clock || !planeb_clock)) {
2566
2567 const static int sr_latency_ns = 6000;
2568
2569 sr_clock = planea_clock ? planea_clock : planeb_clock;
2570 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2571
2572
2573 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2574 pixel_size * sr_hdisplay) / 1000;
2575 sr_entries = roundup(sr_entries / cacheline_size, 1);
2576 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2577 srwm = total_size - sr_entries;
2578 if (srwm < 0)
2579 srwm = 1;
2580 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2581 }
2582
2583 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2584 planea_wm, planeb_wm, cwm, srwm);
2585
2586 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2587 fwater_hi = (cwm & 0x1f);
2588
2589
2590 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2591 fwater_hi = fwater_hi | (1 << 8);
2592
2593 I915_WRITE(FW_BLC, fwater_lo);
2594 I915_WRITE(FW_BLC2, fwater_hi);
2595}
2596
2597static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2598 int unused2, int pixel_size)
2599{
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2602 int planea_wm;
2603
2604 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2605
2606 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2607 pixel_size, latency_ns);
2608 fwater_lo |= (3<<8) | planea_wm;
2609
2610 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2611
2612 I915_WRITE(FW_BLC, fwater_lo);
2613}
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646static void intel_update_watermarks(struct drm_device *dev)
2647{
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct drm_crtc *crtc;
2650 struct intel_crtc *intel_crtc;
2651 int sr_hdisplay = 0;
2652 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2653 int enabled = 0, pixel_size = 0;
2654
2655 if (!dev_priv->display.update_wm)
2656 return;
2657
2658
2659 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2660 intel_crtc = to_intel_crtc(crtc);
2661 if (crtc->enabled) {
2662 enabled++;
2663 if (intel_crtc->plane == 0) {
2664 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2665 intel_crtc->pipe, crtc->mode.clock);
2666 planea_clock = crtc->mode.clock;
2667 } else {
2668 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2669 intel_crtc->pipe, crtc->mode.clock);
2670 planeb_clock = crtc->mode.clock;
2671 }
2672 sr_hdisplay = crtc->mode.hdisplay;
2673 sr_clock = crtc->mode.clock;
2674 if (crtc->fb)
2675 pixel_size = crtc->fb->bits_per_pixel / 8;
2676 else
2677 pixel_size = 4;
2678 }
2679 }
2680
2681 if (enabled <= 0)
2682 return;
2683
2684
2685 if (enabled == 1 && IS_IGD(dev))
2686 igd_enable_cxsr(dev, sr_clock, pixel_size);
2687 else if (IS_IGD(dev))
2688 igd_disable_cxsr(dev);
2689
2690 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2691 sr_hdisplay, pixel_size);
2692}
2693
2694static int intel_crtc_mode_set(struct drm_crtc *crtc,
2695 struct drm_display_mode *mode,
2696 struct drm_display_mode *adjusted_mode,
2697 int x, int y,
2698 struct drm_framebuffer *old_fb)
2699{
2700 struct drm_device *dev = crtc->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 int pipe = intel_crtc->pipe;
2704 int plane = intel_crtc->plane;
2705 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2706 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2707 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2708 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2709 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2710 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2711 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2712 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2713 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2714 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2715 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2716 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2717 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2718 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2719 int refclk, num_outputs = 0;
2720 intel_clock_t clock, reduced_clock;
2721 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2722 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2723 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2724 bool is_edp = false;
2725 struct drm_mode_config *mode_config = &dev->mode_config;
2726 struct drm_connector *connector;
2727 const intel_limit_t *limit;
2728 int ret;
2729 struct fdi_m_n m_n = {0};
2730 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2731 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2732 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2733 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2734 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2735 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2736 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2737 int lvds_reg = LVDS;
2738 u32 temp;
2739 int sdvo_pixel_multiply;
2740 int target_clock;
2741
2742 drm_vblank_pre_modeset(dev, pipe);
2743
2744 list_for_each_entry(connector, &mode_config->connector_list, head) {
2745 struct intel_output *intel_output = to_intel_output(connector);
2746
2747 if (!connector->encoder || connector->encoder->crtc != crtc)
2748 continue;
2749
2750 switch (intel_output->type) {
2751 case INTEL_OUTPUT_LVDS:
2752 is_lvds = true;
2753 break;
2754 case INTEL_OUTPUT_SDVO:
2755 case INTEL_OUTPUT_HDMI:
2756 is_sdvo = true;
2757 if (intel_output->needs_tv_clock)
2758 is_tv = true;
2759 break;
2760 case INTEL_OUTPUT_DVO:
2761 is_dvo = true;
2762 break;
2763 case INTEL_OUTPUT_TVOUT:
2764 is_tv = true;
2765 break;
2766 case INTEL_OUTPUT_ANALOG:
2767 is_crt = true;
2768 break;
2769 case INTEL_OUTPUT_DISPLAYPORT:
2770 is_dp = true;
2771 break;
2772 case INTEL_OUTPUT_EDP:
2773 is_edp = true;
2774 break;
2775 }
2776
2777 num_outputs++;
2778 }
2779
2780 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2781 refclk = dev_priv->lvds_ssc_freq * 1000;
2782 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2783 } else if (IS_I9XX(dev)) {
2784 refclk = 96000;
2785 if (IS_IGDNG(dev))
2786 refclk = 120000;
2787 } else {
2788 refclk = 48000;
2789 }
2790
2791
2792
2793
2794
2795
2796
2797 limit = intel_limit(crtc);
2798 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2799 if (!ok) {
2800 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2801 drm_vblank_post_modeset(dev, pipe);
2802 return -EINVAL;
2803 }
2804
2805 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2806 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2807 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2808 (adjusted_mode->clock*3/4),
2809 refclk,
2810 &reduced_clock);
2811 }
2812
2813
2814
2815 if (is_sdvo && is_tv) {
2816 if (adjusted_mode->clock >= 100000
2817 && adjusted_mode->clock < 140500) {
2818 clock.p1 = 2;
2819 clock.p2 = 10;
2820 clock.n = 3;
2821 clock.m1 = 16;
2822 clock.m2 = 8;
2823 } else if (adjusted_mode->clock >= 140500
2824 && adjusted_mode->clock <= 200000) {
2825 clock.p1 = 1;
2826 clock.p2 = 10;
2827 clock.n = 6;
2828 clock.m1 = 12;
2829 clock.m2 = 8;
2830 }
2831 }
2832
2833
2834 if (IS_IGDNG(dev)) {
2835 int lane, link_bw, bpp;
2836
2837
2838 if (is_edp) {
2839 struct drm_connector *edp;
2840 target_clock = mode->clock;
2841 edp = intel_pipe_get_output(crtc);
2842 intel_edp_link_config(to_intel_output(edp),
2843 &lane, &link_bw);
2844 } else {
2845
2846
2847 if (is_dp)
2848 target_clock = mode->clock;
2849 else
2850 target_clock = adjusted_mode->clock;
2851 lane = 4;
2852 link_bw = 270000;
2853 }
2854
2855
2856 temp = I915_READ(pipeconf_reg);
2857
2858 switch (temp & PIPE_BPC_MASK) {
2859 case PIPE_8BPC:
2860 bpp = 24;
2861 break;
2862 case PIPE_10BPC:
2863 bpp = 30;
2864 break;
2865 case PIPE_6BPC:
2866 bpp = 18;
2867 break;
2868 case PIPE_12BPC:
2869 bpp = 36;
2870 break;
2871 default:
2872 DRM_ERROR("unknown pipe bpc value\n");
2873 bpp = 24;
2874 }
2875
2876 igdng_compute_m_n(bpp, lane, target_clock,
2877 link_bw, &m_n);
2878 }
2879
2880
2881
2882
2883
2884
2885 if (IS_IGDNG(dev)) {
2886 temp = I915_READ(PCH_DREF_CONTROL);
2887
2888 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2889 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2890 I915_WRITE(PCH_DREF_CONTROL, temp);
2891 POSTING_READ(PCH_DREF_CONTROL);
2892
2893 temp &= ~DREF_SSC_SOURCE_MASK;
2894 temp |= DREF_SSC_SOURCE_ENABLE;
2895 I915_WRITE(PCH_DREF_CONTROL, temp);
2896 POSTING_READ(PCH_DREF_CONTROL);
2897
2898 udelay(200);
2899
2900 if (is_edp) {
2901 if (dev_priv->lvds_use_ssc) {
2902 temp |= DREF_SSC1_ENABLE;
2903 I915_WRITE(PCH_DREF_CONTROL, temp);
2904 POSTING_READ(PCH_DREF_CONTROL);
2905
2906 udelay(200);
2907
2908 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2909 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2910 I915_WRITE(PCH_DREF_CONTROL, temp);
2911 POSTING_READ(PCH_DREF_CONTROL);
2912 } else {
2913 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2914 I915_WRITE(PCH_DREF_CONTROL, temp);
2915 POSTING_READ(PCH_DREF_CONTROL);
2916 }
2917 }
2918 }
2919
2920 if (IS_IGD(dev)) {
2921 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2922 if (has_reduced_clock)
2923 fp2 = (1 << reduced_clock.n) << 16 |
2924 reduced_clock.m1 << 8 | reduced_clock.m2;
2925 } else {
2926 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2927 if (has_reduced_clock)
2928 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2929 reduced_clock.m2;
2930 }
2931
2932 if (!IS_IGDNG(dev))
2933 dpll = DPLL_VGA_MODE_DIS;
2934
2935 if (IS_I9XX(dev)) {
2936 if (is_lvds)
2937 dpll |= DPLLB_MODE_LVDS;
2938 else
2939 dpll |= DPLLB_MODE_DAC_SERIAL;
2940 if (is_sdvo) {
2941 dpll |= DPLL_DVO_HIGH_SPEED;
2942 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2943 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2944 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2945 else if (IS_IGDNG(dev))
2946 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2947 }
2948 if (is_dp)
2949 dpll |= DPLL_DVO_HIGH_SPEED;
2950
2951
2952 if (IS_IGD(dev))
2953 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2954 else {
2955 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2956
2957 if (IS_IGDNG(dev))
2958 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2959 if (IS_G4X(dev) && has_reduced_clock)
2960 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2961 }
2962 switch (clock.p2) {
2963 case 5:
2964 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2965 break;
2966 case 7:
2967 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2968 break;
2969 case 10:
2970 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2971 break;
2972 case 14:
2973 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2974 break;
2975 }
2976 if (IS_I965G(dev) && !IS_IGDNG(dev))
2977 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2978 } else {
2979 if (is_lvds) {
2980 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2981 } else {
2982 if (clock.p1 == 2)
2983 dpll |= PLL_P1_DIVIDE_BY_TWO;
2984 else
2985 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2986 if (clock.p2 == 4)
2987 dpll |= PLL_P2_DIVIDE_BY_4;
2988 }
2989 }
2990
2991 if (is_sdvo && is_tv)
2992 dpll |= PLL_REF_INPUT_TVCLKINBC;
2993 else if (is_tv)
2994
2995
2996 dpll |= 3;
2997 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2998 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2999 else
3000 dpll |= PLL_REF_INPUT_DREFCLK;
3001
3002
3003 pipeconf = I915_READ(pipeconf_reg);
3004
3005
3006 dspcntr = DISPPLANE_GAMMA_ENABLE;
3007
3008
3009
3010 if (!IS_IGDNG(dev)) {
3011 if (pipe == 0)
3012 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3013 else
3014 dspcntr |= DISPPLANE_SEL_PIPE_B;
3015 }
3016
3017 if (pipe == 0 && !IS_I965G(dev)) {
3018
3019
3020
3021
3022
3023
3024 if (mode->clock >
3025 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3026 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3027 else
3028 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3029 }
3030
3031 dspcntr |= DISPLAY_PLANE_ENABLE;
3032 pipeconf |= PIPEACONF_ENABLE;
3033 dpll |= DPLL_VCO_ENABLE;
3034
3035
3036
3037 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3038 I915_WRITE(PFIT_CONTROL, 0);
3039
3040 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3041 drm_mode_debug_printmodeline(mode);
3042
3043
3044 if (IS_IGDNG(dev)) {
3045 fp_reg = pch_fp_reg;
3046 dpll_reg = pch_dpll_reg;
3047 }
3048
3049 if (is_edp) {
3050 igdng_disable_pll_edp(crtc);
3051 } else if ((dpll & DPLL_VCO_ENABLE)) {
3052 I915_WRITE(fp_reg, fp);
3053 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3054 I915_READ(dpll_reg);
3055 udelay(150);
3056 }
3057
3058
3059
3060
3061
3062 if (is_lvds) {
3063 u32 lvds;
3064
3065 if (IS_IGDNG(dev))
3066 lvds_reg = PCH_LVDS;
3067
3068 lvds = I915_READ(lvds_reg);
3069 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3070
3071 lvds |= dev_priv->lvds_border_bits;
3072
3073
3074
3075 if (clock.p2 == 7)
3076 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3077 else
3078 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3079
3080
3081
3082
3083
3084
3085 I915_WRITE(lvds_reg, lvds);
3086 I915_READ(lvds_reg);
3087 }
3088 if (is_dp)
3089 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3090
3091 if (!is_edp) {
3092 I915_WRITE(fp_reg, fp);
3093 I915_WRITE(dpll_reg, dpll);
3094 I915_READ(dpll_reg);
3095
3096 udelay(150);
3097
3098 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3099 if (is_sdvo) {
3100 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3101 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3102 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3103 } else
3104 I915_WRITE(dpll_md_reg, 0);
3105 } else {
3106
3107 I915_WRITE(dpll_reg, dpll);
3108 }
3109 I915_READ(dpll_reg);
3110
3111 udelay(150);
3112 }
3113
3114 if (is_lvds && has_reduced_clock && i915_powersave) {
3115 I915_WRITE(fp_reg + 4, fp2);
3116 intel_crtc->lowfreq_avail = true;
3117 if (HAS_PIPE_CXSR(dev)) {
3118 DRM_DEBUG("enabling CxSR downclocking\n");
3119 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3120 }
3121 } else {
3122 I915_WRITE(fp_reg + 4, fp);
3123 intel_crtc->lowfreq_avail = false;
3124 if (HAS_PIPE_CXSR(dev)) {
3125 DRM_DEBUG("disabling CxSR downclocking\n");
3126 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3127 }
3128 }
3129
3130 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3131 ((adjusted_mode->crtc_htotal - 1) << 16));
3132 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3133 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3134 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3135 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3136 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3137 ((adjusted_mode->crtc_vtotal - 1) << 16));
3138 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3139 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3140 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3141 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3142
3143
3144
3145 if (!IS_IGDNG(dev)) {
3146 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3147 (mode->hdisplay - 1));
3148 I915_WRITE(dsppos_reg, 0);
3149 }
3150 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3151
3152 if (IS_IGDNG(dev)) {
3153 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3154 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3155 I915_WRITE(link_m1_reg, m_n.link_m);
3156 I915_WRITE(link_n1_reg, m_n.link_n);
3157
3158 if (is_edp) {
3159 igdng_set_pll_edp(crtc, adjusted_mode->clock);
3160 } else {
3161
3162 temp = I915_READ(fdi_rx_reg);
3163 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3164 udelay(200);
3165 }
3166 }
3167
3168 I915_WRITE(pipeconf_reg, pipeconf);
3169 I915_READ(pipeconf_reg);
3170
3171 intel_wait_for_vblank(dev);
3172
3173 if (IS_IGDNG(dev)) {
3174
3175 temp = I915_READ(DISP_ARB_CTL);
3176 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3177 }
3178
3179 I915_WRITE(dspcntr_reg, dspcntr);
3180
3181
3182 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3183
3184 if ((IS_I965G(dev) || plane == 0))
3185 intel_update_fbc(crtc, &crtc->mode);
3186
3187 intel_update_watermarks(dev);
3188
3189 drm_vblank_post_modeset(dev, pipe);
3190
3191 return ret;
3192}
3193
3194
3195void intel_crtc_load_lut(struct drm_crtc *crtc)
3196{
3197 struct drm_device *dev = crtc->dev;
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3201 int i;
3202
3203
3204 if (!crtc->enabled)
3205 return;
3206
3207
3208 if (IS_IGDNG(dev))
3209 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3210 LGC_PALETTE_B;
3211
3212 for (i = 0; i < 256; i++) {
3213 I915_WRITE(palreg + 4 * i,
3214 (intel_crtc->lut_r[i] << 16) |
3215 (intel_crtc->lut_g[i] << 8) |
3216 intel_crtc->lut_b[i]);
3217 }
3218}
3219
3220static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3221 struct drm_file *file_priv,
3222 uint32_t handle,
3223 uint32_t width, uint32_t height)
3224{
3225 struct drm_device *dev = crtc->dev;
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228 struct drm_gem_object *bo;
3229 struct drm_i915_gem_object *obj_priv;
3230 int pipe = intel_crtc->pipe;
3231 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3232 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3233 uint32_t temp = I915_READ(control);
3234 size_t addr;
3235 int ret;
3236
3237 DRM_DEBUG("\n");
3238
3239
3240 if (!handle) {
3241 DRM_DEBUG("cursor off\n");
3242 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3243 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3244 temp |= CURSOR_MODE_DISABLE;
3245 } else {
3246 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3247 }
3248 addr = 0;
3249 bo = NULL;
3250 mutex_lock(&dev->struct_mutex);
3251 goto finish;
3252 }
3253
3254
3255 if (width != 64 || height != 64) {
3256 DRM_ERROR("we currently only support 64x64 cursors\n");
3257 return -EINVAL;
3258 }
3259
3260 bo = drm_gem_object_lookup(dev, file_priv, handle);
3261 if (!bo)
3262 return -ENOENT;
3263
3264 obj_priv = bo->driver_private;
3265
3266 if (bo->size < width * height * 4) {
3267 DRM_ERROR("buffer is to small\n");
3268 ret = -ENOMEM;
3269 goto fail;
3270 }
3271
3272
3273 mutex_lock(&dev->struct_mutex);
3274 if (!dev_priv->cursor_needs_physical) {
3275 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3276 if (ret) {
3277 DRM_ERROR("failed to pin cursor bo\n");
3278 goto fail_locked;
3279 }
3280 addr = obj_priv->gtt_offset;
3281 } else {
3282 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3283 if (ret) {
3284 DRM_ERROR("failed to attach phys object\n");
3285 goto fail_locked;
3286 }
3287 addr = obj_priv->phys_obj->handle->busaddr;
3288 }
3289
3290 if (!IS_I9XX(dev))
3291 I915_WRITE(CURSIZE, (height << 12) | width);
3292
3293
3294 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3295 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3296 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3297 temp |= (pipe << 28);
3298 } else {
3299 temp &= ~(CURSOR_FORMAT_MASK);
3300 temp |= CURSOR_ENABLE;
3301 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3302 }
3303
3304 finish:
3305 I915_WRITE(control, temp);
3306 I915_WRITE(base, addr);
3307
3308 if (intel_crtc->cursor_bo) {
3309 if (dev_priv->cursor_needs_physical) {
3310 if (intel_crtc->cursor_bo != bo)
3311 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3312 } else
3313 i915_gem_object_unpin(intel_crtc->cursor_bo);
3314 drm_gem_object_unreference(intel_crtc->cursor_bo);
3315 }
3316
3317 mutex_unlock(&dev->struct_mutex);
3318
3319 intel_crtc->cursor_addr = addr;
3320 intel_crtc->cursor_bo = bo;
3321
3322 return 0;
3323fail:
3324 mutex_lock(&dev->struct_mutex);
3325fail_locked:
3326 drm_gem_object_unreference(bo);
3327 mutex_unlock(&dev->struct_mutex);
3328 return ret;
3329}
3330
3331static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3332{
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3336 struct intel_framebuffer *intel_fb;
3337 int pipe = intel_crtc->pipe;
3338 uint32_t temp = 0;
3339 uint32_t adder;
3340
3341 if (crtc->fb) {
3342 intel_fb = to_intel_framebuffer(crtc->fb);
3343 intel_mark_busy(dev, intel_fb->obj);
3344 }
3345
3346 if (x < 0) {
3347 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3348 x = -x;
3349 }
3350 if (y < 0) {
3351 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3352 y = -y;
3353 }
3354
3355 temp |= x << CURSOR_X_SHIFT;
3356 temp |= y << CURSOR_Y_SHIFT;
3357
3358 adder = intel_crtc->cursor_addr;
3359 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3360 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3361
3362 return 0;
3363}
3364
3365
3366void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3367 u16 blue, int regno)
3368{
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370
3371 intel_crtc->lut_r[regno] = red >> 8;
3372 intel_crtc->lut_g[regno] = green >> 8;
3373 intel_crtc->lut_b[regno] = blue >> 8;
3374}
3375
3376void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3377 u16 *blue, int regno)
3378{
3379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3380
3381 *red = intel_crtc->lut_r[regno] << 8;
3382 *green = intel_crtc->lut_g[regno] << 8;
3383 *blue = intel_crtc->lut_b[regno] << 8;
3384}
3385
3386static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3387 u16 *blue, uint32_t size)
3388{
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390 int i;
3391
3392 if (size != 256)
3393 return;
3394
3395 for (i = 0; i < 256; i++) {
3396 intel_crtc->lut_r[i] = red[i] >> 8;
3397 intel_crtc->lut_g[i] = green[i] >> 8;
3398 intel_crtc->lut_b[i] = blue[i] >> 8;
3399 }
3400
3401 intel_crtc_load_lut(crtc);
3402}
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419static struct drm_display_mode load_detect_mode = {
3420 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3421 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3422};
3423
3424struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3425 struct drm_display_mode *mode,
3426 int *dpms_mode)
3427{
3428 struct intel_crtc *intel_crtc;
3429 struct drm_crtc *possible_crtc;
3430 struct drm_crtc *supported_crtc =NULL;
3431 struct drm_encoder *encoder = &intel_output->enc;
3432 struct drm_crtc *crtc = NULL;
3433 struct drm_device *dev = encoder->dev;
3434 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3435 struct drm_crtc_helper_funcs *crtc_funcs;
3436 int i = -1;
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449 if (encoder->crtc) {
3450 crtc = encoder->crtc;
3451
3452 intel_crtc = to_intel_crtc(crtc);
3453 *dpms_mode = intel_crtc->dpms_mode;
3454 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3455 crtc_funcs = crtc->helper_private;
3456 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3457 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3458 }
3459 return crtc;
3460 }
3461
3462
3463 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3464 i++;
3465 if (!(encoder->possible_crtcs & (1 << i)))
3466 continue;
3467 if (!possible_crtc->enabled) {
3468 crtc = possible_crtc;
3469 break;
3470 }
3471 if (!supported_crtc)
3472 supported_crtc = possible_crtc;
3473 }
3474
3475
3476
3477
3478 if (!crtc) {
3479 return NULL;
3480 }
3481
3482 encoder->crtc = crtc;
3483 intel_output->base.encoder = encoder;
3484 intel_output->load_detect_temp = true;
3485
3486 intel_crtc = to_intel_crtc(crtc);
3487 *dpms_mode = intel_crtc->dpms_mode;
3488
3489 if (!crtc->enabled) {
3490 if (!mode)
3491 mode = &load_detect_mode;
3492 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3493 } else {
3494 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3495 crtc_funcs = crtc->helper_private;
3496 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3497 }
3498
3499
3500 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3501 encoder_funcs->commit(encoder);
3502 }
3503
3504 intel_wait_for_vblank(dev);
3505
3506 return crtc;
3507}
3508
3509void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3510{
3511 struct drm_encoder *encoder = &intel_output->enc;
3512 struct drm_device *dev = encoder->dev;
3513 struct drm_crtc *crtc = encoder->crtc;
3514 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3515 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3516
3517 if (intel_output->load_detect_temp) {
3518 encoder->crtc = NULL;
3519 intel_output->base.encoder = NULL;
3520 intel_output->load_detect_temp = false;
3521 crtc->enabled = drm_helper_crtc_in_use(crtc);
3522 drm_helper_disable_unused_functions(dev);
3523 }
3524
3525
3526 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3527 if (encoder->crtc == crtc)
3528 encoder_funcs->dpms(encoder, dpms_mode);
3529 crtc_funcs->dpms(crtc, dpms_mode);
3530 }
3531}
3532
3533
3534static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3535{
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3538 int pipe = intel_crtc->pipe;
3539 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3540 u32 fp;
3541 intel_clock_t clock;
3542
3543 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3544 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3545 else
3546 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3547
3548 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3549 if (IS_IGD(dev)) {
3550 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3551 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3552 } else {
3553 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3554 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3555 }
3556
3557 if (IS_I9XX(dev)) {
3558 if (IS_IGD(dev))
3559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3560 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3561 else
3562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3563 DPLL_FPA01_P1_POST_DIV_SHIFT);
3564
3565 switch (dpll & DPLL_MODE_MASK) {
3566 case DPLLB_MODE_DAC_SERIAL:
3567 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3568 5 : 10;
3569 break;
3570 case DPLLB_MODE_LVDS:
3571 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3572 7 : 14;
3573 break;
3574 default:
3575 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3576 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3577 return 0;
3578 }
3579
3580
3581 intel_clock(dev, 96000, &clock);
3582 } else {
3583 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3584
3585 if (is_lvds) {
3586 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3587 DPLL_FPA01_P1_POST_DIV_SHIFT);
3588 clock.p2 = 14;
3589
3590 if ((dpll & PLL_REF_INPUT_MASK) ==
3591 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3592
3593 intel_clock(dev, 66000, &clock);
3594 } else
3595 intel_clock(dev, 48000, &clock);
3596 } else {
3597 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3598 clock.p1 = 2;
3599 else {
3600 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3601 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3602 }
3603 if (dpll & PLL_P2_DIVIDE_BY_4)
3604 clock.p2 = 4;
3605 else
3606 clock.p2 = 2;
3607
3608 intel_clock(dev, 48000, &clock);
3609 }
3610 }
3611
3612
3613
3614
3615
3616
3617 return clock.dot;
3618}
3619
3620
3621struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3622 struct drm_crtc *crtc)
3623{
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 int pipe = intel_crtc->pipe;
3627 struct drm_display_mode *mode;
3628 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3629 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3630 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3631 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3632
3633 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3634 if (!mode)
3635 return NULL;
3636
3637 mode->clock = intel_crtc_clock_get(dev, crtc);
3638 mode->hdisplay = (htot & 0xffff) + 1;
3639 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3640 mode->hsync_start = (hsync & 0xffff) + 1;
3641 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3642 mode->vdisplay = (vtot & 0xffff) + 1;
3643 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3644 mode->vsync_start = (vsync & 0xffff) + 1;
3645 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3646
3647 drm_mode_set_name(mode);
3648 drm_mode_set_crtcinfo(mode, 0);
3649
3650 return mode;
3651}
3652
3653#define GPU_IDLE_TIMEOUT 500
3654
3655
3656static void intel_gpu_idle_timer(unsigned long arg)
3657{
3658 struct drm_device *dev = (struct drm_device *)arg;
3659 drm_i915_private_t *dev_priv = dev->dev_private;
3660
3661 DRM_DEBUG("idle timer fired, downclocking\n");
3662
3663 dev_priv->busy = false;
3664
3665 queue_work(dev_priv->wq, &dev_priv->idle_work);
3666}
3667
3668void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3669{
3670 drm_i915_private_t *dev_priv = dev->dev_private;
3671
3672 if (IS_IGDNG(dev))
3673 return;
3674
3675 if (!dev_priv->render_reclock_avail) {
3676 DRM_DEBUG("not reclocking render clock\n");
3677 return;
3678 }
3679
3680
3681 if (IS_G4X(dev) || IS_I9XX(dev))
3682 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3683 else if (IS_I85X(dev))
3684 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3685 DRM_DEBUG("increasing render clock frequency\n");
3686
3687
3688 if (schedule)
3689 mod_timer(&dev_priv->idle_timer, jiffies +
3690 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3691}
3692
3693void intel_decrease_renderclock(struct drm_device *dev)
3694{
3695 drm_i915_private_t *dev_priv = dev->dev_private;
3696
3697 if (IS_IGDNG(dev))
3698 return;
3699
3700 if (!dev_priv->render_reclock_avail) {
3701 DRM_DEBUG("not reclocking render clock\n");
3702 return;
3703 }
3704
3705 if (IS_G4X(dev)) {
3706 u16 gcfgc;
3707
3708
3709 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3710
3711
3712 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3713 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3714
3715 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3716 } else if (IS_I965G(dev)) {
3717 u16 gcfgc;
3718
3719
3720 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3721
3722
3723 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3724 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3725
3726 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3727 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3728 u16 gcfgc;
3729
3730
3731 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3732
3733
3734 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3735 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3736
3737 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3738 } else if (IS_I915G(dev)) {
3739 u16 gcfgc;
3740
3741
3742 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3743
3744
3745 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3746 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3747
3748 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3749 } else if (IS_I85X(dev)) {
3750 u16 hpllcc;
3751
3752
3753 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3754
3755
3756 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3757 hpllcc |= GC_CLOCK_133_200;
3758
3759 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3760 }
3761 DRM_DEBUG("decreasing render clock frequency\n");
3762}
3763
3764
3765
3766
3767void intel_decrease_displayclock(struct drm_device *dev)
3768{
3769 if (IS_IGDNG(dev))
3770 return;
3771
3772 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3773 IS_I915GM(dev)) {
3774 u16 gcfgc;
3775
3776
3777 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3778
3779
3780 gcfgc &= ~0xf0;
3781 gcfgc |= 0x80;
3782
3783 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3784 }
3785}
3786
3787#define CRTC_IDLE_TIMEOUT 1000
3788
3789static void intel_crtc_idle_timer(unsigned long arg)
3790{
3791 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3792 struct drm_crtc *crtc = &intel_crtc->base;
3793 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3794
3795 DRM_DEBUG("idle timer fired, downclocking\n");
3796
3797 intel_crtc->busy = false;
3798
3799 queue_work(dev_priv->wq, &dev_priv->idle_work);
3800}
3801
3802static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3803{
3804 struct drm_device *dev = crtc->dev;
3805 drm_i915_private_t *dev_priv = dev->dev_private;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807 int pipe = intel_crtc->pipe;
3808 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3809 int dpll = I915_READ(dpll_reg);
3810
3811 if (IS_IGDNG(dev))
3812 return;
3813
3814 if (!dev_priv->lvds_downclock_avail)
3815 return;
3816
3817 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3818 DRM_DEBUG("upclocking LVDS\n");
3819
3820
3821 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3822
3823 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3824 I915_WRITE(dpll_reg, dpll);
3825 dpll = I915_READ(dpll_reg);
3826 intel_wait_for_vblank(dev);
3827 dpll = I915_READ(dpll_reg);
3828 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3829 DRM_DEBUG("failed to upclock LVDS!\n");
3830
3831
3832 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3833 }
3834
3835
3836 if (schedule)
3837 mod_timer(&intel_crtc->idle_timer, jiffies +
3838 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3839}
3840
3841static void intel_decrease_pllclock(struct drm_crtc *crtc)
3842{
3843 struct drm_device *dev = crtc->dev;
3844 drm_i915_private_t *dev_priv = dev->dev_private;
3845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846 int pipe = intel_crtc->pipe;
3847 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3848 int dpll = I915_READ(dpll_reg);
3849
3850 if (IS_IGDNG(dev))
3851 return;
3852
3853 if (!dev_priv->lvds_downclock_avail)
3854 return;
3855
3856
3857
3858
3859
3860 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3861 DRM_DEBUG("downclocking LVDS\n");
3862
3863
3864 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3865
3866 dpll |= DISPLAY_RATE_SELECT_FPA1;
3867 I915_WRITE(dpll_reg, dpll);
3868 dpll = I915_READ(dpll_reg);
3869 intel_wait_for_vblank(dev);
3870 dpll = I915_READ(dpll_reg);
3871 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3872 DRM_DEBUG("failed to downclock LVDS!\n");
3873
3874
3875 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3876 }
3877
3878}
3879
3880
3881
3882
3883
3884
3885
3886
3887static void intel_idle_update(struct work_struct *work)
3888{
3889 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3890 idle_work);
3891 struct drm_device *dev = dev_priv->dev;
3892 struct drm_crtc *crtc;
3893 struct intel_crtc *intel_crtc;
3894
3895 if (!i915_powersave)
3896 return;
3897
3898 mutex_lock(&dev->struct_mutex);
3899
3900
3901 if (!dev_priv->busy) {
3902 intel_decrease_renderclock(dev);
3903 intel_decrease_displayclock(dev);
3904 }
3905
3906 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3907
3908 if (!crtc->fb)
3909 continue;
3910
3911 intel_crtc = to_intel_crtc(crtc);
3912 if (!intel_crtc->busy)
3913 intel_decrease_pllclock(crtc);
3914 }
3915
3916 mutex_unlock(&dev->struct_mutex);
3917}
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3930{
3931 drm_i915_private_t *dev_priv = dev->dev_private;
3932 struct drm_crtc *crtc = NULL;
3933 struct intel_framebuffer *intel_fb;
3934 struct intel_crtc *intel_crtc;
3935
3936 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3937 return;
3938
3939 dev_priv->busy = true;
3940 intel_increase_renderclock(dev, true);
3941
3942 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3943 if (!crtc->fb)
3944 continue;
3945
3946 intel_crtc = to_intel_crtc(crtc);
3947 intel_fb = to_intel_framebuffer(crtc->fb);
3948 if (intel_fb->obj == obj) {
3949 if (!intel_crtc->busy) {
3950
3951 intel_increase_pllclock(crtc, true);
3952 intel_crtc->busy = true;
3953 } else {
3954
3955 mod_timer(&intel_crtc->idle_timer, jiffies +
3956 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3957 }
3958 }
3959 }
3960}
3961
3962static void intel_crtc_destroy(struct drm_crtc *crtc)
3963{
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3965
3966 drm_crtc_cleanup(crtc);
3967 kfree(intel_crtc);
3968}
3969
3970static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3971 .dpms = intel_crtc_dpms,
3972 .mode_fixup = intel_crtc_mode_fixup,
3973 .mode_set = intel_crtc_mode_set,
3974 .mode_set_base = intel_pipe_set_base,
3975 .prepare = intel_crtc_prepare,
3976 .commit = intel_crtc_commit,
3977 .load_lut = intel_crtc_load_lut,
3978};
3979
3980static const struct drm_crtc_funcs intel_crtc_funcs = {
3981 .cursor_set = intel_crtc_cursor_set,
3982 .cursor_move = intel_crtc_cursor_move,
3983 .gamma_set = intel_crtc_gamma_set,
3984 .set_config = drm_crtc_helper_set_config,
3985 .destroy = intel_crtc_destroy,
3986};
3987
3988
3989static void intel_crtc_init(struct drm_device *dev, int pipe)
3990{
3991 struct intel_crtc *intel_crtc;
3992 int i;
3993
3994 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3995 if (intel_crtc == NULL)
3996 return;
3997
3998 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3999
4000 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4001 intel_crtc->pipe = pipe;
4002 intel_crtc->plane = pipe;
4003 for (i = 0; i < 256; i++) {
4004 intel_crtc->lut_r[i] = i;
4005 intel_crtc->lut_g[i] = i;
4006 intel_crtc->lut_b[i] = i;
4007 }
4008
4009
4010 intel_crtc->pipe = pipe;
4011 intel_crtc->plane = pipe;
4012 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4013 DRM_DEBUG("swapping pipes & planes for FBC\n");
4014 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4015 }
4016
4017 intel_crtc->cursor_addr = 0;
4018 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4019 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4020
4021 intel_crtc->busy = false;
4022
4023 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4024 (unsigned long)intel_crtc);
4025}
4026
4027int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4028 struct drm_file *file_priv)
4029{
4030 drm_i915_private_t *dev_priv = dev->dev_private;
4031 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4032 struct drm_mode_object *drmmode_obj;
4033 struct intel_crtc *crtc;
4034
4035 if (!dev_priv) {
4036 DRM_ERROR("called with no initialization\n");
4037 return -EINVAL;
4038 }
4039
4040 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4041 DRM_MODE_OBJECT_CRTC);
4042
4043 if (!drmmode_obj) {
4044 DRM_ERROR("no such CRTC id\n");
4045 return -EINVAL;
4046 }
4047
4048 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4049 pipe_from_crtc_id->pipe = crtc->pipe;
4050
4051 return 0;
4052}
4053
4054struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4055{
4056 struct drm_crtc *crtc = NULL;
4057
4058 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4060 if (intel_crtc->pipe == pipe)
4061 break;
4062 }
4063 return crtc;
4064}
4065
4066static int intel_connector_clones(struct drm_device *dev, int type_mask)
4067{
4068 int index_mask = 0;
4069 struct drm_connector *connector;
4070 int entry = 0;
4071
4072 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4073 struct intel_output *intel_output = to_intel_output(connector);
4074 if (type_mask & intel_output->clone_mask)
4075 index_mask |= (1 << entry);
4076 entry++;
4077 }
4078 return index_mask;
4079}
4080
4081
4082static void intel_setup_outputs(struct drm_device *dev)
4083{
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085 struct drm_connector *connector;
4086
4087 intel_crt_init(dev);
4088
4089
4090 if (IS_MOBILE(dev) && !IS_I830(dev))
4091 intel_lvds_init(dev);
4092
4093 if (IS_IGDNG(dev)) {
4094 int found;
4095
4096 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4097 intel_dp_init(dev, DP_A);
4098
4099 if (I915_READ(HDMIB) & PORT_DETECTED) {
4100
4101
4102 found = 0;
4103 if (!found)
4104 intel_hdmi_init(dev, HDMIB);
4105 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4106 intel_dp_init(dev, PCH_DP_B);
4107 }
4108
4109 if (I915_READ(HDMIC) & PORT_DETECTED)
4110 intel_hdmi_init(dev, HDMIC);
4111
4112 if (I915_READ(HDMID) & PORT_DETECTED)
4113 intel_hdmi_init(dev, HDMID);
4114
4115 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4116 intel_dp_init(dev, PCH_DP_C);
4117
4118 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4119 intel_dp_init(dev, PCH_DP_D);
4120
4121 } else if (IS_I9XX(dev)) {
4122 bool found = false;
4123
4124 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4125 found = intel_sdvo_init(dev, SDVOB);
4126 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4127 intel_hdmi_init(dev, SDVOB);
4128
4129 if (!found && SUPPORTS_INTEGRATED_DP(dev))
4130 intel_dp_init(dev, DP_B);
4131 }
4132
4133
4134
4135 if (I915_READ(SDVOB) & SDVO_DETECTED)
4136 found = intel_sdvo_init(dev, SDVOC);
4137
4138 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4139
4140 if (SUPPORTS_INTEGRATED_HDMI(dev))
4141 intel_hdmi_init(dev, SDVOC);
4142 if (SUPPORTS_INTEGRATED_DP(dev))
4143 intel_dp_init(dev, DP_C);
4144 }
4145
4146 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4147 intel_dp_init(dev, DP_D);
4148 } else
4149 intel_dvo_init(dev);
4150
4151 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4152 intel_tv_init(dev);
4153
4154 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4155 struct intel_output *intel_output = to_intel_output(connector);
4156 struct drm_encoder *encoder = &intel_output->enc;
4157
4158 encoder->possible_crtcs = intel_output->crtc_mask;
4159 encoder->possible_clones = intel_connector_clones(dev,
4160 intel_output->clone_mask);
4161 }
4162}
4163
4164static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4165{
4166 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4167 struct drm_device *dev = fb->dev;
4168
4169 if (fb->fbdev)
4170 intelfb_remove(dev, fb);
4171
4172 drm_framebuffer_cleanup(fb);
4173 mutex_lock(&dev->struct_mutex);
4174 drm_gem_object_unreference(intel_fb->obj);
4175 mutex_unlock(&dev->struct_mutex);
4176
4177 kfree(intel_fb);
4178}
4179
4180static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4181 struct drm_file *file_priv,
4182 unsigned int *handle)
4183{
4184 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4185 struct drm_gem_object *object = intel_fb->obj;
4186
4187 return drm_gem_handle_create(file_priv, object, handle);
4188}
4189
4190static const struct drm_framebuffer_funcs intel_fb_funcs = {
4191 .destroy = intel_user_framebuffer_destroy,
4192 .create_handle = intel_user_framebuffer_create_handle,
4193};
4194
4195int intel_framebuffer_create(struct drm_device *dev,
4196 struct drm_mode_fb_cmd *mode_cmd,
4197 struct drm_framebuffer **fb,
4198 struct drm_gem_object *obj)
4199{
4200 struct intel_framebuffer *intel_fb;
4201 int ret;
4202
4203 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4204 if (!intel_fb)
4205 return -ENOMEM;
4206
4207 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4208 if (ret) {
4209 DRM_ERROR("framebuffer init failed %d\n", ret);
4210 return ret;
4211 }
4212
4213 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4214
4215 intel_fb->obj = obj;
4216
4217 *fb = &intel_fb->base;
4218
4219 return 0;
4220}
4221
4222
4223static struct drm_framebuffer *
4224intel_user_framebuffer_create(struct drm_device *dev,
4225 struct drm_file *filp,
4226 struct drm_mode_fb_cmd *mode_cmd)
4227{
4228 struct drm_gem_object *obj;
4229 struct drm_framebuffer *fb;
4230 int ret;
4231
4232 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4233 if (!obj)
4234 return NULL;
4235
4236 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4237 if (ret) {
4238 mutex_lock(&dev->struct_mutex);
4239 drm_gem_object_unreference(obj);
4240 mutex_unlock(&dev->struct_mutex);
4241 return NULL;
4242 }
4243
4244 return fb;
4245}
4246
4247static const struct drm_mode_config_funcs intel_mode_funcs = {
4248 .fb_create = intel_user_framebuffer_create,
4249 .fb_changed = intelfb_probe,
4250};
4251
4252void intel_init_clock_gating(struct drm_device *dev)
4253{
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255
4256
4257
4258
4259
4260 if (IS_IGDNG(dev)) {
4261 return;
4262 } else if (IS_G4X(dev)) {
4263 uint32_t dspclk_gate;
4264 I915_WRITE(RENCLK_GATE_D1, 0);
4265 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4266 GS_UNIT_CLOCK_GATE_DISABLE |
4267 CL_UNIT_CLOCK_GATE_DISABLE);
4268 I915_WRITE(RAMCLK_GATE_D, 0);
4269 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4270 OVRUNIT_CLOCK_GATE_DISABLE |
4271 OVCUNIT_CLOCK_GATE_DISABLE;
4272 if (IS_GM45(dev))
4273 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4274 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4275 } else if (IS_I965GM(dev)) {
4276 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4277 I915_WRITE(RENCLK_GATE_D2, 0);
4278 I915_WRITE(DSPCLK_GATE_D, 0);
4279 I915_WRITE(RAMCLK_GATE_D, 0);
4280 I915_WRITE16(DEUC, 0);
4281 } else if (IS_I965G(dev)) {
4282 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4283 I965_RCC_CLOCK_GATE_DISABLE |
4284 I965_RCPB_CLOCK_GATE_DISABLE |
4285 I965_ISC_CLOCK_GATE_DISABLE |
4286 I965_FBC_CLOCK_GATE_DISABLE);
4287 I915_WRITE(RENCLK_GATE_D2, 0);
4288 } else if (IS_I9XX(dev)) {
4289 u32 dstate = I915_READ(D_STATE);
4290
4291 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4292 DSTATE_DOT_CLOCK_GATING;
4293 I915_WRITE(D_STATE, dstate);
4294 } else if (IS_I855(dev) || IS_I865G(dev)) {
4295 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4296 } else if (IS_I830(dev)) {
4297 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4298 }
4299}
4300
4301
4302static void intel_init_display(struct drm_device *dev)
4303{
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305
4306
4307 if (IS_IGDNG(dev))
4308 dev_priv->display.dpms = igdng_crtc_dpms;
4309 else
4310 dev_priv->display.dpms = i9xx_crtc_dpms;
4311
4312
4313 if (IS_MOBILE(dev)) {
4314 if (IS_GM45(dev)) {
4315 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4316 dev_priv->display.enable_fbc = g4x_enable_fbc;
4317 dev_priv->display.disable_fbc = g4x_disable_fbc;
4318 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4319 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4320 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4321 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4322 }
4323
4324 }
4325
4326
4327 if (IS_I945G(dev))
4328 dev_priv->display.get_display_clock_speed =
4329 i945_get_display_clock_speed;
4330 else if (IS_I915G(dev))
4331 dev_priv->display.get_display_clock_speed =
4332 i915_get_display_clock_speed;
4333 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4334 dev_priv->display.get_display_clock_speed =
4335 i9xx_misc_get_display_clock_speed;
4336 else if (IS_I915GM(dev))
4337 dev_priv->display.get_display_clock_speed =
4338 i915gm_get_display_clock_speed;
4339 else if (IS_I865G(dev))
4340 dev_priv->display.get_display_clock_speed =
4341 i865_get_display_clock_speed;
4342 else if (IS_I855(dev))
4343 dev_priv->display.get_display_clock_speed =
4344 i855_get_display_clock_speed;
4345 else
4346 dev_priv->display.get_display_clock_speed =
4347 i830_get_display_clock_speed;
4348
4349
4350 if (IS_IGDNG(dev))
4351 dev_priv->display.update_wm = NULL;
4352 else if (IS_G4X(dev))
4353 dev_priv->display.update_wm = g4x_update_wm;
4354 else if (IS_I965G(dev))
4355 dev_priv->display.update_wm = i965_update_wm;
4356 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4357 dev_priv->display.update_wm = i9xx_update_wm;
4358 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4359 } else {
4360 if (IS_I85X(dev))
4361 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4362 else if (IS_845G(dev))
4363 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4364 else
4365 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4366 dev_priv->display.update_wm = i830_update_wm;
4367 }
4368}
4369
4370void intel_modeset_init(struct drm_device *dev)
4371{
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int num_pipe;
4374 int i;
4375
4376 drm_mode_config_init(dev);
4377
4378 dev->mode_config.min_width = 0;
4379 dev->mode_config.min_height = 0;
4380
4381 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4382
4383 intel_init_display(dev);
4384
4385 if (IS_I965G(dev)) {
4386 dev->mode_config.max_width = 8192;
4387 dev->mode_config.max_height = 8192;
4388 } else if (IS_I9XX(dev)) {
4389 dev->mode_config.max_width = 4096;
4390 dev->mode_config.max_height = 4096;
4391 } else {
4392 dev->mode_config.max_width = 2048;
4393 dev->mode_config.max_height = 2048;
4394 }
4395
4396
4397 if (IS_I9XX(dev))
4398 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4399 else
4400 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4401
4402 if (IS_MOBILE(dev) || IS_I9XX(dev))
4403 num_pipe = 2;
4404 else
4405 num_pipe = 1;
4406 DRM_DEBUG("%d display pipe%s available.\n",
4407 num_pipe, num_pipe > 1 ? "s" : "");
4408
4409 if (IS_I85X(dev))
4410 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4411 else if (IS_I9XX(dev) || IS_G4X(dev))
4412 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4413
4414 for (i = 0; i < num_pipe; i++) {
4415 intel_crtc_init(dev, i);
4416 }
4417
4418 intel_setup_outputs(dev);
4419
4420 intel_init_clock_gating(dev);
4421
4422 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4423 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4424 (unsigned long)dev);
4425}
4426
4427void intel_modeset_cleanup(struct drm_device *dev)
4428{
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430 struct drm_crtc *crtc;
4431 struct intel_crtc *intel_crtc;
4432
4433 mutex_lock(&dev->struct_mutex);
4434
4435 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4436
4437 if (!crtc->fb)
4438 continue;
4439
4440 intel_crtc = to_intel_crtc(crtc);
4441 intel_increase_pllclock(crtc, false);
4442 del_timer_sync(&intel_crtc->idle_timer);
4443 }
4444
4445 intel_increase_renderclock(dev, false);
4446 del_timer_sync(&dev_priv->idle_timer);
4447
4448 mutex_unlock(&dev->struct_mutex);
4449
4450 if (dev_priv->display.disable_fbc)
4451 dev_priv->display.disable_fbc(dev);
4452
4453 drm_mode_config_cleanup(dev);
4454}
4455
4456
4457
4458
4459
4460struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4461{
4462 struct intel_output *intel_output = to_intel_output(connector);
4463
4464 return &intel_output->enc;
4465}
4466
4467
4468
4469
4470int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4471{
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 u16 gmch_ctrl;
4474
4475 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4476 if (state)
4477 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4478 else
4479 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4480 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4481 return 0;
4482}
4483