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31#ifndef __MGA_DRV_H__
32#define __MGA_DRV_H__
33
34
35
36
37#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
38
39#define DRIVER_NAME "mga"
40#define DRIVER_DESC "Matrox G200/G400"
41#define DRIVER_DATE "20051102"
42
43#define DRIVER_MAJOR 3
44#define DRIVER_MINOR 2
45#define DRIVER_PATCHLEVEL 1
46
47typedef struct drm_mga_primary_buffer {
48 u8 *start;
49 u8 *end;
50 int size;
51
52 u32 tail;
53 int space;
54 volatile long wrapped;
55
56 volatile u32 *status;
57
58 u32 last_flush;
59 u32 last_wrap;
60
61 u32 high_mark;
62} drm_mga_primary_buffer_t;
63
64typedef struct drm_mga_freelist {
65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev;
67 drm_mga_age_t age;
68 struct drm_buf *buf;
69} drm_mga_freelist_t;
70
71typedef struct {
72 drm_mga_freelist_t *list_entry;
73 int discard;
74 int dispatched;
75} drm_mga_buf_priv_t;
76
77typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv;
80
81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail;
83
84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
86
87 int chipset;
88 int usec_timeout;
89
90
91
92
93
94
95 int used_new_dma_init;
96
97
98
99
100
101 u32 dma_access;
102
103
104
105
106
107
108 u32 wagp_enable;
109
110
111
112
113
114
115
116 resource_size_t mmio_base;
117 resource_size_t mmio_size;
118
119
120 u32 clear_cmd;
121 u32 maccess;
122
123 atomic_t vbl_received;
124 wait_queue_head_t fence_queue;
125 atomic_t last_fence_retired;
126 u32 next_fence_to_post;
127
128 unsigned int fb_cpp;
129 unsigned int front_offset;
130 unsigned int front_pitch;
131 unsigned int back_offset;
132 unsigned int back_pitch;
133
134 unsigned int depth_cpp;
135 unsigned int depth_offset;
136 unsigned int depth_pitch;
137
138 unsigned int texture_offset;
139 unsigned int texture_size;
140
141 drm_local_map_t *sarea;
142 drm_local_map_t *mmio;
143 drm_local_map_t *status;
144 drm_local_map_t *warp;
145 drm_local_map_t *primary;
146 drm_local_map_t *agp_textures;
147
148 unsigned long agp_handle;
149 unsigned int agp_size;
150} drm_mga_private_t;
151
152extern struct drm_ioctl_desc mga_ioctls[];
153extern int mga_max_ioctl;
154
155
156extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
157 struct drm_file *file_priv);
158extern int mga_dma_init(struct drm_device *dev, void *data,
159 struct drm_file *file_priv);
160extern int mga_dma_flush(struct drm_device *dev, void *data,
161 struct drm_file *file_priv);
162extern int mga_dma_reset(struct drm_device *dev, void *data,
163 struct drm_file *file_priv);
164extern int mga_dma_buffers(struct drm_device *dev, void *data,
165 struct drm_file *file_priv);
166extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
167extern int mga_driver_unload(struct drm_device * dev);
168extern void mga_driver_lastclose(struct drm_device * dev);
169extern int mga_driver_dma_quiescent(struct drm_device * dev);
170
171extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv);
172
173extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
174extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
175extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
176
177extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
178
179
180extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
181extern int mga_warp_init(drm_mga_private_t * dev_priv);
182
183
184extern int mga_enable_vblank(struct drm_device *dev, int crtc);
185extern void mga_disable_vblank(struct drm_device *dev, int crtc);
186extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc);
187extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
188extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
189extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
190extern void mga_driver_irq_preinstall(struct drm_device * dev);
191extern int mga_driver_irq_postinstall(struct drm_device *dev);
192extern void mga_driver_irq_uninstall(struct drm_device * dev);
193extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
194 unsigned long arg);
195
196#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
197
198#if defined(__linux__) && defined(__alpha__)
199#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
200#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
201
202#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
203#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
204
205#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
206#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
207#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
208#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
209
210static inline u32 _MGA_READ(u32 * addr)
211{
212 DRM_MEMORYBARRIER();
213 return *(volatile u32 *)addr;
214}
215#else
216#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
217#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
218#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
219#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
220#endif
221
222#define DWGREG0 0x1c00
223#define DWGREG0_END 0x1dff
224#define DWGREG1 0x2c00
225#define DWGREG1_END 0x2dff
226
227#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
228#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
229#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
230#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
231
232
233
234
235
236#define MGA_EMIT_STATE( dev_priv, dirty ) \
237do { \
238 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
239 if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \
240 mga_g400_emit_state( dev_priv ); \
241 } else { \
242 mga_g200_emit_state( dev_priv ); \
243 } \
244 } \
245} while (0)
246
247#define WRAP_TEST_WITH_RETURN( dev_priv ) \
248do { \
249 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
250 if ( mga_is_idle( dev_priv ) ) { \
251 mga_do_dma_wrap_end( dev_priv ); \
252 } else if ( dev_priv->prim.space < \
253 dev_priv->prim.high_mark ) { \
254 if ( MGA_DMA_DEBUG ) \
255 DRM_INFO( "wrap...\n"); \
256 return -EBUSY; \
257 } \
258 } \
259} while (0)
260
261#define WRAP_WAIT_WITH_RETURN( dev_priv ) \
262do { \
263 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
264 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
265 if ( MGA_DMA_DEBUG ) \
266 DRM_INFO( "wrap...\n"); \
267 return -EBUSY; \
268 } \
269 mga_do_dma_wrap_end( dev_priv ); \
270 } \
271} while (0)
272
273
274
275
276
277#define MGA_VERBOSE 0
278
279#define DMA_LOCALS unsigned int write; volatile u8 *prim;
280
281#define DMA_BLOCK_SIZE (5 * sizeof(u32))
282
283#define BEGIN_DMA( n ) \
284do { \
285 if ( MGA_VERBOSE ) { \
286 DRM_INFO( "BEGIN_DMA( %d )\n", (n) ); \
287 DRM_INFO( " space=0x%x req=0x%Zx\n", \
288 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
289 } \
290 prim = dev_priv->prim.start; \
291 write = dev_priv->prim.tail; \
292} while (0)
293
294#define BEGIN_DMA_WRAP() \
295do { \
296 if ( MGA_VERBOSE ) { \
297 DRM_INFO( "BEGIN_DMA()\n" ); \
298 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
299 } \
300 prim = dev_priv->prim.start; \
301 write = dev_priv->prim.tail; \
302} while (0)
303
304#define ADVANCE_DMA() \
305do { \
306 dev_priv->prim.tail = write; \
307 if ( MGA_VERBOSE ) { \
308 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
309 write, dev_priv->prim.space ); \
310 } \
311} while (0)
312
313#define FLUSH_DMA() \
314do { \
315 if ( 0 ) { \
316 DRM_INFO( "\n" ); \
317 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
318 dev_priv->prim.tail, \
319 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
320 dev_priv->primary->offset)); \
321 } \
322 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
323 if ( dev_priv->prim.space < \
324 dev_priv->prim.high_mark ) { \
325 mga_do_dma_wrap_start( dev_priv ); \
326 } else { \
327 mga_do_dma_flush( dev_priv ); \
328 } \
329 } \
330} while (0)
331
332
333
334#define DMA_WRITE( offset, val ) \
335do { \
336 if ( MGA_VERBOSE ) { \
337 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
338 (u32)(val), write + (offset) * sizeof(u32) ); \
339 } \
340 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
341} while (0)
342
343#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
344do { \
345 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
346 (DMAREG( reg1 ) << 8) | \
347 (DMAREG( reg2 ) << 16) | \
348 (DMAREG( reg3 ) << 24)) ); \
349 DMA_WRITE( 1, val0 ); \
350 DMA_WRITE( 2, val1 ); \
351 DMA_WRITE( 3, val2 ); \
352 DMA_WRITE( 4, val3 ); \
353 write += DMA_BLOCK_SIZE; \
354} while (0)
355
356
357
358
359#define SET_AGE( age, h, w ) \
360do { \
361 (age)->head = h; \
362 (age)->wrap = w; \
363} while (0)
364
365#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
366 ( (age)->wrap == w && \
367 (age)->head < h ) )
368
369#define AGE_BUFFER( buf_priv ) \
370do { \
371 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
372 if ( (buf_priv)->dispatched ) { \
373 entry->age.head = (dev_priv->prim.tail + \
374 dev_priv->primary->offset); \
375 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
376 } else { \
377 entry->age.head = 0; \
378 entry->age.wrap = 0; \
379 } \
380} while (0)
381
382#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
383 MGA_DWGENGSTS | \
384 MGA_ENDPRDMASTS)
385#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
386 MGA_ENDPRDMASTS)
387
388#define MGA_DMA_DEBUG 0
389
390
391
392#define MGA_CRTC_INDEX 0x1fd4
393#define MGA_CRTC_DATA 0x1fd5
394
395
396#define MGA_VINTCLR (1 << 4)
397#define MGA_VINTEN (1 << 5)
398
399#define MGA_ALPHACTRL 0x2c7c
400#define MGA_AR0 0x1c60
401#define MGA_AR1 0x1c64
402#define MGA_AR2 0x1c68
403#define MGA_AR3 0x1c6c
404#define MGA_AR4 0x1c70
405#define MGA_AR5 0x1c74
406#define MGA_AR6 0x1c78
407
408#define MGA_CXBNDRY 0x1c80
409#define MGA_CXLEFT 0x1ca0
410#define MGA_CXRIGHT 0x1ca4
411
412#define MGA_DMAPAD 0x1c54
413#define MGA_DSTORG 0x2cb8
414#define MGA_DWGCTL 0x1c00
415# define MGA_OPCOD_MASK (15 << 0)
416# define MGA_OPCOD_TRAP (4 << 0)
417# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
418# define MGA_OPCOD_BITBLT (8 << 0)
419# define MGA_OPCOD_ILOAD (9 << 0)
420# define MGA_ATYPE_MASK (7 << 4)
421# define MGA_ATYPE_RPL (0 << 4)
422# define MGA_ATYPE_RSTR (1 << 4)
423# define MGA_ATYPE_ZI (3 << 4)
424# define MGA_ATYPE_BLK (4 << 4)
425# define MGA_ATYPE_I (7 << 4)
426# define MGA_LINEAR (1 << 7)
427# define MGA_ZMODE_MASK (7 << 8)
428# define MGA_ZMODE_NOZCMP (0 << 8)
429# define MGA_ZMODE_ZE (2 << 8)
430# define MGA_ZMODE_ZNE (3 << 8)
431# define MGA_ZMODE_ZLT (4 << 8)
432# define MGA_ZMODE_ZLTE (5 << 8)
433# define MGA_ZMODE_ZGT (6 << 8)
434# define MGA_ZMODE_ZGTE (7 << 8)
435# define MGA_SOLID (1 << 11)
436# define MGA_ARZERO (1 << 12)
437# define MGA_SGNZERO (1 << 13)
438# define MGA_SHIFTZERO (1 << 14)
439# define MGA_BOP_MASK (15 << 16)
440# define MGA_BOP_ZERO (0 << 16)
441# define MGA_BOP_DST (10 << 16)
442# define MGA_BOP_SRC (12 << 16)
443# define MGA_BOP_ONE (15 << 16)
444# define MGA_TRANS_SHIFT 20
445# define MGA_TRANS_MASK (15 << 20)
446# define MGA_BLTMOD_MASK (15 << 25)
447# define MGA_BLTMOD_BMONOLEF (0 << 25)
448# define MGA_BLTMOD_BMONOWF (4 << 25)
449# define MGA_BLTMOD_PLAN (1 << 25)
450# define MGA_BLTMOD_BFCOL (2 << 25)
451# define MGA_BLTMOD_BU32BGR (3 << 25)
452# define MGA_BLTMOD_BU32RGB (7 << 25)
453# define MGA_BLTMOD_BU24BGR (11 << 25)
454# define MGA_BLTMOD_BU24RGB (15 << 25)
455# define MGA_PATTERN (1 << 29)
456# define MGA_TRANSC (1 << 30)
457# define MGA_CLIPDIS (1 << 31)
458#define MGA_DWGSYNC 0x2c4c
459
460#define MGA_FCOL 0x1c24
461#define MGA_FIFOSTATUS 0x1e10
462#define MGA_FOGCOL 0x1cf4
463#define MGA_FXBNDRY 0x1c84
464#define MGA_FXLEFT 0x1ca8
465#define MGA_FXRIGHT 0x1cac
466
467#define MGA_ICLEAR 0x1e18
468# define MGA_SOFTRAPICLR (1 << 0)
469# define MGA_VLINEICLR (1 << 5)
470#define MGA_IEN 0x1e1c
471# define MGA_SOFTRAPIEN (1 << 0)
472# define MGA_VLINEIEN (1 << 5)
473
474#define MGA_LEN 0x1c5c
475
476#define MGA_MACCESS 0x1c04
477
478#define MGA_PITCH 0x1c8c
479#define MGA_PLNWT 0x1c1c
480#define MGA_PRIMADDRESS 0x1e58
481# define MGA_DMA_GENERAL (0 << 0)
482# define MGA_DMA_BLIT (1 << 0)
483# define MGA_DMA_VECTOR (2 << 0)
484# define MGA_DMA_VERTEX (3 << 0)
485#define MGA_PRIMEND 0x1e5c
486# define MGA_PRIMNOSTART (1 << 0)
487# define MGA_PAGPXFER (1 << 1)
488#define MGA_PRIMPTR 0x1e50
489# define MGA_PRIMPTREN0 (1 << 0)
490# define MGA_PRIMPTREN1 (1 << 1)
491
492#define MGA_RST 0x1e40
493# define MGA_SOFTRESET (1 << 0)
494# define MGA_SOFTEXTRST (1 << 1)
495
496#define MGA_SECADDRESS 0x2c40
497#define MGA_SECEND 0x2c44
498#define MGA_SETUPADDRESS 0x2cd0
499#define MGA_SETUPEND 0x2cd4
500#define MGA_SGN 0x1c58
501#define MGA_SOFTRAP 0x2c48
502#define MGA_SRCORG 0x2cb4
503# define MGA_SRMMAP_MASK (1 << 0)
504# define MGA_SRCMAP_FB (0 << 0)
505# define MGA_SRCMAP_SYSMEM (1 << 0)
506# define MGA_SRCACC_MASK (1 << 1)
507# define MGA_SRCACC_PCI (0 << 1)
508# define MGA_SRCACC_AGP (1 << 1)
509#define MGA_STATUS 0x1e14
510# define MGA_SOFTRAPEN (1 << 0)
511# define MGA_VSYNCPEN (1 << 4)
512# define MGA_VLINEPEN (1 << 5)
513# define MGA_DWGENGSTS (1 << 16)
514# define MGA_ENDPRDMASTS (1 << 17)
515#define MGA_STENCIL 0x2cc8
516#define MGA_STENCILCTL 0x2ccc
517
518#define MGA_TDUALSTAGE0 0x2cf8
519#define MGA_TDUALSTAGE1 0x2cfc
520#define MGA_TEXBORDERCOL 0x2c5c
521#define MGA_TEXCTL 0x2c30
522#define MGA_TEXCTL2 0x2c3c
523# define MGA_DUALTEX (1 << 7)
524# define MGA_G400_TC2_MAGIC (1 << 15)
525# define MGA_MAP1_ENABLE (1 << 31)
526#define MGA_TEXFILTER 0x2c58
527#define MGA_TEXHEIGHT 0x2c2c
528#define MGA_TEXORG 0x2c24
529# define MGA_TEXORGMAP_MASK (1 << 0)
530# define MGA_TEXORGMAP_FB (0 << 0)
531# define MGA_TEXORGMAP_SYSMEM (1 << 0)
532# define MGA_TEXORGACC_MASK (1 << 1)
533# define MGA_TEXORGACC_PCI (0 << 1)
534# define MGA_TEXORGACC_AGP (1 << 1)
535#define MGA_TEXORG1 0x2ca4
536#define MGA_TEXORG2 0x2ca8
537#define MGA_TEXORG3 0x2cac
538#define MGA_TEXORG4 0x2cb0
539#define MGA_TEXTRANS 0x2c34
540#define MGA_TEXTRANSHIGH 0x2c38
541#define MGA_TEXWIDTH 0x2c28
542
543#define MGA_WACCEPTSEQ 0x1dd4
544#define MGA_WCODEADDR 0x1e6c
545#define MGA_WFLAG 0x1dc4
546#define MGA_WFLAG1 0x1de0
547#define MGA_WFLAGNB 0x1e64
548#define MGA_WFLAGNB1 0x1e08
549#define MGA_WGETMSB 0x1dc8
550#define MGA_WIADDR 0x1dc0
551#define MGA_WIADDR2 0x1dd8
552# define MGA_WMODE_SUSPEND (0 << 0)
553# define MGA_WMODE_RESUME (1 << 0)
554# define MGA_WMODE_JUMP (2 << 0)
555# define MGA_WMODE_START (3 << 0)
556# define MGA_WAGP_ENABLE (1 << 2)
557#define MGA_WMISC 0x1e70
558# define MGA_WUCODECACHE_ENABLE (1 << 0)
559# define MGA_WMASTER_ENABLE (1 << 1)
560# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
561#define MGA_WVRTXSZ 0x1dcc
562
563#define MGA_YBOT 0x1c9c
564#define MGA_YDST 0x1c90
565#define MGA_YDSTLEN 0x1c88
566#define MGA_YDSTORG 0x1c94
567#define MGA_YTOP 0x1c98
568
569#define MGA_ZORG 0x1c0c
570
571
572
573#define MGA_EXEC 0x0100
574
575
576
577#define MGA_AGP_PLL 0x1e4c
578# define MGA_AGP2XPLL_DISABLE (0 << 0)
579# define MGA_AGP2XPLL_ENABLE (1 << 0)
580
581
582
583#define MGA_WR0 0x2d00
584#define MGA_WR1 0x2d04
585#define MGA_WR2 0x2d08
586#define MGA_WR3 0x2d0c
587#define MGA_WR4 0x2d10
588#define MGA_WR5 0x2d14
589#define MGA_WR6 0x2d18
590#define MGA_WR7 0x2d1c
591#define MGA_WR8 0x2d20
592#define MGA_WR9 0x2d24
593#define MGA_WR10 0x2d28
594#define MGA_WR11 0x2d2c
595#define MGA_WR12 0x2d30
596#define MGA_WR13 0x2d34
597#define MGA_WR14 0x2d38
598#define MGA_WR15 0x2d3c
599#define MGA_WR16 0x2d40
600#define MGA_WR17 0x2d44
601#define MGA_WR18 0x2d48
602#define MGA_WR19 0x2d4c
603#define MGA_WR20 0x2d50
604#define MGA_WR21 0x2d54
605#define MGA_WR22 0x2d58
606#define MGA_WR23 0x2d5c
607#define MGA_WR24 0x2d60
608#define MGA_WR25 0x2d64
609#define MGA_WR26 0x2d68
610#define MGA_WR27 0x2d6c
611#define MGA_WR28 0x2d70
612#define MGA_WR29 0x2d74
613#define MGA_WR30 0x2d78
614#define MGA_WR31 0x2d7c
615#define MGA_WR32 0x2d80
616#define MGA_WR33 0x2d84
617#define MGA_WR34 0x2d88
618#define MGA_WR35 0x2d8c
619#define MGA_WR36 0x2d90
620#define MGA_WR37 0x2d94
621#define MGA_WR38 0x2d98
622#define MGA_WR39 0x2d9c
623#define MGA_WR40 0x2da0
624#define MGA_WR41 0x2da4
625#define MGA_WR42 0x2da8
626#define MGA_WR43 0x2dac
627#define MGA_WR44 0x2db0
628#define MGA_WR45 0x2db4
629#define MGA_WR46 0x2db8
630#define MGA_WR47 0x2dbc
631#define MGA_WR48 0x2dc0
632#define MGA_WR49 0x2dc4
633#define MGA_WR50 0x2dc8
634#define MGA_WR51 0x2dcc
635#define MGA_WR52 0x2dd0
636#define MGA_WR53 0x2dd4
637#define MGA_WR54 0x2dd8
638#define MGA_WR55 0x2ddc
639#define MGA_WR56 0x2de0
640#define MGA_WR57 0x2de4
641#define MGA_WR58 0x2de8
642#define MGA_WR59 0x2dec
643#define MGA_WR60 0x2df0
644#define MGA_WR61 0x2df4
645#define MGA_WR62 0x2df8
646#define MGA_WR63 0x2dfc
647# define MGA_G400_WR_MAGIC (1 << 6)
648# define MGA_G400_WR56_MAGIC 0x46480000
649
650#define MGA_ILOAD_ALIGN 64
651#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
652
653#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
654 MGA_ATYPE_I | \
655 MGA_ZMODE_NOZCMP | \
656 MGA_ARZERO | \
657 MGA_SGNZERO | \
658 MGA_BOP_SRC | \
659 (15 << MGA_TRANS_SHIFT))
660
661#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
662 MGA_ZMODE_NOZCMP | \
663 MGA_SOLID | \
664 MGA_ARZERO | \
665 MGA_SGNZERO | \
666 MGA_SHIFTZERO | \
667 MGA_BOP_SRC | \
668 (0 << MGA_TRANS_SHIFT) | \
669 MGA_BLTMOD_BMONOLEF | \
670 MGA_TRANSC | \
671 MGA_CLIPDIS)
672
673#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
674 MGA_ATYPE_RPL | \
675 MGA_SGNZERO | \
676 MGA_SHIFTZERO | \
677 MGA_BOP_SRC | \
678 (0 << MGA_TRANS_SHIFT) | \
679 MGA_BLTMOD_BFCOL | \
680 MGA_CLIPDIS)
681
682
683
684static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
685{
686 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
687 return (status == MGA_ENDPRDMASTS);
688}
689
690#endif
691
