1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32#include <linux/firmware.h>
33#include <linux/platform_device.h>
34
35#include "drmP.h"
36#include "drm.h"
37#include "r128_drm.h"
38#include "r128_drv.h"
39
40#define R128_FIFO_DEBUG 0
41
42#define FIRMWARE_NAME "r128/r128_cce.bin"
43
44MODULE_FIRMWARE(FIRMWARE_NAME);
45
46static int R128_READ_PLL(struct drm_device * dev, int addr)
47{
48 drm_r128_private_t *dev_priv = dev->dev_private;
49
50 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
51 return R128_READ(R128_CLOCK_CNTL_DATA);
52}
53
54#if R128_FIFO_DEBUG
55static void r128_status(drm_r128_private_t * dev_priv)
56{
57 printk("GUI_STAT = 0x%08x\n",
58 (unsigned int)R128_READ(R128_GUI_STAT));
59 printk("PM4_STAT = 0x%08x\n",
60 (unsigned int)R128_READ(R128_PM4_STAT));
61 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
62 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
63 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
64 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
65 printk("PM4_MICRO_CNTL = 0x%08x\n",
66 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
67 printk("PM4_BUFFER_CNTL = 0x%08x\n",
68 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
69}
70#endif
71
72
73
74
75
76static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
77{
78 u32 tmp;
79 int i;
80
81 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
82 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
83
84 for (i = 0; i < dev_priv->usec_timeout; i++) {
85 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
86 return 0;
87 }
88 DRM_UDELAY(1);
89 }
90
91#if R128_FIFO_DEBUG
92 DRM_ERROR("failed!\n");
93#endif
94 return -EBUSY;
95}
96
97static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
98{
99 int i;
100
101 for (i = 0; i < dev_priv->usec_timeout; i++) {
102 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
103 if (slots >= entries)
104 return 0;
105 DRM_UDELAY(1);
106 }
107
108#if R128_FIFO_DEBUG
109 DRM_ERROR("failed!\n");
110#endif
111 return -EBUSY;
112}
113
114static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
115{
116 int i, ret;
117
118 ret = r128_do_wait_for_fifo(dev_priv, 64);
119 if (ret)
120 return ret;
121
122 for (i = 0; i < dev_priv->usec_timeout; i++) {
123 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
124 r128_do_pixcache_flush(dev_priv);
125 return 0;
126 }
127 DRM_UDELAY(1);
128 }
129
130#if R128_FIFO_DEBUG
131 DRM_ERROR("failed!\n");
132#endif
133 return -EBUSY;
134}
135
136
137
138
139
140
141static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
142{
143 struct platform_device *pdev;
144 const struct firmware *fw;
145 const __be32 *fw_data;
146 int rc, i;
147
148 DRM_DEBUG("\n");
149
150 pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
151 if (IS_ERR(pdev)) {
152 printk(KERN_ERR "r128_cce: Failed to register firmware\n");
153 return PTR_ERR(pdev);
154 }
155 rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
156 platform_device_unregister(pdev);
157 if (rc) {
158 printk(KERN_ERR "r128_cce: Failed to load firmware \"%s\"\n",
159 FIRMWARE_NAME);
160 return rc;
161 }
162
163 if (fw->size != 256 * 8) {
164 printk(KERN_ERR
165 "r128_cce: Bogus length %zu in firmware \"%s\"\n",
166 fw->size, FIRMWARE_NAME);
167 rc = -EINVAL;
168 goto out_release;
169 }
170
171 r128_do_wait_for_idle(dev_priv);
172
173 fw_data = (const __be32 *)fw->data;
174 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
175 for (i = 0; i < 256; i++) {
176 R128_WRITE(R128_PM4_MICROCODE_DATAH,
177 be32_to_cpup(&fw_data[i * 2]));
178 R128_WRITE(R128_PM4_MICROCODE_DATAL,
179 be32_to_cpup(&fw_data[i * 2 + 1]));
180 }
181
182out_release:
183 release_firmware(fw);
184 return rc;
185}
186
187
188
189
190
191static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
192{
193 u32 tmp;
194
195 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
196 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
197}
198
199
200
201int r128_do_cce_idle(drm_r128_private_t * dev_priv)
202{
203 int i;
204
205 for (i = 0; i < dev_priv->usec_timeout; i++) {
206 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
207 int pm4stat = R128_READ(R128_PM4_STAT);
208 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
209 dev_priv->cce_fifo_size) &&
210 !(pm4stat & (R128_PM4_BUSY |
211 R128_PM4_GUI_ACTIVE))) {
212 return r128_do_pixcache_flush(dev_priv);
213 }
214 }
215 DRM_UDELAY(1);
216 }
217
218#if R128_FIFO_DEBUG
219 DRM_ERROR("failed!\n");
220 r128_status(dev_priv);
221#endif
222 return -EBUSY;
223}
224
225
226
227static void r128_do_cce_start(drm_r128_private_t * dev_priv)
228{
229 r128_do_wait_for_idle(dev_priv);
230
231 R128_WRITE(R128_PM4_BUFFER_CNTL,
232 dev_priv->cce_mode | dev_priv->ring.size_l2qw
233 | R128_PM4_BUFFER_CNTL_NOUPDATE);
234 R128_READ(R128_PM4_BUFFER_ADDR);
235 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
236
237 dev_priv->cce_running = 1;
238}
239
240
241
242
243
244static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
245{
246 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
247 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
248 dev_priv->ring.tail = 0;
249}
250
251
252
253
254
255static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
256{
257 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
258 R128_WRITE(R128_PM4_BUFFER_CNTL,
259 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
260
261 dev_priv->cce_running = 0;
262}
263
264
265
266static int r128_do_engine_reset(struct drm_device * dev)
267{
268 drm_r128_private_t *dev_priv = dev->dev_private;
269 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
270
271 r128_do_pixcache_flush(dev_priv);
272
273 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
274 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
275
276 R128_WRITE_PLL(R128_MCLK_CNTL,
277 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
278
279 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
280
281
282 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
283 R128_READ(R128_GEN_RESET_CNTL);
284 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
285 R128_READ(R128_GEN_RESET_CNTL);
286
287 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
288 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
289 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
290
291
292 r128_do_cce_reset(dev_priv);
293
294
295 dev_priv->cce_running = 0;
296
297
298 r128_freelist_reset(dev);
299
300 return 0;
301}
302
303static void r128_cce_init_ring_buffer(struct drm_device * dev,
304 drm_r128_private_t * dev_priv)
305{
306 u32 ring_start;
307 u32 tmp;
308
309 DRM_DEBUG("\n");
310
311
312
313
314#if __OS_HAS_AGP
315 if (!dev_priv->is_pci)
316 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
317 else
318#endif
319 ring_start = dev_priv->cce_ring->offset -
320 (unsigned long)dev->sg->virtual;
321
322 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
323
324 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
325 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
326
327
328 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
329 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
330 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
331 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
332 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
333
334
335 R128_READ(R128_PM4_BUFFER_ADDR);
336
337
338 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
339 R128_WRITE(R128_BUS_CNTL, tmp);
340}
341
342static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
343{
344 drm_r128_private_t *dev_priv;
345 int rc;
346
347 DRM_DEBUG("\n");
348
349 if (dev->dev_private) {
350 DRM_DEBUG("called when already initialized\n");
351 return -EINVAL;
352 }
353
354 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
355 if (dev_priv == NULL)
356 return -ENOMEM;
357
358 dev_priv->is_pci = init->is_pci;
359
360 if (dev_priv->is_pci && !dev->sg) {
361 DRM_ERROR("PCI GART memory not allocated!\n");
362 dev->dev_private = (void *)dev_priv;
363 r128_do_cleanup_cce(dev);
364 return -EINVAL;
365 }
366
367 dev_priv->usec_timeout = init->usec_timeout;
368 if (dev_priv->usec_timeout < 1 ||
369 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
370 DRM_DEBUG("TIMEOUT problem!\n");
371 dev->dev_private = (void *)dev_priv;
372 r128_do_cleanup_cce(dev);
373 return -EINVAL;
374 }
375
376 dev_priv->cce_mode = init->cce_mode;
377
378
379
380 atomic_set(&dev_priv->idle_count, 0);
381
382
383
384
385
386 if ((init->cce_mode != R128_PM4_192BM) &&
387 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
388 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
389 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
390 DRM_DEBUG("Bad cce_mode!\n");
391 dev->dev_private = (void *)dev_priv;
392 r128_do_cleanup_cce(dev);
393 return -EINVAL;
394 }
395
396 switch (init->cce_mode) {
397 case R128_PM4_NONPM4:
398 dev_priv->cce_fifo_size = 0;
399 break;
400 case R128_PM4_192PIO:
401 case R128_PM4_192BM:
402 dev_priv->cce_fifo_size = 192;
403 break;
404 case R128_PM4_128PIO_64INDBM:
405 case R128_PM4_128BM_64INDBM:
406 dev_priv->cce_fifo_size = 128;
407 break;
408 case R128_PM4_64PIO_128INDBM:
409 case R128_PM4_64BM_128INDBM:
410 case R128_PM4_64PIO_64VCBM_64INDBM:
411 case R128_PM4_64BM_64VCBM_64INDBM:
412 case R128_PM4_64PIO_64VCPIO_64INDPIO:
413 dev_priv->cce_fifo_size = 64;
414 break;
415 }
416
417 switch (init->fb_bpp) {
418 case 16:
419 dev_priv->color_fmt = R128_DATATYPE_RGB565;
420 break;
421 case 32:
422 default:
423 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
424 break;
425 }
426 dev_priv->front_offset = init->front_offset;
427 dev_priv->front_pitch = init->front_pitch;
428 dev_priv->back_offset = init->back_offset;
429 dev_priv->back_pitch = init->back_pitch;
430
431 switch (init->depth_bpp) {
432 case 16:
433 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
434 break;
435 case 24:
436 case 32:
437 default:
438 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
439 break;
440 }
441 dev_priv->depth_offset = init->depth_offset;
442 dev_priv->depth_pitch = init->depth_pitch;
443 dev_priv->span_offset = init->span_offset;
444
445 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
446 (dev_priv->front_offset >> 5));
447 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
448 (dev_priv->back_offset >> 5));
449 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
450 (dev_priv->depth_offset >> 5) |
451 R128_DST_TILE);
452 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
453 (dev_priv->span_offset >> 5));
454
455 dev_priv->sarea = drm_getsarea(dev);
456 if (!dev_priv->sarea) {
457 DRM_ERROR("could not find sarea!\n");
458 dev->dev_private = (void *)dev_priv;
459 r128_do_cleanup_cce(dev);
460 return -EINVAL;
461 }
462
463 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
464 if (!dev_priv->mmio) {
465 DRM_ERROR("could not find mmio region!\n");
466 dev->dev_private = (void *)dev_priv;
467 r128_do_cleanup_cce(dev);
468 return -EINVAL;
469 }
470 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
471 if (!dev_priv->cce_ring) {
472 DRM_ERROR("could not find cce ring region!\n");
473 dev->dev_private = (void *)dev_priv;
474 r128_do_cleanup_cce(dev);
475 return -EINVAL;
476 }
477 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
478 if (!dev_priv->ring_rptr) {
479 DRM_ERROR("could not find ring read pointer!\n");
480 dev->dev_private = (void *)dev_priv;
481 r128_do_cleanup_cce(dev);
482 return -EINVAL;
483 }
484 dev->agp_buffer_token = init->buffers_offset;
485 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
486 if (!dev->agp_buffer_map) {
487 DRM_ERROR("could not find dma buffer region!\n");
488 dev->dev_private = (void *)dev_priv;
489 r128_do_cleanup_cce(dev);
490 return -EINVAL;
491 }
492
493 if (!dev_priv->is_pci) {
494 dev_priv->agp_textures =
495 drm_core_findmap(dev, init->agp_textures_offset);
496 if (!dev_priv->agp_textures) {
497 DRM_ERROR("could not find agp texture region!\n");
498 dev->dev_private = (void *)dev_priv;
499 r128_do_cleanup_cce(dev);
500 return -EINVAL;
501 }
502 }
503
504 dev_priv->sarea_priv =
505 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
506 init->sarea_priv_offset);
507
508#if __OS_HAS_AGP
509 if (!dev_priv->is_pci) {
510 drm_core_ioremap_wc(dev_priv->cce_ring, dev);
511 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
512 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
513 if (!dev_priv->cce_ring->handle ||
514 !dev_priv->ring_rptr->handle ||
515 !dev->agp_buffer_map->handle) {
516 DRM_ERROR("Could not ioremap agp regions!\n");
517 dev->dev_private = (void *)dev_priv;
518 r128_do_cleanup_cce(dev);
519 return -ENOMEM;
520 }
521 } else
522#endif
523 {
524 dev_priv->cce_ring->handle =
525 (void *)(unsigned long)dev_priv->cce_ring->offset;
526 dev_priv->ring_rptr->handle =
527 (void *)(unsigned long)dev_priv->ring_rptr->offset;
528 dev->agp_buffer_map->handle =
529 (void *)(unsigned long)dev->agp_buffer_map->offset;
530 }
531
532#if __OS_HAS_AGP
533 if (!dev_priv->is_pci)
534 dev_priv->cce_buffers_offset = dev->agp->base;
535 else
536#endif
537 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
538
539 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
540 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
541 + init->ring_size / sizeof(u32));
542 dev_priv->ring.size = init->ring_size;
543 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
544
545 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
546
547 dev_priv->ring.high_mark = 128;
548
549 dev_priv->sarea_priv->last_frame = 0;
550 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
551
552 dev_priv->sarea_priv->last_dispatch = 0;
553 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
554
555#if __OS_HAS_AGP
556 if (dev_priv->is_pci) {
557#endif
558 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
559 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
560 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
561 dev_priv->gart_info.addr = NULL;
562 dev_priv->gart_info.bus_addr = 0;
563 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
564 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
565 DRM_ERROR("failed to init PCI GART!\n");
566 dev->dev_private = (void *)dev_priv;
567 r128_do_cleanup_cce(dev);
568 return -ENOMEM;
569 }
570 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
571#if __OS_HAS_AGP
572 }
573#endif
574
575 r128_cce_init_ring_buffer(dev, dev_priv);
576 rc = r128_cce_load_microcode(dev_priv);
577
578 dev->dev_private = (void *)dev_priv;
579
580 r128_do_engine_reset(dev);
581
582 if (rc) {
583 DRM_ERROR("Failed to load firmware!\n");
584 r128_do_cleanup_cce(dev);
585 }
586
587 return rc;
588}
589
590int r128_do_cleanup_cce(struct drm_device * dev)
591{
592
593
594
595
596
597 if (dev->irq_enabled)
598 drm_irq_uninstall(dev);
599
600 if (dev->dev_private) {
601 drm_r128_private_t *dev_priv = dev->dev_private;
602
603#if __OS_HAS_AGP
604 if (!dev_priv->is_pci) {
605 if (dev_priv->cce_ring != NULL)
606 drm_core_ioremapfree(dev_priv->cce_ring, dev);
607 if (dev_priv->ring_rptr != NULL)
608 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
609 if (dev->agp_buffer_map != NULL) {
610 drm_core_ioremapfree(dev->agp_buffer_map, dev);
611 dev->agp_buffer_map = NULL;
612 }
613 } else
614#endif
615 {
616 if (dev_priv->gart_info.bus_addr)
617 if (!drm_ati_pcigart_cleanup(dev,
618 &dev_priv->gart_info))
619 DRM_ERROR
620 ("failed to cleanup PCI GART!\n");
621 }
622
623 kfree(dev->dev_private);
624 dev->dev_private = NULL;
625 }
626
627 return 0;
628}
629
630int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
631{
632 drm_r128_init_t *init = data;
633
634 DRM_DEBUG("\n");
635
636 LOCK_TEST_WITH_RETURN(dev, file_priv);
637
638 switch (init->func) {
639 case R128_INIT_CCE:
640 return r128_do_init_cce(dev, init);
641 case R128_CLEANUP_CCE:
642 return r128_do_cleanup_cce(dev);
643 }
644
645 return -EINVAL;
646}
647
648int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
649{
650 drm_r128_private_t *dev_priv = dev->dev_private;
651 DRM_DEBUG("\n");
652
653 LOCK_TEST_WITH_RETURN(dev, file_priv);
654
655 DEV_INIT_TEST_WITH_RETURN(dev_priv);
656
657 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
658 DRM_DEBUG("while CCE running\n");
659 return 0;
660 }
661
662 r128_do_cce_start(dev_priv);
663
664 return 0;
665}
666
667
668
669
670int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
671{
672 drm_r128_private_t *dev_priv = dev->dev_private;
673 drm_r128_cce_stop_t *stop = data;
674 int ret;
675 DRM_DEBUG("\n");
676
677 LOCK_TEST_WITH_RETURN(dev, file_priv);
678
679 DEV_INIT_TEST_WITH_RETURN(dev_priv);
680
681
682
683
684 if (stop->flush) {
685 r128_do_cce_flush(dev_priv);
686 }
687
688
689
690
691 if (stop->idle) {
692 ret = r128_do_cce_idle(dev_priv);
693 if (ret)
694 return ret;
695 }
696
697
698
699
700
701 r128_do_cce_stop(dev_priv);
702
703
704 r128_do_engine_reset(dev);
705
706 return 0;
707}
708
709
710
711int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
712{
713 drm_r128_private_t *dev_priv = dev->dev_private;
714 DRM_DEBUG("\n");
715
716 LOCK_TEST_WITH_RETURN(dev, file_priv);
717
718 DEV_INIT_TEST_WITH_RETURN(dev_priv);
719
720 r128_do_cce_reset(dev_priv);
721
722
723 dev_priv->cce_running = 0;
724
725 return 0;
726}
727
728int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
729{
730 drm_r128_private_t *dev_priv = dev->dev_private;
731 DRM_DEBUG("\n");
732
733 LOCK_TEST_WITH_RETURN(dev, file_priv);
734
735 DEV_INIT_TEST_WITH_RETURN(dev_priv);
736
737 if (dev_priv->cce_running) {
738 r128_do_cce_flush(dev_priv);
739 }
740
741 return r128_do_cce_idle(dev_priv);
742}
743
744int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
745{
746 DRM_DEBUG("\n");
747
748 LOCK_TEST_WITH_RETURN(dev, file_priv);
749
750 DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
751
752 return r128_do_engine_reset(dev);
753}
754
755int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
756{
757 return -EINVAL;
758}
759
760
761
762
763#define R128_BUFFER_USED 0xffffffff
764#define R128_BUFFER_FREE 0
765
766#if 0
767static int r128_freelist_init(struct drm_device * dev)
768{
769 struct drm_device_dma *dma = dev->dma;
770 drm_r128_private_t *dev_priv = dev->dev_private;
771 struct drm_buf *buf;
772 drm_r128_buf_priv_t *buf_priv;
773 drm_r128_freelist_t *entry;
774 int i;
775
776 dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
777 if (dev_priv->head == NULL)
778 return -ENOMEM;
779
780 dev_priv->head->age = R128_BUFFER_USED;
781
782 for (i = 0; i < dma->buf_count; i++) {
783 buf = dma->buflist[i];
784 buf_priv = buf->dev_private;
785
786 entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
787 if (!entry)
788 return -ENOMEM;
789
790 entry->age = R128_BUFFER_FREE;
791 entry->buf = buf;
792 entry->prev = dev_priv->head;
793 entry->next = dev_priv->head->next;
794 if (!entry->next)
795 dev_priv->tail = entry;
796
797 buf_priv->discard = 0;
798 buf_priv->dispatched = 0;
799 buf_priv->list_entry = entry;
800
801 dev_priv->head->next = entry;
802
803 if (dev_priv->head->next)
804 dev_priv->head->next->prev = entry;
805 }
806
807 return 0;
808
809}
810#endif
811
812static struct drm_buf *r128_freelist_get(struct drm_device * dev)
813{
814 struct drm_device_dma *dma = dev->dma;
815 drm_r128_private_t *dev_priv = dev->dev_private;
816 drm_r128_buf_priv_t *buf_priv;
817 struct drm_buf *buf;
818 int i, t;
819
820
821
822 for (i = 0; i < dma->buf_count; i++) {
823 buf = dma->buflist[i];
824 buf_priv = buf->dev_private;
825 if (!buf->file_priv)
826 return buf;
827 }
828
829 for (t = 0; t < dev_priv->usec_timeout; t++) {
830 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
831
832 for (i = 0; i < dma->buf_count; i++) {
833 buf = dma->buflist[i];
834 buf_priv = buf->dev_private;
835 if (buf->pending && buf_priv->age <= done_age) {
836
837
838
839 buf->pending = 0;
840 return buf;
841 }
842 }
843 DRM_UDELAY(1);
844 }
845
846 DRM_DEBUG("returning NULL!\n");
847 return NULL;
848}
849
850void r128_freelist_reset(struct drm_device * dev)
851{
852 struct drm_device_dma *dma = dev->dma;
853 int i;
854
855 for (i = 0; i < dma->buf_count; i++) {
856 struct drm_buf *buf = dma->buflist[i];
857 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
858 buf_priv->age = 0;
859 }
860}
861
862
863
864
865
866int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
867{
868 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
869 int i;
870
871 for (i = 0; i < dev_priv->usec_timeout; i++) {
872 r128_update_ring_snapshot(dev_priv);
873 if (ring->space >= n)
874 return 0;
875 DRM_UDELAY(1);
876 }
877
878
879 DRM_ERROR("failed!\n");
880 return -EBUSY;
881}
882
883static int r128_cce_get_buffers(struct drm_device * dev,
884 struct drm_file *file_priv,
885 struct drm_dma * d)
886{
887 int i;
888 struct drm_buf *buf;
889
890 for (i = d->granted_count; i < d->request_count; i++) {
891 buf = r128_freelist_get(dev);
892 if (!buf)
893 return -EAGAIN;
894
895 buf->file_priv = file_priv;
896
897 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
898 sizeof(buf->idx)))
899 return -EFAULT;
900 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
901 sizeof(buf->total)))
902 return -EFAULT;
903
904 d->granted_count++;
905 }
906 return 0;
907}
908
909int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
910{
911 struct drm_device_dma *dma = dev->dma;
912 int ret = 0;
913 struct drm_dma *d = data;
914
915 LOCK_TEST_WITH_RETURN(dev, file_priv);
916
917
918
919 if (d->send_count != 0) {
920 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
921 DRM_CURRENTPID, d->send_count);
922 return -EINVAL;
923 }
924
925
926
927 if (d->request_count < 0 || d->request_count > dma->buf_count) {
928 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
929 DRM_CURRENTPID, d->request_count, dma->buf_count);
930 return -EINVAL;
931 }
932
933 d->granted_count = 0;
934
935 if (d->request_count) {
936 ret = r128_cce_get_buffers(dev, file_priv, d);
937 }
938
939 return ret;
940}
941
