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26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h"
30#include "radeon.h"
31#include "atom.h"
32
33static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
34 struct drm_display_mode *mode,
35 struct drm_display_mode *adjusted_mode)
36{
37 struct drm_device *dev = crtc->dev;
38 struct radeon_device *rdev = dev->dev_private;
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 int xres = mode->hdisplay;
41 int yres = mode->vdisplay;
42 bool hscale = true, vscale = true;
43 int hsync_wid;
44 int vsync_wid;
45 int hsync_start;
46 int blank_width;
47 u32 scale, inc, crtc_more_cntl;
48 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
52
53 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54 (RADEON_VERT_STRETCH_RESERVED |
55 RADEON_VERT_AUTO_RATIO_INC);
56 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
57 (RADEON_HORZ_FP_LOOP_STRETCH |
58 RADEON_HORZ_AUTO_RATIO_INC);
59
60 crtc_more_cntl = 0;
61 if ((rdev->family == CHIP_RS100) ||
62 (rdev->family == CHIP_RS200)) {
63
64
65 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
66 }
67
68
69 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
70 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
71
72 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
73 if (!hsync_wid)
74 hsync_wid = 1;
75 hsync_start = mode->crtc_hsync_start - 8;
76
77 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
78 | ((hsync_wid & 0x3f) << 16)
79 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
80 ? RADEON_CRTC_H_SYNC_POL
81 : 0));
82
83 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
84 | ((mode->crtc_vdisplay - 1) << 16));
85
86 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
87 if (!vsync_wid)
88 vsync_wid = 1;
89
90 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
91 | ((vsync_wid & 0x1f) << 16)
92 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
93 ? RADEON_CRTC_V_SYNC_POL
94 : 0));
95
96 fp_horz_vert_active = 0;
97
98 if (native_mode->hdisplay == 0 ||
99 native_mode->vdisplay == 0) {
100 hscale = false;
101 vscale = false;
102 } else {
103 if (xres > native_mode->hdisplay)
104 xres = native_mode->hdisplay;
105 if (yres > native_mode->vdisplay)
106 yres = native_mode->vdisplay;
107
108 if (xres == native_mode->hdisplay)
109 hscale = false;
110 if (yres == native_mode->vdisplay)
111 vscale = false;
112 }
113
114 switch (radeon_crtc->rmx_type) {
115 case RMX_FULL:
116 case RMX_ASPECT:
117 if (!hscale)
118 fp_horz_stretch |= ((xres/8-1) << 16);
119 else {
120 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122 / native_mode->hdisplay + 1;
123 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
124 RADEON_HORZ_STRETCH_BLEND |
125 RADEON_HORZ_STRETCH_ENABLE |
126 ((native_mode->hdisplay/8-1) << 16));
127 }
128
129 if (!vscale)
130 fp_vert_stretch |= ((yres-1) << 12);
131 else {
132 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134 / native_mode->vdisplay + 1;
135 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
136 RADEON_VERT_STRETCH_ENABLE |
137 RADEON_VERT_STRETCH_BLEND |
138 ((native_mode->vdisplay-1) << 12));
139 }
140 break;
141 case RMX_CENTER:
142 fp_horz_stretch |= ((xres/8-1) << 16);
143 fp_vert_stretch |= ((yres-1) << 12);
144
145 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
146 RADEON_CRTC_AUTO_VERT_CENTER_EN);
147
148 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
149 if (blank_width > 110)
150 blank_width = 110;
151
152 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
153 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
154
155 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
156 if (!hsync_wid)
157 hsync_wid = 1;
158
159 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
160 | ((hsync_wid & 0x3f) << 16)
161 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
162 ? RADEON_CRTC_H_SYNC_POL
163 : 0));
164
165 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
166 | ((mode->crtc_vdisplay - 1) << 16));
167
168 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
169 if (!vsync_wid)
170 vsync_wid = 1;
171
172 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
173 | ((vsync_wid & 0x1f) << 16)
174 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
175 ? RADEON_CRTC_V_SYNC_POL
176 : 0)));
177
178 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
179 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
180 break;
181 case RMX_OFF:
182 default:
183 fp_horz_stretch |= ((xres/8-1) << 16);
184 fp_vert_stretch |= ((yres-1) << 12);
185 break;
186 }
187
188 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
189 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
190 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
191 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
192 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
193 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
194 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
195 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
196}
197
198void radeon_restore_common_regs(struct drm_device *dev)
199{
200
201}
202
203static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
204{
205 struct radeon_device *rdev = dev->dev_private;
206 int i = 0;
207
208
209
210
211
212 for (i = 0;
213 (i < 10000 &&
214 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
215 i++);
216}
217
218static void radeon_pll_write_update(struct drm_device *dev)
219{
220 struct radeon_device *rdev = dev->dev_private;
221
222 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
223
224 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
225 RADEON_PPLL_ATOMIC_UPDATE_W,
226 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
227}
228
229static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
230{
231 struct radeon_device *rdev = dev->dev_private;
232 int i = 0;
233
234
235
236
237
238
239 for (i = 0;
240 (i < 10000 &&
241 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
242 i++);
243}
244
245static void radeon_pll2_write_update(struct drm_device *dev)
246{
247 struct radeon_device *rdev = dev->dev_private;
248
249 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
250
251 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
252 RADEON_P2PLL_ATOMIC_UPDATE_W,
253 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
254}
255
256static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
257 uint16_t fb_div)
258{
259 unsigned int vcoFreq;
260
261 if (!ref_div)
262 return 1;
263
264 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
265
266
267
268
269
270 if (vcoFreq >= 30000)
271
272
273
274 return 7;
275 else if (vcoFreq >= 18000)
276
277
278
279 return 4;
280 else
281
282
283
284 return 1;
285}
286
287void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
288{
289 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
290 struct drm_device *dev = crtc->dev;
291 struct radeon_device *rdev = dev->dev_private;
292 uint32_t mask;
293
294 if (radeon_crtc->crtc_id)
295 mask = (RADEON_CRTC2_EN |
296 RADEON_CRTC2_DISP_DIS |
297 RADEON_CRTC2_VSYNC_DIS |
298 RADEON_CRTC2_HSYNC_DIS |
299 RADEON_CRTC2_DISP_REQ_EN_B);
300 else
301 mask = (RADEON_CRTC_DISPLAY_DIS |
302 RADEON_CRTC_VSYNC_DIS |
303 RADEON_CRTC_HSYNC_DIS);
304
305 switch (mode) {
306 case DRM_MODE_DPMS_ON:
307 if (radeon_crtc->crtc_id)
308 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
309 else {
310 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
311 RADEON_CRTC_DISP_REQ_EN_B));
312 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
313 }
314 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
315 radeon_crtc_load_lut(crtc);
316 break;
317 case DRM_MODE_DPMS_STANDBY:
318 case DRM_MODE_DPMS_SUSPEND:
319 case DRM_MODE_DPMS_OFF:
320 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
321 if (radeon_crtc->crtc_id)
322 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
323 else {
324 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
325 RADEON_CRTC_DISP_REQ_EN_B));
326 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
327 }
328 break;
329 }
330}
331
332
333void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
334{
335 struct drm_device *dev = crtc->dev;
336 struct radeon_device *rdev = dev->dev_private;
337 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
338 int format;
339 uint32_t crtc_gen_cntl;
340 uint32_t disp_merge_cntl;
341 uint32_t crtc_pitch;
342
343 switch (crtc->fb->bits_per_pixel) {
344 case 8:
345 format = 2;
346 break;
347 case 15:
348 format = 3;
349 break;
350 case 16:
351 format = 4;
352 break;
353 case 24:
354 format = 5;
355 break;
356 case 32:
357 format = 6;
358 break;
359 default:
360 return;
361 }
362
363 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
364 ((crtc->fb->bits_per_pixel * 8) - 1)) /
365 (crtc->fb->bits_per_pixel * 8));
366 crtc_pitch |= crtc_pitch << 16;
367
368 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
369
370 switch (radeon_crtc->crtc_id) {
371 case 0:
372 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
373 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
374 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
375
376 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
377 crtc_gen_cntl |= (format << 8);
378 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
379 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
380 break;
381 case 1:
382 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
383 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
384 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
385
386 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
387 crtc_gen_cntl |= (format << 8);
388 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
389 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
390 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
391 break;
392 }
393}
394
395int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
396 struct drm_framebuffer *old_fb)
397{
398 struct drm_device *dev = crtc->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
401 struct radeon_framebuffer *radeon_fb;
402 struct drm_gem_object *obj;
403 uint64_t base;
404 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
405 uint32_t crtc_pitch, pitch_pixels;
406 uint32_t tiling_flags;
407 int format;
408 uint32_t gen_cntl_reg, gen_cntl_val;
409
410 DRM_DEBUG("\n");
411
412 radeon_fb = to_radeon_framebuffer(crtc->fb);
413
414 switch (crtc->fb->bits_per_pixel) {
415 case 8:
416 format = 2;
417 break;
418 case 15:
419 format = 3;
420 break;
421 case 16:
422 format = 4;
423 break;
424 case 24:
425 format = 5;
426 break;
427 case 32:
428 format = 6;
429 break;
430 default:
431 return false;
432 }
433
434 obj = radeon_fb->obj;
435 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
436 return -EINVAL;
437 }
438
439
440 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
441
442 base -= radeon_crtc->legacy_display_base_addr;
443
444 crtc_offset_cntl = 0;
445
446 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
447 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
448 ((crtc->fb->bits_per_pixel * 8) - 1)) /
449 (crtc->fb->bits_per_pixel * 8));
450 crtc_pitch |= crtc_pitch << 16;
451
452 radeon_object_get_tiling_flags(obj->driver_private,
453 &tiling_flags, NULL);
454 if (tiling_flags & RADEON_TILING_MICRO)
455 DRM_ERROR("trying to scanout microtiled buffer\n");
456
457 if (tiling_flags & RADEON_TILING_MACRO) {
458 if (ASIC_IS_R300(rdev))
459 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
460 R300_CRTC_MICRO_TILE_BUFFER_DIS |
461 R300_CRTC_MACRO_TILE_EN);
462 else
463 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
464 } else {
465 if (ASIC_IS_R300(rdev))
466 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
467 R300_CRTC_MICRO_TILE_BUFFER_DIS |
468 R300_CRTC_MACRO_TILE_EN);
469 else
470 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
471 }
472
473 if (tiling_flags & RADEON_TILING_MACRO) {
474 if (ASIC_IS_R300(rdev)) {
475 crtc_tile_x0_y0 = x | (y << 16);
476 base &= ~0x7ff;
477 } else {
478 int byteshift = crtc->fb->bits_per_pixel >> 4;
479 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
480 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
481 crtc_offset_cntl |= (y % 16);
482 }
483 } else {
484 int offset = y * pitch_pixels + x;
485 switch (crtc->fb->bits_per_pixel) {
486 case 8:
487 offset *= 1;
488 break;
489 case 15:
490 case 16:
491 offset *= 2;
492 break;
493 case 24:
494 offset *= 3;
495 break;
496 case 32:
497 offset *= 4;
498 break;
499 default:
500 return false;
501 }
502 base += offset;
503 }
504
505 base &= ~7;
506
507 if (radeon_crtc->crtc_id == 1)
508 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
509 else
510 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
511
512 gen_cntl_val = RREG32(gen_cntl_reg);
513 gen_cntl_val &= ~(0xf << 8);
514 gen_cntl_val |= (format << 8);
515 WREG32(gen_cntl_reg, gen_cntl_val);
516
517 crtc_offset = (u32)base;
518
519 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
520
521 if (ASIC_IS_R300(rdev)) {
522 if (radeon_crtc->crtc_id)
523 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
524 else
525 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
526 }
527 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
528 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
529 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
530
531 if (old_fb && old_fb != crtc->fb) {
532 radeon_fb = to_radeon_framebuffer(old_fb);
533 radeon_gem_object_unpin(radeon_fb->obj);
534 }
535
536
537 radeon_bandwidth_update(rdev);
538
539 return 0;
540}
541
542static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
543{
544 struct drm_device *dev = crtc->dev;
545 struct radeon_device *rdev = dev->dev_private;
546 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
547 struct drm_encoder *encoder;
548 int format;
549 int hsync_start;
550 int hsync_wid;
551 int vsync_wid;
552 uint32_t crtc_h_total_disp;
553 uint32_t crtc_h_sync_strt_wid;
554 uint32_t crtc_v_total_disp;
555 uint32_t crtc_v_sync_strt_wid;
556 bool is_tv = false;
557
558 DRM_DEBUG("\n");
559 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
560 if (encoder->crtc == crtc) {
561 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
562 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
563 is_tv = true;
564 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
565 break;
566 }
567 }
568 }
569
570 switch (crtc->fb->bits_per_pixel) {
571 case 8:
572 format = 2;
573 break;
574 case 15:
575 format = 3;
576 break;
577 case 16:
578 format = 4;
579 break;
580 case 24:
581 format = 5;
582 break;
583 case 32:
584 format = 6;
585 break;
586 default:
587 return false;
588 }
589
590 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
591 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
592
593 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
594 if (!hsync_wid)
595 hsync_wid = 1;
596 hsync_start = mode->crtc_hsync_start - 8;
597
598 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
599 | ((hsync_wid & 0x3f) << 16)
600 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
601 ? RADEON_CRTC_H_SYNC_POL
602 : 0));
603
604
605 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
606 | ((mode->crtc_vdisplay - 1) << 16));
607
608 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
609 if (!vsync_wid)
610 vsync_wid = 1;
611
612 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
613 | ((vsync_wid & 0x1f) << 16)
614 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
615 ? RADEON_CRTC_V_SYNC_POL
616 : 0));
617
618
619 if (0) {
620 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
621 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
622 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
623 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
624
625 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
626 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
627
628
629
630
631 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
632 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
633 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
634
635 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
636 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
637 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
638 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
639 }
640
641 if (radeon_crtc->crtc_id) {
642 uint32_t crtc2_gen_cntl;
643 uint32_t disp2_merge_cntl;
644
645
646 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
647 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
648 else
649 crtc2_gen_cntl = 0;
650
651 crtc2_gen_cntl |= ((format << 8)
652 | RADEON_CRTC2_VSYNC_DIS
653 | RADEON_CRTC2_HSYNC_DIS
654 | RADEON_CRTC2_DISP_DIS
655 | RADEON_CRTC2_DISP_REQ_EN_B
656 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
657 ? RADEON_CRTC2_DBL_SCAN_EN
658 : 0)
659 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
660 ? RADEON_CRTC2_CSYNC_EN
661 : 0)
662 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
663 ? RADEON_CRTC2_INTERLACE_EN
664 : 0));
665
666 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
667 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
668
669 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
670 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
671
672 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
673 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
674 } else {
675 uint32_t crtc_gen_cntl;
676 uint32_t crtc_ext_cntl;
677 uint32_t disp_merge_cntl;
678
679 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
680 | (format << 8)
681 | RADEON_CRTC_DISP_REQ_EN_B
682 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
683 ? RADEON_CRTC_DBL_SCAN_EN
684 : 0)
685 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
686 ? RADEON_CRTC_CSYNC_EN
687 : 0)
688 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
689 ? RADEON_CRTC_INTERLACE_EN
690 : 0));
691
692 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
693 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
694 RADEON_CRTC_VSYNC_DIS |
695 RADEON_CRTC_HSYNC_DIS |
696 RADEON_CRTC_DISPLAY_DIS);
697
698 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
699 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
700
701 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
702 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
703 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
704 }
705
706 if (is_tv)
707 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
708 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
709 &crtc_v_sync_strt_wid);
710
711 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
712 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
713 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
714 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
715
716 return true;
717}
718
719static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
720{
721 struct drm_device *dev = crtc->dev;
722 struct radeon_device *rdev = dev->dev_private;
723 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
724 struct drm_encoder *encoder;
725 uint32_t feedback_div = 0;
726 uint32_t frac_fb_div = 0;
727 uint32_t reference_div = 0;
728 uint32_t post_divider = 0;
729 uint32_t freq = 0;
730 uint8_t pll_gain;
731 int pll_flags = RADEON_PLL_LEGACY;
732 bool use_bios_divs = false;
733
734 uint32_t pll_ref_div = 0;
735 uint32_t pll_fb_post_div = 0;
736 uint32_t htotal_cntl = 0;
737 bool is_tv = false;
738 struct radeon_pll *pll;
739
740 struct {
741 int divider;
742 int bitvalue;
743 } *post_div, post_divs[] = {
744
745
746
747
748
749 { 1, 0 },
750 { 2, 1 },
751 { 4, 2 },
752 { 8, 3 },
753 { 3, 4 },
754 { 16, 5 },
755 { 6, 6 },
756 { 12, 7 },
757 { 0, 0 }
758 };
759
760 if (radeon_crtc->crtc_id)
761 pll = &rdev->clock.p2pll;
762 else
763 pll = &rdev->clock.p1pll;
764
765 if (mode->clock > 200000)
766 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
767 else
768 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
769
770 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
771 if (encoder->crtc == crtc) {
772 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
773
774 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
775 is_tv = true;
776 break;
777 }
778
779 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
780 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
781 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
782 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
783 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
784 if (lvds) {
785 if (lvds->use_bios_dividers) {
786 pll_ref_div = lvds->panel_ref_divider;
787 pll_fb_post_div = (lvds->panel_fb_divider |
788 (lvds->panel_post_divider << 16));
789 htotal_cntl = 0;
790 use_bios_divs = true;
791 }
792 }
793 pll_flags |= RADEON_PLL_USE_REF_DIV;
794 }
795 }
796 }
797
798 DRM_DEBUG("\n");
799
800 if (!use_bios_divs) {
801 radeon_compute_pll(pll, mode->clock,
802 &freq, &feedback_div, &frac_fb_div,
803 &reference_div, &post_divider,
804 pll_flags);
805
806 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
807 if (post_div->divider == post_divider)
808 break;
809 }
810
811 if (!post_div->divider)
812 post_div = &post_divs[0];
813
814 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
815 (unsigned)freq,
816 feedback_div,
817 reference_div,
818 post_divider);
819
820 pll_ref_div = reference_div;
821#if defined(__powerpc__) && (0)
822
823 if (info->MacModel == RADEON_MAC_IBOOK)
824 pll_fb_post_div = 0x000600ad;
825 else
826#endif
827 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
828
829 htotal_cntl = mode->htotal & 0x7;
830
831 }
832
833 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
834 pll_ref_div & 0x3ff,
835 pll_fb_post_div & 0x7ff);
836
837 if (radeon_crtc->crtc_id) {
838 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
839 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
840 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
841
842 if (is_tv) {
843 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
844 &pll_ref_div, &pll_fb_post_div,
845 &pixclks_cntl);
846 }
847
848 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
849 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
850 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
851
852 WREG32_PLL_P(RADEON_P2PLL_CNTL,
853 RADEON_P2PLL_RESET
854 | RADEON_P2PLL_ATOMIC_UPDATE_EN
855 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
856 ~(RADEON_P2PLL_RESET
857 | RADEON_P2PLL_ATOMIC_UPDATE_EN
858 | RADEON_P2PLL_PVG_MASK));
859
860 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
861 pll_ref_div,
862 ~RADEON_P2PLL_REF_DIV_MASK);
863
864 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
865 pll_fb_post_div,
866 ~RADEON_P2PLL_FB0_DIV_MASK);
867
868 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
869 pll_fb_post_div,
870 ~RADEON_P2PLL_POST0_DIV_MASK);
871
872 radeon_pll2_write_update(dev);
873 radeon_pll2_wait_for_read_update_complete(dev);
874
875 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
876
877 WREG32_PLL_P(RADEON_P2PLL_CNTL,
878 0,
879 ~(RADEON_P2PLL_RESET
880 | RADEON_P2PLL_SLEEP
881 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
882
883 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
884 (unsigned)pll_ref_div,
885 (unsigned)pll_fb_post_div,
886 (unsigned)htotal_cntl,
887 RREG32_PLL(RADEON_P2PLL_CNTL));
888 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
889 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
890 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
891 (unsigned)((pll_fb_post_div &
892 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
893
894 mdelay(50);
895
896 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
897 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
898 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
899
900 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
901 } else {
902 uint32_t pixclks_cntl;
903
904
905 if (is_tv) {
906 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
907 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
908 &pll_fb_post_div, &pixclks_cntl);
909 }
910
911 if (rdev->flags & RADEON_IS_MOBILITY) {
912
913
914
915
916
917
918 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
919 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
920 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
921 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
922 RADEON_PLL_DIV_SEL,
923 ~(RADEON_PLL_DIV_SEL));
924 r100_pll_errata_after_index(rdev);
925 return;
926 }
927 }
928
929 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
930 RADEON_VCLK_SRC_SEL_CPUCLK,
931 ~(RADEON_VCLK_SRC_SEL_MASK));
932 WREG32_PLL_P(RADEON_PPLL_CNTL,
933 RADEON_PPLL_RESET
934 | RADEON_PPLL_ATOMIC_UPDATE_EN
935 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
936 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
937 ~(RADEON_PPLL_RESET
938 | RADEON_PPLL_ATOMIC_UPDATE_EN
939 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
940 | RADEON_PPLL_PVG_MASK));
941
942 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
943 RADEON_PLL_DIV_SEL,
944 ~(RADEON_PLL_DIV_SEL));
945 r100_pll_errata_after_index(rdev);
946
947 if (ASIC_IS_R300(rdev) ||
948 (rdev->family == CHIP_RS300) ||
949 (rdev->family == CHIP_RS400) ||
950 (rdev->family == CHIP_RS480)) {
951 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
952
953
954
955 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
956 pll_ref_div,
957 0);
958 } else {
959
960 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
961 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
962 ~R300_PPLL_REF_DIV_ACC_MASK);
963 }
964 } else
965 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
966 pll_ref_div,
967 ~RADEON_PPLL_REF_DIV_MASK);
968
969 WREG32_PLL_P(RADEON_PPLL_DIV_3,
970 pll_fb_post_div,
971 ~RADEON_PPLL_FB3_DIV_MASK);
972
973 WREG32_PLL_P(RADEON_PPLL_DIV_3,
974 pll_fb_post_div,
975 ~RADEON_PPLL_POST3_DIV_MASK);
976
977 radeon_pll_write_update(dev);
978 radeon_pll_wait_for_read_update_complete(dev);
979
980 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
981
982 WREG32_PLL_P(RADEON_PPLL_CNTL,
983 0,
984 ~(RADEON_PPLL_RESET
985 | RADEON_PPLL_SLEEP
986 | RADEON_PPLL_ATOMIC_UPDATE_EN
987 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
988
989 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
990 pll_ref_div,
991 pll_fb_post_div,
992 (unsigned)htotal_cntl,
993 RREG32_PLL(RADEON_PPLL_CNTL));
994 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
995 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
996 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
997 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
998
999 mdelay(50);
1000
1001 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1002 RADEON_VCLK_SRC_SEL_PPLLCLK,
1003 ~(RADEON_VCLK_SRC_SEL_MASK));
1004
1005 if (is_tv)
1006 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1007 }
1008}
1009
1010static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1011 struct drm_display_mode *mode,
1012 struct drm_display_mode *adjusted_mode)
1013{
1014 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1015 return false;
1016 return true;
1017}
1018
1019static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1020 struct drm_display_mode *mode,
1021 struct drm_display_mode *adjusted_mode,
1022 int x, int y, struct drm_framebuffer *old_fb)
1023{
1024 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1025
1026
1027 radeon_crtc_set_base(crtc, x, y, old_fb);
1028 radeon_set_crtc_timing(crtc, adjusted_mode);
1029 radeon_set_pll(crtc, adjusted_mode);
1030 if (radeon_crtc->crtc_id == 0) {
1031 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1032 } else {
1033 if (radeon_crtc->rmx_type != RMX_OFF) {
1034
1035
1036
1037 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1038 }
1039 }
1040 return 0;
1041}
1042
1043static void radeon_crtc_prepare(struct drm_crtc *crtc)
1044{
1045 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1046}
1047
1048static void radeon_crtc_commit(struct drm_crtc *crtc)
1049{
1050 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1051}
1052
1053static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1054 .dpms = radeon_crtc_dpms,
1055 .mode_fixup = radeon_crtc_mode_fixup,
1056 .mode_set = radeon_crtc_mode_set,
1057 .mode_set_base = radeon_crtc_set_base,
1058 .prepare = radeon_crtc_prepare,
1059 .commit = radeon_crtc_commit,
1060 .load_lut = radeon_crtc_load_lut,
1061};
1062
1063
1064void radeon_legacy_init_crtc(struct drm_device *dev,
1065 struct radeon_crtc *radeon_crtc)
1066{
1067 if (radeon_crtc->crtc_id == 1)
1068 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1069 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1070}
1071
